Handbook of Semiconductor Technology, Volume 2

Handbook of Semiconductor Technology Volume 2 Kenneth A. Jackson, Wolfgang Schroter (Eds.)

@3WILEY-VCH Weinheim . New York . Chichester . Brisbane . Singapore . Toronto

Editors: Prof. K. A Jackson The Universit) of Arizona Arizona Materials Laboratory 47 15 E. Fort Lowell Road Tucson. A 2 85712. USA

Prof. Dr. W. Schroter IV. Physikalisches Institut der Georg-August-Universitat Gottingen BunsenstraDe 13-15 D-37073 Gottingen, Germany

This book was carefull) produced. Nevertheless, authors, editors and publisher d o not warrant the information contained therein to be free of errors. Readers are advised to keep in mind that statements. data, illustrations. procedural details or other items may inadvertently be inaccurate.

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.4catalogue record is available from Die Deutsche Bibliothek ISBN 3-527-29835-5

0 WILEY-VCH Verlag GmhH. D-69469 Weinheim (Federal Republic of Germany), 2000 Printed on acid-free and chlorine-free paper. All rights resewed (including those of translation into other languages). No part of this book may be reproduced in any form - by photoprinting, microfilm, or any other means - nor transmitted or translated into machine language without written permission from the publishers. Registered names, trademarks, etc. used in this book, even when not specifically marked as such, are not to be considered unprotected by law.

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List of Contributors

Dr. Daniel I. Amey DuPont Electronic Materials Experimental Station P.O. Box 80334 Wilmington, DE 19880-0334, U.S.A. Chapter 11

Prof. Thomas F. Kuech University of Wisconsin Department of Chemical Engineering 14 15 Engineering Drive Madison, WI 53706, U.S.A. Chapter 3

Dr. Ken E. Benson Formerly with AT&T Allentown, PA, U.S.A. Chapter I

Dr. Dim-Lee Kwong The University of Texas at Austin Microelectronics Research Center Department of Electrical and Computer Engineering Austin, TX 78712, U.S.A. Chapter 9

Prof. Chun-Yen Chang National Chaio Tung University National Nan0 Device Laboratory 1001- 1 Ta Hsueh Road Hsinchu, Taiwan 30050, R.O.C. Chapter 7 Dr. Kevin G. Donohoe Formerly with Applied Materials Santa Clara, CA. U.S.A. Chapter 6 Prof. Kenneth A. Jackson University of Arizona Arizona Materials Laboratory 47 15 East Lowell Road Tucson, AZ 85712, U.S.A. Chapter 6 Dr. Wulf H. Knausenberger RD Hikuai, via Thames New Zealand Chapter 12

Dr. Juan F. Lam Hughes Aircraft Company Hughes Research Laboratories 301 1 Malibu Canyon Road Malibu, CA 90265-4799, U.S.A. Chapter 8 Dr. Rainer Leuschner Siemens AG Corporate Technology Materials and Manufacturing P.O. Box 32 20 D-91050 Erlangen, Germany Chapter 4 Dr. Wen Lin Lucent Technologies Allentown, PA, U.S.A. Chapter 1

List of Contributors

Prof. Subhash Mahajan Carnegie Mellon University Department of Materials Science and Engineering Wean Hall 331 1 Pittsburgh. PA 15213-3890. U.S.A. Chapter 5

Prof. Simon M. Sze National Chiao Tung University Microelectronics and Information Systems Research Center 1001 Ta Hsueh Road Hsinchu, Taiwan 30050. R.O.C. Chapter 7

Dr. J. Brian Mullin EMC Malvern "The Hoo". Brockhill Road West Malvern. Worcs. WR14 4DL. U.K. Chapter 2

Michael A. Tischler Advanced Technology Materials, Inc. Danbury, CT 06810, U.S.A. Chapter 3

Dr. John M. Parsey. Jr. Motorola Semiconductor Products Sector 2100 East Elliot Road Tempe, AZ 85284. U.S.A. Chapter 10 Dr. Georg Pawlowski Clariant Japan K.K.. BU Electronic Materials Shizuoka. Japan Chapter 4 Dr. William E. Stanchina Hughes Aircraft Company Hughes Research Laboratories 301 1 Malibu Canyon Road Malibu. CA 902654799, U.S.A. Chapter 8

Dr. Terry R. Turner Fourth State Technology 2120 Braker Lane, Suite C Austin, TX 78758, U.S.A. Chapter 6 Prof. John G. Wilkes T Formerly with Mullard Ltd., Southampton, U.K. Chapter 1

Preface

In the past, the ages of man have been labeled by the materials over which we have gained control: the stone age, the bronze age, the iron age. This is surely the silicon age, where the term silicon is meant to imply the most ubiquitous member of the class of materials known as semiconductors. The modern electronic industry is based on the technology of these materials, and the information age would not be possible without their remarkable properties. Although silicon makes up one quarter of the earth’s crust in the form of silicate minerals, its use as an electronic material, based on its semiconducting properties, were not realized until about fifty years ago when techniques for purifying and preparing single crystals of silicon were developed. The driving force behind this advance was the developing understanding of the electronic properties of these materials. During the past fifty years, the use of these materials has expanded to the point where their manufacture is a major component of world commerce, and the electronic products which they enable have impacted every aspect of our daily lives. Semiconductors permeate all aspects of modern society. Computers based on these materials have permitted the increasingly rapid processing and interchange of information which is now incorporated into our daily life styles. In addition to increased access to information, modern computers have changed the way science is conducted, they have introduced new paradigms for mathematics, and they are essential to the developing understanding of how our genes are constructed. The technology on which this development is based is simply impressive. The starting silicon material is, by a significant margin, both the purest and most perfect single crystalline material prepared by man. The fabrication technology pushes the limits of the size of the sub-microscopic features created, the limits of the complexity and of the number of steps involved in the processing, the limits of the purity of the chemicals used in the processing including the water, and even the limits of the cleanliness of the manufacturing environment. The volume on Semiconductor Processing describes this manufacturing technology in some detail. This technology continues to evolve and develop very rapidly to maintain the pace of the ever-expanding speed and power of modern computers and of other leading edge electronic components. I am deeply indebted to the contributors to this volume who took valuable time from their busy schedules to write about this impressive technology which they are deeply involved in developing.

Kenneth A. Jackson Tucson, April 2000

Contents

1 Silicon Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 J. G. Wilkes f , K. E. Benson, W Lin 2 Compound Semiconductor Processing . . . . . . . . . . . . . . . . . 67 J. B. Mullin 3 Epitaxial Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7: E Kuech, M. A. Tischler 4 Photolithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . R. Leuschner, G. Pawlowski 5 Selective Doping . . . . . . . . . . . . . . . . . . . . . . . . . . . . S. Mahajan

11 1 177 265

6 Etching Processes in Semiconductor Manufacturing . . . . . . . . . . 291 K. G. Donohoe, ir: R . Turner, K.A . Jackson

7 Silicon Device Structures . . . . . . . . . . . . . . . . . . . . . . . . C.-Y Chang, S. M . Sze

341

8 Compound Semiconductor Device Structures . . . . . . . . . . . . . . 39 1 W. E. Stanchina, J. E Lam 9 Silicon Device Processing . . . . . . . . . . . . . . . . . . . . . . . . 407 D.-L. Kwong

10 Compound Semiconductor Device Processing J. M . Parsey, Jr:

. . . . . . . . . . . . . 489

1 1 Integrated Circuit Packaging . . . . . . . . . . . . . . . . . . . . . . D. I. Amey 12 Interconnection Systems . . . . . . . . . . . . . . . . . . . . . . . . W H. Knausenberger Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

607 649 683

1 Silicon Processing

John G Wilkes *

Updated by Wen Lin** and Ken E Benson*** . October. 1999 List of 1.1 1.2 1.3 1.3.1 1.3.2 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.5 1.5.1 1S . 2 1S.3 1.5.4 1.5.5 1.6 1.6.1 1.6.2 1.6.3 1.6.4 1.6.5 1.6.6 1.6.7 1.7 1.7.1 1.7.2 1.7.3 1.8 1.8.1 1.8.2 1.9 1.10

* ** ***

2 Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Metallurgical-Grade Silicon . . . . . . . . . . . . . . . . . . . . . . . . . 7 Semiconductor Grade Polycrystal Silicon . . . . . . . . . . . . . . . . . . 11 The Chlorosilane Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 The Silane Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Single Crystal Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 Float-Zoned Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Neutron Transmutation Doped Silicon . . . . . . . . . . . . . . . . . . . . . Carbon and Nitrogen in Float-Zoned Silicon . . . . . . . . . . . . . . . . . 20 Periodic Crystal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Dislocation-Free Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Constitutional Supercooling . . . . . . . . . . . . . . . . . . . . . . . . . . 27 The Incorporation of Carbon and Oxygen . . . . . . . . . . . . . . . . . . . 29 Magnetic Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . . 33 Evolution in Czochralski Crystal Diameter . . . . . . . . . . . . . . . . . . 34 Wafer preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Slicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Edge Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Lapping/Grinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Chemical Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Polishing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 41 Mechanical Damage in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . Oxygen in Czochralski Silicon . . . . . . . . . . . . . . . . . . . . . . . . 46 The Behavior of Oxygen in Silicon . . . . . . . . . . . . . . . . . . . . . . 46 48 The Precipitation of Oxygen in Silicon . . . . . . . . . . . . . . . . . . . . Thermal Donors and Enhanced Diffusion . . . . . . . . . . . . . . . . . . . 52 Gettering Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Extrinsic Gettering in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . 53 56 Intrinsic Gettering in Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Formerly with Philips Components Ltd., Southampton. U.K. Lucent Technologies. Allentown. Pa. U.S.A. Formerly with AT&T. Allentown. Pa. U.S.A.

1 Silicon Processing

List of Symbols and Abbreviations A"

Fourier series coefficient lattice constant (for Si, N" = 5.42 A) a, A0 constant B slice bow depth C concentration CH crystal habit CI concentration in liquid concentration (of oxygen in oxide) in particle CP concentration in solid c, equilibrium solid solubility concentration Cr 5 co initial concentration d diameter D diffusion coefficient activation energy for the formation of a particle of critical radius EC ft cut-off frequency f; mean value off, volume free energy change of a precipitate mv F,, F,, F , magnitudes of the forces generated at the edge during sawing fraction of melt solidified height enthalpy of reaction detector signal interstitial collector - base current Boltzmann constant effective distribution coefficient equilibrium distribution coefficient number of particles number of particles of critical radius fast neutron, thermal neutron number of oxygen atoms i n axial bonds number of oxygen atoms in other bonds bound interstitial oxygen concentration Prandtl number radius radius of the total volume from which oxygen condenses into a precipitate critical radius radius of a final precipitate particle, small compared with R time absolute temperature melting point (Si: 1412°C) half life of radioactive species thickness of a silicon slice

List of Symbols and Abbreviations

temperature difference velocity vacancy velocity of growth intrinsic X-ray signal half width measured X-ray signal half width rocking curve broadening alpha particle absorption coefficient for polarized infrared light parallel to the stress axis absorption coefficient for polarized infrared light perpendicular to the stress axis gamma particle boundary layer thickness strain test sample angle Bragg angle, X-ray reflection Fourier coefficient (with dimensions of inverse length) constant kinematic viscosity surface free energy relaxation time relaxation time constants angular velocity AC ACR ASTM BP CMOS CVD

DC DCS DI DRAM EBE EG FZ HF HI-LO LPCVD MG-Si MOS

NFZ

alternating current advanced carbothermic reduction American Society for Testing Materials boiling point complementary, using both n- and p-type, metal- oxide- silicon device chemical vapor deposition Czochralski material direct current dichlorosilane deionized dynamic random access memory extended bulk epitaxy enhanced gettering float zoned (material) high frequency high temperature - low temperature (heat treatment) low pressure chemical vapor deposition metallurgical-grade silicon metal-oxide-silicon (device) (n-MOS, p-MOS refer to the dopant type structure employed) nitrogen-doped float zone (material)

NTD NTP PPba PPma PPt psi RF rPm SANS SIMS SRAM

TCS TD TIR UHF ULSI UV VLSI

WCA

1 Silicon Processing

neutron transmutation doping normal temperature and pressure atomic part5 per billion ( lo9) atomic parts per million parts per trillion ( I 0”) pounds per square inch radio frequency rotations per minute small angle neutron scattering secondary ion mass spectrometry static random access memory trichlorosilane thermal donor total integrated reading (of bow or warp) ultrahigh frequency ultra large scale integration ultraviolet very large scale integration water classified alumina

1.1 Introduction

1.1 Introduction Silicon today is a commodity, its price subject to all the forces of supply and demand in an intensely competitive market, and this has driven the development of high yield processes for the tight tolerance materials demanded. While discrete and power device manufacture calls for some float zoned, and neutron transmutation doped (NTD) silicon; the worldwide compass of integrated circuit manufacture consumes more than 75% of all the semiconductor silicon produced. The development of the product market distribution is shown in Fig. 1-1, Supply of this material isdominated by Czochralski crystal growth, the operational scale of which has increased from charges weighing a few hundred grams, around 1962, to the current units of 60 kilogram and more.

The evolution of the semiconductor industry as we now know it began in the 1950s, when many of the then large electrical companies became involved in the chemistry and metallurgy of Germanium. Their starting point was GeO,, the dioxide, which had to be reduced to metal powder, melted, zone refined, and crystals grown, before the machining operations which led to discrete devices. Germanium being an expensive rare element, the machining itself generated valuable byproduct sludges which had to be recovered. The extreme purity necessary led into problems in chemical and physical analysis, materials of containment, and in general chemical engineering. In retrospect, very few of these electrical companies possessed either the resources or the experience needed for such work; so when, only shortly afterwards, silicon was

300

250

! s1

200

150

d m 100

Z z z z YEAR

Figure 1-1. Global semiconductor sales forecast (After Winegarner).

1 Silicon P r o c e s s i n g

introduced, almost all of them took the opportunity to withdraw from the chemical end of the business. Silicon is one of the most abundant elements, and so the sludges are of no economic importance. Henceforth their starting point became the ultrapure polycrystalline silicon from which they made their own single crystal. Withitime, the number of companies doing even this has steadily declined. until today few of the electronics manufacturers have any involvement in bulk material processing. Indeed most purchase polished slices, cleaned and packaged, furnace ready, for fabrication lines. A number of the device makers still carry out epitaxy and, to that extent alone, retain a residual materials activity. Today’s ultra large scale integrated circuits (ULSI) lithographic feature sizes have been reduced to 0.18 pm (anticipate to be in 0.1 p m region by year 2006 or sooner) as

projected by the National Technology Road Map of Semiconductor. These circuits use multi-level metal interconnects to able the production of highly complex circuits of steadily increasing chip size. Consequently, as the number of chips per wafer decreases, so there has been an accompanying call for ever larger wafer diameter - to reduce perimeter wastage, and to improve the fabrication line yield and throughput, as shown in Fig. 1-2 - hence the continuous need to scale up crystal size, this demanding extremely heavy investment. This scaling has not been at the expense of quality - i n fact quite the reverse. As more has been learned about the relationship between materials properties and the device parameters, so the demand for better performance from the silicon has grown. If one compares a typical purchasing specification of even the mid 1970s, with that in

100,000

10,000

1,000

100

Year Figure 1-2. H i m r i c a l and projected wafer size trends (Source: VLSl Research, SEMATECH. 13001).

1.2 Metallurgical-Grade Silicon

force today for a similar application endproduct, the increase in the number of parameters specified, and the narrowing of virtually all tolerances, is marked. Factors contributing to this position are several. Fine geometry lithography of the ULSI fabrication requires wafer local flatness to match the design rule according to guidance of the National Technology Road Map of Semiconductors (NTRS - 1997). Control of particles of sizes down to one half of the design rules and wafer surface metal contamination at a level near the detection limits (NTRS - 1997). Research into the behavior of oxygen precipitation in bulk silicon under device thermal cycles has led to the introduction of new specification parameters, new crystal growth and wafer processing methods, and to the concept of “crystal engineering”. Controlled oxide precipitation in slices is carried out, prior to their use in fabrication lines, to provide sites for the intrinsic gettering of unwanted fast diffusing electrically deleterious impurities, away from the surface layer where the MOS devices are made. Residual mechanical damage sites after the crystal machining provide similar extrinsic gettering sites. For many applications in “crystal engineering” today, combinations of controlled mechanical and oxide precipitate gettering are used together to achieve optimum performance from the silicon, to match the particular device requirements in MOS, CMOS, and bipolar configurations. To achieve this matching it is necessary to examine the total thermal inventory of the multistage fabrication process, in order to select the most appropriate structure. As semiconductor technology continues to advance, the IC design rule is approaching 0.1 p m by 2006, if not earlier. In parallel with the design rule decrease, the increased circuit design complexity results in

increased chip size. This has been the major driving force for increased wafer diameter for the last twenty five years, that is, to increase the required number of IC’s per wafer in order to reduce IC manufacturing cost. Figure 1-2 shows the wafer diameter evolution in the industry since wafer diameter was about 1.5” in 1960s. In the 1990s, 200 mm is the main stream, which was initiated in the late 1980s. In 1995, the development of a 300 mm wafer was begun, targeting for IC manufacture in the 0.25 pm/ 0.18 p m design rule generation. Concurrently, Japan has some development projects on the 400 mm wafer era technology.

1.2 Metallurgical-Grade Silicon The source of the raw silicon used for semiconductor purposes is metallurgicalgrade silicon, manufactured by the carbothermic reduction of silica in an electric arc furnace. Silica, occurring naturally as quartzite, in vein quartz, and in sandstone, and as unconsolidated sands and gravels, is a common mineral with worldwide distribution. Silicon, after oxygen, is the second most abundant element, but does not occur naturally in its elemental form. Silica, either free as in quartz or in the many forms of silicate igneous rocks, constitutes about a quarter of the earth’s crust. However, the silicon metal producers demand an ore purity of better than 99% Si02, and also place tight restrictions on the allowable concentrations of various impurities present - in particular arsenic, phosphorus, and sulfur so that often only a small fraction of an ore deposit meets their purity specification. Geologically washed out gravel from river bed deposits, and similarly leached out quartz sands, are a source of very high purity silica. Vast deposits, yielding quartzite ore of the highest purity available today,

1 Silicon Processing

have been discovered in Arkansas, U.S.A., from which monocrystals weighing several tons apiece have been displayed i n exhibitions worldwide. In the traditional electric arc furnace process, which has been used for most of this century, chunky quartzite is reacted with carbon, as the reductant, in the forms of coal, co*ke, or charcoal. which can be a source of at least an order of magnitude greater impurity levels than present i n the silica. The overall reaction appears simple: SiO,

+ 2 C -+ Si + 2 C O

(1)

However. as discussed by Healy (1970), the actual reaction sequence in the different temperature zones of the furnace is far more complex than this, as set out i n the schematic diagram of Fig. 1-3. ( a ) Towards the bottom of the furnace, in the region of the arc between the electrodes where the temperature can exceed 2000 "C. silicon is produced by the reaction

S i c + SiO,

+ Si + S i 0 + CO

(2)

(b) Above this, at a somewhat lower temperature, around 1700-1500"C, the rising byproduct gases react to form the intermediate product silicon carbide by Si0 + 2 C

S i c + CO

(3)

(c) Nearer to the top, where the temperature falls below 150OoC,as is expected thermodynamically, the reverse reaction predominates: S i c + CO -+ SiO,

(4)

The input materials are fed into the top of the furnace, while liquid silicon is periodically tapped from the bottom and cast into ingots. If this casting is carried out directionally, under the conditions referred to as normal freezing, impurity redistribution can be used to effect some purification, following the well equation by Pfann (1952, 1958):

For the arc process to run properly, it is essential to maintain porosity throughout the charge to allow uniform S i 0 and C O gas

Figure 1-3. Schematic diagram of the submerged-electrode electric arc furnace for the production of metallurgical grade silicon.

1.2 Metallurgical-Grade Silicon

flow, and to permit the escape of CO, some SiO, and H,O from the top. To assist this wood chips may be included in the feedstock, and the silica must be of a form which does not readily crumble during initial heating in the upper part of the furnace, which could lead to premature fusion and crusting over, with the risk of a dangerous pressure buildup within the charge. Clearly the carbothermic reduction of silica is not a trivial process. Crossman and Baker (1977) have given a very interesting comparison of the impurities present in typical quartzite and the carbon used, related to the spectrographic analysis of more than 2000 tons of the metallurgical-grade silicon produced. Their data, collected into Table 1- 1, indicated total impurity levels in the quartzite of around 750 ppma; in the carbon 8000 ppma, and in the resulting metallurgical-grade silicon (MG-Si) 4000-4500 ppma. Within this analysis the two predominant impurities are seen to be aluminum and iron, largely originating from the carbon, and taken together accounting for over 80% of that in the silicon product. Since these results referred to

Table 1-1. Impurities in silica, carbon, and metallurgical-grade silicon. Impurity

B Cr Fe

P Others Mn Ni Ti V a

Weighted;

Quartzite (ppma)

Carbona (ppma)

MG-siliconb (pema)

620 14 5 75 10 10

5500

15702580 4 4 2 13 137k 75 2070+5 I O 282 6 -

40 14 1700 140

600

7 0 k 20 4 7 2 28 163k 34 l o o k 47

average value + standard deviation.

MG-Si to be used for the production of semiconductor grade polycrystal silicon, the importance of the purity of the carbon source is underlined. Recent developments have focused on improved and cleaner processes, better quality carbon, and efforts to develop quartz sands as an alternative low cost and high purity source. Maintaining charge porosity constitutes the most serious restriction in the operation of the submerged arc furnace, and much attention has been focused on how to meet, or circumvent this problem. In work aimed to reduce drastically the impurities in arc furnace silicon, Dosaj et al. (1978) working at Hemlock Semiconductor Corp. U.S.A. reported using a high purity silica source together with carbon black powder, pelletized with pure sucrose binder, to obtain MG-Si at 99.99% purity. Although the carbon content of the material was relatively low, this particular element tends to be more persistent through the later stages of semiconductor silicon manufacture, and therefore recently there has been interest in exploiting the lower boron content of carbon obtained from petroco*ke. The pelletization of upgraded quartz sands can provide very pure silica in a suitable form. This material then has to be agglomerated to lumps, either separately or mixed with carbon powder. This approach has been studied by several groups, including Elkem A B , Norway, the largest European silicon metal producer, but until now it has only been taken to a development stage. The Siemens advanced carbothermic reduction (ACR) process has recently been described by Aulich et al. (1985), in which high purity pelletized quartz sand is reduced by carbon granules, prepared from carbon black briquettes, which had been leached with hot HC1 to a purity comparable to that of the silica. Since in an arc furnace about 10% of the carbon comes from the elec-

1 Silicon Processing

trode, the effective carbon impurity level was somewhat higher. Nevertheless a substantial overall impurity reduction was achieved. A more radical approach to overcoming the porosity problem has been the application of DC plasma-arc techniques to the production of ferrosilicon alloys and silicon metal. The most important feature of the plasma-arc furnace here is that it can process ore fines directly, without prior briquetting or pelletization. The potential of this route is supported by the extremely efficient plasma purification of normal MGSi, by factors of up to 100 000, reported by Armouroux et ai. (1986). The great evolution of heat from the oxidation of aluminum forms the basis of the Thermit process for the reduction of refractory oxides, such as Cr,03, and MnO,. By the application of this technique to silicon, an entirely new manufacturing route has resulted from the extensive work by Dietl and Holm [see, e.g.. Dietl et al. (1981) and Dietl and Holm (1986)l at Wacker Heliotronic, Germany, on the aluminothermic reduction of quartz sand in a liquid flux system (CaO-SiO,) at a temperature of 16001700°C: 3 SiO,

+ 4 A1 -+ 3 Si + 2 AI,O,

(5)

The flux serves simultaneously as a solvent for the byproduct aluminum oxide, and as a liquid-liquid extraction medium. As the silicon is released it is immiscible in the flux and so separates. Since the silicon is of lower density, if floats as the upper layer and at intervals can be poured off into a mold. where controlled normal freezing further separates low segregation coefficient impurities. The silicon made by this novel semicontinuous process is of relatively high purity compared with normal MG-Si. It is characterized by low boron and carbon levels. and after subsequent grinding, acid

leaching, and liquid-gas extraction, provides a material that is suitable for solar-cell applications. During the past decade, the most important economic trend in silicon metal production has been abandonment of the earlier small scale multi-unit plants, having limited productivity, for the use of very much larger electric arc furnaces, commonly dedicated to a particular product, which operate with lower unit costs. A modern commercial submerged-electrode arc furnace built in a three phase, three electrode configuration, each of these 1.25 m in diameter, and driven from a 24 MW power source, can produce 8000- 10 000 t/a metallurgical-grade Si at an energy consumption of 12-14 kWh/kg. The demand for metallurgical-grade silicon is dominated by the iron-steel and aluminum alloy industries, which require 98% purity metal. A somewhat higher quality, of 99%+ purity, is required for conversion into chlorosilanes, the key intermediates in the synthesis of organo-silicon compounds for the silicone industry, leading to products such as oils, resins, lubricants, and water repellants. Although the semiconductor industry wants the highest purity it can obtain, the amount needed still represents only a very small fraction of the world’s output. For example the global production of MGSi i n 1986 was just under 600 000 t, from which the organo-silicones consumed about 20%. By contrast, in that same year the production of semiconductor-grade, ultrahigh purity, polysilicon reached about 6000 t representing a consumption of less than 2% of total MG-Si output, and, significantly, only a fraction of the capability of a singlearc furnace. Western Europe accounts for over half the world capacity, led by Elkem, Norway, and Pechiney, France at 100 000, and 75 000 tons per annum, respectively. Thus, in summary, while the manufacturers of semiconductor silicon can have only

1.3 Semiconductor Grade Polycrystal Silicon

limited influence over the quality of metallurgical silicon, there have been improvements in this product. While these have probably been driven more by the much larger organo-silicon purity needs, some of the companies in the MG-Si industry have established strong links in the semiconductor market, and their contributions are of greater significance when set against the global background of silicon metal production.

1.3 Semiconductor Grade Polycrystal Silicon As shown in Table 1-1, metallurgicalgrade silicon of 99%+ purity contains, in addition to carbon, the major impurities iron and aluminum at more than lOOOppma, various transition and other metals - titanium, chromium, etc. -at around 100 ppma, and lesser impurities, including boron and phosphorus, at lower levels of 10's ppma. Today, dopants and carbon in semiconductor grade polysilicon are reduced to parts per trillion (ppta: 1 in lo'*) levels. For the producers this extremely demanding task has to be achieved economically, to meet the very competitive market pricing pressures which dominate the industry. Early polysilicon plants were built with a capacity of around 100 t/a, but today, to meet price targets, the latest plants are built with capacities around 1000 tons, or more.

MG-Si

Pure anhydrous HCI

Two main routes are available for the production of semiconductor-grade silicon from MG-Si; either via chlorosilanes (principally trichlorosilane, SiHCl,), or via silane (SiH,). The former has been predominant since the late 1950s. 1.3.1 The Chlorosilane Route

This process, developed at Siemens (Bischoff, 1954), rapidly superceded the earlier SiCl,/Zn method, which had been the principal silicon source until that time. There are three basic key steps in the process: (a) Reaction between powdered MG-Si and hydrogen chloride gas in a fluidized bed reactor to form trichlorosilane (TCS). (b) Fractional distillation of the TCS to provide it in an ultrapure, ppba, form. (c) Reduction of the ultrapure TCS by hydrogen in a chemical vapor deposition (CVD) reaction to yield the desired product - semiconductor-grade polycrystalline silicon. The fundamental, reversible, reaction is Si,,,

+ 3 HCl,,,

fluidized bed

0 CVD

The layout of a fluidized bed unit is shown in Fig. 1-4. However, again the actual reactions are more complex, and between this

H,, HCI

grit

J r

T Heater

Condenser

300-4OO0C

Heating

Cooling

SiHCI,,

SiCI,

Figure 1-4. Layout of a fluidized bed reactor. The high degree of recycling in a chlorosilane plant is similar to that in a silane plant see also Fig. 1-5.

1 Silicon Processing

and the later stages of the process there is considerable recycling. The overall flow design of the plant, the efficient use of heat exchangers, and precise control of the recycling of intermediates are crucial factors in the operating costs. The reaction between powdered silicon and anhydrous hydrogen chloride gas in the fluidized bed, held at 300 to 400 "C is highly exothermic, producing a mixed output which contains about 90% of the wanted SiHCI, [Boiling point (BP): 3 1.8 "C], about 107~SiC1, (BP: 57.6"C), and also a little dichlorosilane, SiH2C12 (BP: 8.5"C); together with hydrogen, unreacted HCI, and some volatile impurity metal chlorides. For this conversion high purity anhydrous HC1 gas is essential, and a complex purification plant is needed to guarantee the €1 ppma level specified for this stage. Phosphorus trichloride (BP: 76"C), and boron trichloride, which is a gas at room temperature, are the two principal electrically active impurities carried over from the MG-Si; arsenic, as AsCl, (BP: 130°C) is also present to a lesser degree, together with small amounts other volatile metal chlorides, such as AlCI,; but the fluidized bed stage does reduce the incoming impurity levels quite substantially. At the next stage conventional high performance multiplate fractional distillation is employed to refine the TCS, separating i t from other chlorosilanes and Si-H-C-Cl species present, and reducing the undesirable metals to ppba levels. The fractional distillation is backed up by the use of selective adsorption techniques to reach the very highest purity possible. This stage is pure chemical engineering, akin to that to be seen at any petrochemical refinery. Provided that they are kept completely dry, chlorosilanes, and also anhydrous hydrogen chloride, are chemically inactive in both liquid and gaseous form. and therefore can be moved and

transported in conventional carbon-steel pipelines and tanks, but special valves and pumps are needed to maintain a totally leakfree environment. Thus the final ultrapure TCS is relatively easy to handle onwards to the next, silicon deposition, stage. The quality of the semiconductor-grade polysilicon obtained from TCS is seen in Table 1-2, which shows the low levels of all impurities typically achieved. There has had to be much development of new analytical techniques in order to be able to quantify these impurities. Even using the highly sensitive method of ultraviolet spectroscopy, all metals are normally at a level below their respective detection limits. Special grades of even higher purity are available, for example, for epitaxial deposition. At this level often the only way to discriminate between two source materials is by their comparative performance under rigorously controlled conditions. When the data in Table 1-2 are compared with earlier published results, as for example those given by Crossman and Baker (1977) (their studies of MG-Si have already been mentioned). The third stage of the process is silicon deposition, where the Siemens chemical va-

Table 1-2. Impurities in semiconductor-grade polycrystalline silicon* Impurity

Concentration

Carbon Oxygen Donors Acceptors

< S O ppba not quoted <SO ppta < I O ppta

Bulk Metals (Fe. Cr. Ni, Zn and Cu)

< O . l ppbw (cumulative)

Surface Metals Na Other metals individually

<0.1 ppbw

* Data represent I997 capability of major polysilicon suppliers

1.3 Semiconductor Grade Polycrystal Silicon

por deposition technique is used worldwide by all the major producers. Again today’s reactors are much larger, but the configuration is still essentially that first proposed in the mid 1950s. Two thin rods of ultrapure silicon, about 5 mm in diameter, and, today, up to 2-3 m in length are attached to heavy electrodes at their lower ends, while at their upper ends they are joined together with a shorter bridging piece of silicon thin rod in an inverted “U” configuration. By passing an electric current through the silicon, the rods are heated to a temperature of about 1100°C in a trichlorosilane-hydrogen mixture, when reaction at the hot surface deposits ultrapure silicon. The process is continued for some 200-300 h until the rods reach a diameter of 150-200 mm. The preferred input material is TCS, rather than SiCl,, which was used in the 1960s by some companies trying to evade the Siemens patent, because the reaction using TCS proceeds at a lower temperature and a faster rate. Again more complex than given by Reaction (6), the intermediate high temperature compound silicon dichloride, SiCl,, plays an important role, both in the adsorption-deposition step at the surface and in the formation of byproduct SiC1,. Since chlorosilane epitaxy uses the same process to deposit thin single crystal silicon layers, this reaction has been studied extensively, the work of Bloem, Gilling, and their coworkers over a number of years being notable (Bloem and Gilling, 1978; Bloem and Classen, 1980, 1983/ 1984). In such a deposition process, any hom*ogeneous nucleation, followed by particle growth in the gas phase, would lead to powder deposits downstream all over the system, which would be disastrous. The TCS process operating parameters are chosen to ensure a heterogeneous surface controlled reaction. Under these conditions the rate of deposition with time (kg/h) is directly pro-

portional to the surface area, rising as the rod diameter increases. Clearly it is desirable to grow the rod to as large a diameter as possible, and hence the scaling up of these reactors has contributed very markedly to reducing process costs, as does recycling. Only a fraction of the TCS fed through the reactor cells is converted to silicon. The outgoing gas contains unreacted SiHCl,, SiCl,, HC1, H,, and other lesser constituents, all of which are separated, repurified as necessary, and fed back to the appropriate earlier stage, the HCl, for example, being returned right back to the first fluidized bed stage. Some of the SiC1, byproduct from the overall operation is not recycled but finds a market, having various uses, for some silicon and silicone products, and more recently in the manufacture of optical fibers. In summary, while there are operating complications, the Siemens process, in the three basic steps of dissolution, highly efficient distillation, and redeposition, converts MG-Si of ppma purity to ultrapure ppba semiconductor silicon, in a very cost-effective manner, and far superior to the earlier SiCl,/Zn Dupont process (Lyon et al., 1949) that it displaced completely. By 1959 the laboratory growth of undoped float zone silicon crystals was being reported which had near intrinsic resistivity values, in excess of 100 000 R cm (Hoffman et al., 1959). Today’s analytical data for typical electronic grade polysilicon, collated from latest vendor specifications, as shown in Table 1-2, reflect the steadily continuing quality improvements, linked to those of its precursor trichlorosilane - the material which has underpinned the advances in the device field for over two decades.

1.3.2 The Silane Route Although research into the potential semi-conductor uses of silane, SiH,, started

1 Silicon Processing

early, silance became commercially important only in the later 1960s when its planar fabrication applications emerged, used in the chemical vapor deposition of silicon dioxide and silicon nitride dielectrics, and for polysilicon interconnect layers in devices. Much of this silane has been made using the lithium hydride, high temperature flux LiCl(45%)/KC1(55%)electrolytic cell system (Sundermeyer, 1957), in which the key reaction at 390-430°C is SiCl,

+ 4 LiH -+

SiH,

+ 4 LiCl

(7)

The merchant market demand for silane for these purposes reached about 110 tons in 1986 and, following the continuing rapid silicon integrated circuit device expansion, has since more than doubled. However, here we are concerned with the use of silane as a route to bulk polysilicon. For many years Komatsu Ltd., Japan, has operated a silane plant (Yusa et al., 1975; Taylor, 1987) which uses a process based on the reactions

Mg?Si + 4 NH'$C1

NH3(llq 1

'S i H 4 +

(9)

+2 MgCl? + 4 NH3

SiH,

+ Si + 2 Hz

(10)

Powdered magnesium and silicon are melted together to form the silicide, which is then reacted with ammonium chloride in a liquid ammonia solvent at a temperature of 0°C. Since boron forms a stable BH,: NH, addition compound, it is reduced to extremely low levels, 0.01-0.02 ppba, at this stage. Phosphorus, as phosphine, PH,, is a much more difficult impurity to remove from the output silane gas. Therefore the next step is multiplate fractional distillation, under reduced pressure at very low temperature, below the boiling point of silane, -1 12°C. Since silane forms a sponta-

neously explosive mixture with air, the equipment is complicated and expensive, and the product could still contain too much phosphorus. Further purification by selective adsorption onto modified A-type zeolites, at a temperature of -20 to -3O"C, removes PH, to extremely low levels, well below 0.01 ppba (Yusa et al., 1975). Work on improved modified zeolite adsorbants has continued, for example, Showa Denko KK (1984). The final stage of deposition, carried out in equipment as described above for the Siemens process, but operated at a somewhat lower temperature, around 900"C, in order to avoid unwanted hom*ogeneous reaction, is a simple thermal pyrolysis, requiring no other reactant, unused silane and hydrogen being the only byproducts for recovery. The polysilicon produced is of a very high quality, and the premium grade silicon product finds its use in the market for high-resistivity float-zoned, and neutron transmutation doped single crystals (see Sec. 1.4.2). Within the U.S. Department of Energy funded solar energy program of the mid 1970s, various potential routes to silicon were explored or re-examined. Examples include the reduction of SiCl, by Na or Zn, and routes involving SiF,. These have been well reviewed by Diet1 et al. (1981). Out of this program one process has reached full maturity, in a plant that added significantly to the world's semiconductor silicon capacity. The Union Carbide, Moses Lake, Washington, plant produces silane as the precursor to deposition, but combines the merits of both TCS and silane in the intermediate stages (Taylor, 1987). Manufacture again starts from MG-Si fed into a fluidized bed reactor, but operated quite differently from that described in the Siemens process, in that the silicon is mixed with large amounts of recycled SiCI,, and hydrogen in the reaction 3 SiCI,

+ Si + 2 H, + 4 SiHCI,

(1 1)

1.3 Semiconductor Grade Polycrystal Silicon

Operated at a high pressure of 500 psi (=35 bar) and at a temperature of 5OO0C, this process is nearly thermoneutral, and yields a single-pass efficiency of 30-35%. It is quite unlike the highly exothermic Reaction (6) of the Siemens system. This stage is followed immediately by distillation to separate out and recycle the excess SiC1,. The next two stages, leading to silane, are successive catalytic disproportionation steps:

2 SiHCl,

+ SiCl, + SiH2C1,

(12)

to dichlorosilane (DCS) and then

2 SiH2C12+ SiC1, + SiH,

(13)

both are carried out at a pressure around 50 psi (=35 bar) and at a temperature in the range of 6O-8O0C, using a tertiary amine ion-exchange resin catalyst; and each achieves a single-pass efficiency of around IO-12%. Again, as shown, the components are separated by distillation between the stages, the silane being finally purified by cryogenic fractionation. As revealed by the

stage single-pass efficiency factors, there is a high degree of recycling throughout the process. The schematic flow diagram of the Union Carbide process set out in Fig. 1-5 shows the high level of feedback between stages. The development of the purification methods required to achieve the highest purity silane has demanded improved and new analytical techniques, such as deep level transient spectroscopy and photoluminescent spectroscopy, where sensitivities down to the parts per trillion (ppt) level are now routinely reported (Taylor, 1988). The final pyrolysis at 900°C is as described above, with the byproduct hydrogen, and unused SiH, (not shown) being recycled. The demand of polysilicon has steadily increased in the 1990s in response to the drastic increase in semiconductor devices. The trend is expected to continue. Figure 16 shows the projected polysilicon production, including all silane, chlorosilane and granular processes, as compared to the demand.

H, recvcle SiHCI, recycle

I Metallurgical-grade silicon

Fluidized bed reactor and distillation

Disproportionation and distillation

-SiH2CI, I

SiH,C12 recycle

’

Disproportionation and cryogenic distillation

3 I[

Pyrolysis deposition reactor

1 Silicon Processing

40000

35000

0PRODUCTIONVOLUME ----t

DEMAND

30000

25000

20000

2 15000

10000

5000

1994

1995

1996

1997

1998

1999

2000

2001

2002

2003

YEAR

Figure 1-6. Polysilicon production volume vs. demand. Source: Dataquest

1.4 Single Crystal Silicon The manufacture of single crystal silicon from the ultrapure polycrystalline material is mainly by large vendors, who produce polished silicon wafers and epitaxial wafers. There are, however, a few device companies who produce single crystals and polished waferdepi wafers as starting materials. Two techniques are used to manufacture monocrystalline silicon - free float zoning, and Czochralski crystal pulling from a silica crucible. The material produced has different properties, and very different device applications. Today float zoning addresses a much smaller part of the market, and is discussed first.

1.4.1 Float-Zoned Silicon

Floating zone refining was introduced independently by several groups of workers in the early 1950s (Keck and Golay, 1953; Theurer, 1952, 1956), and very quickly became a widely used crystal growth technique. In float zoning a cylindrical rod is held vertically and heated in argon by a radio frequency induction coil, to establish a molten droplet between the lower end of the rod and a single crystal seed rod mounted coaxially beneath, the two rods being rotated in opposing directions. The molten zone, retained in place between the polycrystal and seed rods only by surface tension, is then moved gradually upwards through the length of the polycrystal, converting it to monocrystal form.

1.4 Single Crystal Silicon

The input material is a 2-3 m long cylindrical rod, obtained by limiting the final diameter at the deposition stage. The surface of an as-deposited rod has a coarse granular structure on a millimeter scale, which is removed by rotary diamond grinding to a tight diameter tolerance. The rod is then deep etched to a bright smooth finish, to ensure that all the damage and impurities introduced into the surface by the machining are removed, and also to reach the diameter required for the zoner. Finally the rod is washed in very high purity deionized water before zoning. As already stated, the silicon deposition rate in the polycrystal reactor is proportional to diameter, and so limiting the process to making smaller diameter material increases costs and reduces the reactor plant capacity. Only true straight rod sections can be used for zoning, and so, when the additional machining and preparation are taken into account, the input material is more expensive than the simple broken poly lump suitable for melting in a crucible. Float zoning is an inherently difficult technique because of the problems in controlling such a free molten zone. Compared

m +

h L u

-Counter

& r

to Czochralski pulling, where melt convection can be influenced by the heater shape and its position with respect to the melt, and by baffle design, and the crucible and crystal rotations can be chosen at will, in the zoner there are far fewer degrees of freedom to chose from to adjust its performance. A great deal of work has centered on induction coil design, and the use of auxiliary coils, to set the desired temperature gradients. Hence developments to reach larger diameters lagged behind the availability of equivalent Czochralski material. It was found almost impossible to maintain a large diameter molten zone whose volume was such that surface tension alone could hold it in place without the liquid falling out. The problem was eventually solved by a new approach, known as the “needle-eye’’ technique (Keller, 1959), see Fig. 1-7. During the rod preparation machining stage, described above, a modification was introduced whereby, after the rod had been ground to a parallel cylinder, its bottom end was further ground to a tapered cone, as matching section to the seed. The RF induction coil was made at a smaller diameter

rotation-

e Polycrystal c i rod

c 0 W .-c>

- 0

@RF

* “W

.-0 W

heater coil :centricity

L W

Molten zone

j s i n g i e crystal-

Figure 1-7. Floating zone growth configurations. (a) Keck, small diameter; (b) Needle-eye, large diameter.

1 Silicon Processing

than the machined rod, so that as the zone was established and passed up through the polysilicon rod, with the coil now just inside the rod diameter, the smaller molten zone volume involved could then be successfully moved through the length of the rod without prematurely falling out. Establishing this as a reliable production procedure took much effort, and the design of highly specialized zoners. By this crucible-free technique standard crystal product, zero dislocation density silicon up to 150 mm diameter, is made at a purity close to that of the input polysilicon. Resistivities are available up to 5000 R cm, and in limited amounts even higher, well beyond that attainable by Czochralski growth. The control of doping to specific resistivity bands in float zoned (FZ) silicon is approached in three ways. Firstly, by gas phase doping during crystal growth, adding diluted phosphine, PH,, or diborane, B,H,, to the argon gas flow through the zoner, a wide range of both n- and p-type specifications can be made. The higher resistivities are more difficult to meet, and the tolerances quoted get wider. The equilibrium segregation coefficients for boron and phosphorus in 4licon are 0.8 and 0.35, respectively. and so doping uniformity, both axially and radially, is somewhat easier to achieve with boron. The second doping method used is only available to the polysilicon producers. The thin rods used to construct the inverted "U" structures. for the reactors in which the silicon deposition occurs, are made by fast pulling from a pure silicon melt. By adding phosphorus or boron to the melt, doped thin rods can be made to various specifications and stocked, to be used later when the deposition rods are planned for float zoning. Then as the molten zone is passed through the polysilicon rod the dopant in the core is released. Very precise resistivity control

can be achieved by this method, with high run-to-run reproducibility. The third method, only possible for phosphorus, n-type, material, is neutron transmutation doping (NTD) which has become very important for power applications.

1.4.2 Neutron Transmutation Doped Silicon By float zoning undoped material under very clean conditions crystal can be produced in which the resistivity is of the order of 5000 R cm or greater, and with a very low residual phosphorus and boron. If this ingot is placed into a nuclear reactor, transmutation doping generates phosphorus in an extremely uniform distribution, avoiding the growth striation phenomena common to both the float zone and Czochralski growth methods, to be discussed later. This method is particularly suitable for making the high resistivity silicon required for power device applications, where the other doping techniques cannot match NTD material in its ability to meet very close tolerances. Normal elemental silicon consists of three stable isotopes with abundancies as: "Si '9Si 3OSi

92.21% 4.70% 3.09%

The possibility of doping silicon by transmuting the "Si isotope into 3'P was first recognized by Lark-Horowitz (195 1). Later, Tanenbaum and Mills (1961) made detailed experiments to verify that the scheme was potentially useful, but this work was dormant until when Herrmann and Mucke (1973) published their power device study. Since then the major developments have taken place, leading to a series of international conferences and many papers on this sole topic.

1.4 Single Crystal Silicon

The principal nuclear reaction upon which the whole process depends is

The stable 30Si isotope captures a thermal neutron to form 31Si with the emission of Frays. For this isotope of natural abundance 3.09%, the capture cross-section for cm2, or a thermal neutron is 0.1 ~xIO-~O 0.1 1 barn. In its turn 31Siis unstable and decays with a half life of 2.62 h to the stable phosphorus isotope 31Pwith the emission of an electron of energy 1.47 MeV. During neutron irradiation other nuclear reactions occur, some of which must be taken into account: 28

Si (nt, '13 + 2 9 ~ i

(15)

and 2 9 ~ (nt, i '13

+3 0 ~ i

The thermal neutron capture cross-sections for these are 0.08 and 0.28 barn, respectively, and the only real effect on the process arises from ingot heating by the emitted Frays. However, two other reactions occur, which are much more important: 'OB

(nt, a) + 7 ~ i

(17)

In this reaction a total energy release of 2.5 MeV is associated with the a and lithium particles, which leads to considerable short range lattice damage. Boron has a very high thermal neutron capture cross-section of >755 barn, but, provided the boron concentration in the silicon is kept low, the effect is small. The most serious side reaction in the process is 31

p (nt,

r )+32

~ , , ~ = 1 4 . d3

)

32S+ (18)

Since the capture cross-section here is only 0.2 barn the amount of sulfur produced is minute in doping terms, but the long half

life for the decay of 32Pcan impose restrictions on the handling of low resistivity NTD silicon. All the reactions so far have referred to thermal neutrons, that is, neutrons which have already been scattered by sufficient collisions within the pile that their energy has reached thermal equilibrium with the medium before intersecting the silicon. Such neutrons, at room temperature, have an average energy of only 0.025 eV and a velocity of 2200 d s . However, fast neutrons in the pile, with energies in excess of 1 MeV, also reach the silicon. These give rise to much of the lattice damage generated during transmutation doping, and are also responsible for reactions of the type 28Si (nf, a) + 25Mg

(19)

producing a high energy a-particle. Even without reaction, the head-on collision of a 1 MeV neutron with a silicon atom will knock out about 200 silicon atoms from their lattice sites. Thus the slow-to-fast neutron ratio in the nuclear reactor is critical, and it is for this reason that heavy water reactors, with slow-to-fast ratios around 1000: 1 (a much higher ratio than available in light water and other reactors), have proved to successful for NTD processing. The subject of neutron irradiation damage has proved to be a matter of great complexity, beyond the scope of this chapter. Much lattice disarray is introduced, immediately after irradiation high resistivity values are found, and at this point most of the phosphorus formed is interstitial. Therefore the post-irradiation annealing process is crucial and has been studied in depth. The resistivity values, expected from the total reactor neutron flux, are fully realized after about 1 h at 600°C; however, defect studies indicate the need for a higher temperature, and poor minority carrier lifetime has been a problem (Meese, 1978). The producer's

1 Silicon Processing

postanneal processes, which at the introduction of NTD products were at moderate temperature, sometimes relying on the high temperature semiconductor fabrication to complete the anneal, subsequently moved to higher temperatures and more complex time- temperature schedures.

1.4.3 Carbon and Nitrogen in Float-Zoned Silicon For many years it was thought that any residual carbon in silicon was of little importance; it is an isoelectronic group 4 element. it occupies substitutional sites in the lattice, and silicon carbide is an insulator. The first indication of device linked effects came when Akiyama et al. (1973) reported a correlation between high carbon concentrations, reduced breakdown voltage, and increased reverse current leakage i n rectifier diodes. Because this work used silicon with a very high carbon level (between 1 and 2xIOl7 atoms/cm3) close to the solid solubility limit, and only appeared as a short communication, its significance was generally overlooked at the time. Carbon was not listed in most purchasing specifications. The common requirement of trichlorosilane for organosilicon and semiconductor use has already been noted in Sec. 1.2, and many of the world’s polysilicon plants are cosited with, or close to a silicones plant. Thus, when in mid 1975, accidentally and undetected, a quantity of high-carbon float zone silicon reached device lines, serious yield problems were met in rectifier, thyristor, and power transistor manufacture. Subsequent research showed that, while not affecting the breakdown voltage, lower levels of carbon still degrade the reverse leakage, as is shown in the plot of Fig. 1-8. Recognizing a severe problem, polysilicon producers made major plant overhauls to remove carbonaceous sources from pumps,

Carbon concentration latoms/cm3)

Figure 1-8. Rectifier diode failure as a function of carbon concentration: 0 breakdown voltage; x reverse leakage current. Note that, even when the breakdown voltage has been restored, leakage effects persist to much lower carbon levels. The dashed vertical line marks Ce,*the carbon solid solubility saturation value.

valves, glands, etc., set new low carbon operating standards, and instituted strict test procedures - in single crystal the substitutional carbon has an infrared absorption at 16.6 p m (605 cm-’) measured by differential (double-beam) spectrophotometry, ASTM Standard F123. Today carbon levels are rigorously controlled by all silane, TCS, and polysilicon producers, to ensure final silicon levels below around 2 x 10I6 atoms/ cm-3 . The role of nitrogen in silicon is quite different. Unlike other group 5 elements, such as P, or As, nitrogen does not behave as a donor impurity. An electronic center deep in the band gap has been reported by Tokumaru et al. (1982), but in general nitrogen does not appear to be electrically active in melt doped silicon. Another distinguishing feature is its low solid solubility: 3 x I O I 5 atoms/cm3 at the melting point of silicon (Yatsurugi et al., 1973). This is much lower than for other light elements, such as carbon, N = 3.5 x 10’’ cmP3, or oxygen, 1.7 x 1018 atoms/cm3. In float zoned silicon the

1.4 Single Crystal Silicon

equilibrium solid solubility is often exceeded, the excess concentration being proportional to the zone velocity, where typically the values met may be up to 5 x 1015atoms/ cm3 (Yatsurugi et al., 1973). The low electrical activity of nitrogen in silicon is useful because it has a major attribute, in that nitrogen doping at low concentrations, limited by its solid solubility, effectively inhibits dislocation generation and propagation, as first reported by Abe et al. (1981). Second-phase hardening is a well known metallurgical phenomenon, but usually occurs at higher concentrations. Low levels of nitrogen in silicon, in the 1015 atoms/cm3 range, impart resistance to the thermally induced warp of wafers met during device fabrication. Wafers sliced from Czochralski grown silicon contain oxygen on the order of 10l8 at./cm3. The interstitial oxygen has the function of strengthening the silicon crystal lattice, by raising the yield limit for onset of slip dislocations. This function is weakened if a significant fraction of interstitial oxygen is turned into oxide precipitates via precipitation process. Normal float zoned silicon slices, with an

140

Slices all 3 8 0 v m thick Load 509 Span 6 3 m m

oxygen content less then 1 ~ 1 0atomdcm', '~ and also low in carbon, distort readily under thermal stress, but with nitrogen doping outperform high oxygen Czochralski material. A simple demonstration to compare the normal FZ and CZ material is as follows. Standard, polished, (100) orientation single crystal slices, 76 mm diameter, 380 pm thick mounted on a three support point silica jig span 63 mm, and loaded by a 50 g weight are heated at 1150°C for 1 h, ramping the temperature up and down from 850°C in 30 min measuring the change in warp, and, by Secco etching, the amount of crystallographic slip caused by the controlled thermal stress. The results in Figure 1-9 clearly demonstrates that nitrogen doping strengthens FZ wafers. The NFZ is not currently used in commercial products.

1.4.4 Periodic Crystal Growth Temperature oscillations during crystal growth have been recognized for a long time, and their effects described (Carruthers, 1967; Hurle, 1967; Chedzey and Hurle, 1966). At first sight this may appear an odd

(1001 orientation

120

---

5100

Chanqe in TIR (warp) LH a i i s Extent of slip RH axis

.-C

470 50 :. 440 %

g, 60 c I I I I

6 40 20

I L

Float zone N-doped

Float zone standard

Czochralski 0-doped

Figure 1-9. A comparison of warp and slip after loading slices (1 h at 1150°C) (LH: left hand, RH: right hand). [Note that curvature in a silicon slice is hardly ever a simple saucer shape; it is more like a potato chip (potato crisp). Modern metrology equipment scans the whole surface to arrive at a single value, the total indicator reading (TIR), and also provides plots of the surfaces.]

1 Silicon Processing

concept, but the underlying principle is simple and can easily be demonstrated (Hurle et al., 1974). A small channel containing gallium (a metal which, conveniently, is molten at temperatures above 30 "C) with a number of thermocouples inserted equispaced along its length is well wrapped in thermal insulation to prevent heat loss. One end of the channel is clamped to a flowing water cooler, and so held at around 3540°C. The other end is attached to a heater, whose temperature is gradually increased. At first, simple heat flow along the channel creates a thermal gradient, recorded by the thermocouples. However, as this temperature gradient is increased, a point is reached when the thermocouple signals suddenly change into regular sinusoidal oscillation. The system behaves analogously to an electrical AC driven oscillator, whose frequency is determined by the inductancecapacitance product. Here the thermal diffusivity, kinematic viscosity, and channel dimensions, replace their electrical counterparts in an equivalent thermal-mechanical resonator. Thermal oscillations have been seen widely in many crystal growth systems, not only in semiconductors - Si, Ge, GaAs, InSb, etc. -but also in LiNbO,, garnets, and most oxides and fluorides (co*ckayne and Gates. 1967). Superposition of oscillations on the temperature near the solid-liquid interface between a crystal and its melt causes large regular fluctuations in the growth conditions. The driving force, which determines the overall rate of growth, is provided by supercooling - setting the melt temperature close to the interface a little below the melting point. Since most crystal growth rates are relatively slow. this value is normally smaller than the magnitude of the thermal oscillations, and so the growth becomes highly dynamic, and even, at the peak of each cycle, includes momen-

tary meltback. This periodic nature of crystal growth controls the incorporation of dopants and impurities into the crystal, whose concentrations may vary markedly, the changes exactly replicating the periodicity. The regularity of these growth striations can be seen by etching, and by spreading resistance (microresistivity) measurements, made on a cut vertical section of a crystal, as shown i n Fig. 1-10. Since the crystal growth interface across a diameter is always curved, cut slices intersect several striae, and subsequent delineation reveals a spiral radial impurity distribution pattern in the slice, as shown in the X-ray topograph of the carbon distribution in a float-zoned slice

Figure 1-10. Periodic crystal growth ( I ). Spreading resistance plot (above). with points taken at 10 p m intervals along the growth axis. Etched surface micrograph (below). showing the structure variations within a single striation.

1.4 Single Crystal Silicon

Figure 1-11. Periodic crystal growth (2). X-ray topograph of the carbon distribution across a cut slice. C, = 4 x 1 0 ' atoms/cm3. ~

in Fig. 1-1 1. (Note: the X-ray topography technique is covered in Sec. 1.6.1). If growth periodicity did not include a meltback within the cycle its effect on impurity distribution would be far less severe. This has been demonstrated by the float zone growth of small diameter rods, when the latent heat of solidification generated at the interface can escape more easily than at larger diameters, permitting higher growth rates. As the rate is increased, a point is reached when the supercooling gradient overcomes the thermal oscillations, and at a growth rate above 3 m d m i n the striae disappear. This research, while interesting, is not a production option. In the case of Czochralski growth, as will be discussed later, the melt is normally positioned in the heat field to keep thermal convection low, the axial pitch of striations is closely linked to the growth parameters. The etched vertical section shown in Fig. 1-10 was taken from an 80 mm diameter, (100) orientation, crystal pulled at 1.5 mm/ rnin, with a rotation rate of 15 rpm hence the

thickness of the silicon layer grown per revolution was 100 ym, which, as the measurements show, is also the striation pitch. On the other hand if the crystal is grown under high thermal convection, then the striae are closely spaced, discontinuous, and aperiodic (Carruthers et al., 1977). Spreading resistance measurements taken on the slices cut from such crystals reveal an extremely wide scatter of values. The effects of normal striated silicon in device manufacture are quite variable. In some cases it does not seem to matter, but in other cases striae can cause serious losses. Again because of the greater difficulties in zoner operation, float zone silicon tends to have more problems. For example, in the manufacture of UHF transistors, for applications at around 500 MHz, the cut-off frequency, ft, is a function of the collector-base current, Zcb, which is very susceptible to small, local, microresistivity variations. In a direct comparative trial, the percentage standard deviations about the mean offt,f,, at the operating Zc, current, has been measured using three materials sources (see Table 1-3). In the third material an epitaxial layer of the same type, and resistivity as the underlaying substrate, deposited from the vapor phase, and so free of the melt-growth striae, provides an extended bulk material within which the transistors are fabricated. As the table shows neither CZ nor FZ can match extended bulk epitaxy, EBE, while the FZ Table 1-3. The effect of resistivity striations on device performance. cr: standard deviation, ft: mean value of the cut-off frequency. Type of material

oft) in %

Float zone Czochralski Epitaxially extended bulk

24 10 3

1 Silicon Processing

material is the worst in this application. EBE material is used i n large scale production of these devices, its additional cost for outweighed by the yield improvement. Epitaxy therefore is one way to overcome the bulk striation problem. Another is the neutron transmutation doping method already described, and whose importance in the high voltage and power fields will now be more fully appreciated. Again the costs are obviously somewhat higher than for the conventionally doped materials, but the fabrication and device performance are far superior. Herzer (1977, 1980) and Herrmann and Herzer (1975) have examined the interaction of striations in NTD doping. Using material with a starting resistivity of 10 times the final value shows no background striations, at 5 times slight striations are seen, while an initial resistivity 2 times final, gave + l o % variations. A third, and the most widely used way to overcome striation effects, which introduces no added costs, is that employed in MOS integrated circuit fabrication. Taking n-MOS as the example, the substrate is p-type, boron doped at around 20-30 R cm resistivity. The MOS devices are made entirely by ion implantation, with n+ source and drain channels, and an n- gate implant equivalent to a resistivity of somewhere around 1-5 R cm. These implant concentrations are at least 10 times higher than the substrate boron level, and striation effects are reduced to insignificance; that is, similar to the NTD situation. Today integrated circuit manufacture consumes more than 90% of the world's semiconductor silicon as Czochralski crystal, our next topic.

1.5 Czochralski Silicon The increasing size of crystals pulled by the Czochralski ( 1917) technique, and

the technological developments associated with the growth of dislocation-free material, in which there is close control over not only the dopants, but all impurities, represents one of the outstanding achievements in semiconductor processing. The silicon pullers used initially were quite simple (Teal and Buehler, 1952). The charge, consisting of small lumps of broken polysilicon, was melted together with a small precise amount of dopant, from a silicon alloy made with P, As, or Sb (n-type), or B (ptype), at just above the melting point, 1412"C, in a pure silica crucible, retained in a graphite holder to prevent it sagging, held under an argon atmosphere; either resistance or RF induction heating was used. A thin, single crystal, seed rod mounted in a rotating shaft or a stainless steel cable was lowered into contact with the melt surface, and a little melted off in order to establish a clean solid-liquid interface. Then, as the temperature was lowered, silicon started to solidify on the seed, which was withdrawn at a controlled rate to pull a crystal of the desired resistivity, ultimately almost emptying the crucible. This apparently simple description is deceptive, there were many hidden subtleties needing to be understood. It was soon realized that, to be able to pull a crystal at all, without spurious growth at the crucible wall, it was essential to have a centrosymmetric heat field - the introduction of crucible rotation followed, which also minimized random convection in the melt. As charge sizes increased, RF heating was abandoned, and the tapering of graphite resistance heaters was used to shape the best vertical heat field profile. However, having established this i n the melt - crystal interface region, it could only be maintained as melt was used by introducing a crucible lift mechanism. The furnace configuration which resulted, as shown in

1 . 5 C z o c h r a l s k i Silicon

Crystal rotation and lift Solid conduction Surface radiation Gas convection Thermal baffles Si0 evaporation Interface generation of latent heat

Crucible holder

Oxygen dissolution

Crucible

Heater

Vacuum pump I

Heater

-t- Crucibleurotation and lift

(a)

(b)

Figure 1-12. The Czochralski silicon crystal puller. (a) Principal components of the hot zone. (b) Heat flow (t) and oxygen transport (0) during crystal growth.

Fig. 1-12a, is that still in use in even the largest pullers. 1.5.1 Dislocation-Free Silicon

The first dislocation-free material (Dash, 1958, 1959, 1960), was made by slowly growing small finely tapered crystals, but Zeigler (1961) used a rapid pull rate after seeding, to establish a thin neck, in which the few dislocations present grew out to the side surfaces, onto which a large dislocation-free crystal could then be grown. This was possible since, once a crystal is free of dislocations, it is better able to withstand the thermal stresses met during crystal growth. Prior to the introduction of dislocation-free growth, the germanium and early silicon crystals contained 105-106 cm-2 dislocations. As a result of the thermal gradients in the system, these formed up into

arrays, and lineage, deteriorating towards the bottom of the crystal; twinning was a serious problem leading to yield losses (Wilkes, 1959). The ability to grow dislocation-free crystals depends critically on control of the shape of the solid-liquid interface in the meniscus region. Why any crystal takes the shape it does is closely linked to this problem, and is examined first. The external shape of a crystal is related to two basic parameters, each a generic term covering several associated attributes: (a) Temperature, T, which includes all aspects of heat flow - conduction, convection, etc. - and generation - from the main heater, or from latent heat at the interface. (b) Crystal habit, CH, which includes all aspects of morphology - nucleation, crystal growth along basal planes, dislocation formation, twinning, etc.

1 Silicon Processing

The totally facetted alum crystal from a near isothermal solution growth is crystal habit dominated, while the near shapeless mass from a crude unbaffled melt system with high temperature gradients is temperature dominated. Normal Czochralski growth from a well designed system produces crystals whose macroscopic features show the balance that exists between the “temperature”. and “crystal habit”, contributions. In such a machine a very slowly rotated, (1 1 1) orientation silicon crystal can be pulled, at low or high growth rates, and will not exhibit any marked ’‘flats” along its sides, There are high-temperature gradients across the melt surface in the vicinity of the growing crystal. On the other hand, under fast rotation conditions, while the interface shape becomes fluid-flow dominated, the crystal grows out of a near isothermal surface, and such crystals, irrespective of growth rate, always exhibit extremely pronounced “flats”. Under normal growth using moderate rotation rates a crystal may exhibit narrow side facets near to its top which increase in width towards the bottom, when the near empty crucible behaves as a “black box”, near isothermal, cavity. For this reason the crucible and remaining charge is lifted faster than needed to keep the melt surface stationary, but lifting it out of this too isothermal region. so avoiding excessive facetting. The T e CHbalance applies everywhere, including at the solid-liquid growth interface, on which we now focus. While the main heater, and baffles, determines the overall thermal profile of the puller, it is actually quite ineffective i n influencing the interface shape of the growing crystal, whose thermal conduction provides a good heat sink during growth. However, the latent heat of solidification (12.1 kcal mol-’ or 50 J mol-’), released at the interface, is a significant heat source. As

the pull rate increases the interface curvature changes from convex (into the melt), to concave (back into the crystal). Silicon crytallizes in the diamond-cubic lattice, with the { 1 1 1 } planes being the most densely packed, while the bonding between adjacent { 1 1 1 ] planes is relatively weak compared to other directions. Growth is fast along the { 1 1 1 ] planes, so leading to the appearance of ( 11 I ] facets on crystals, but slow perpendicular, while cleavage twinning, and dislocation generation and propagation all occur along this dominant basal plane (Ellis and Treuting, 1951; Townley, 1973). Since in the T CH interactive model, facets are only expected in near isothermal regions, their position and size can be predicted, as the interface shape changes from convex to concave during the growth of a (1 1 1) orientation silicon crystal, shown in Fig. 1 - 13, and matched by a series of actual interfaces of crystals snatched from the melt grown at increasing pull rates: from convex, to inversion, to ring facet, finally concave (Wilkes and Perkins, 1971-72). Dislocations form on the very small peripheral { 1 1 1 } facets at the edge of convex interfaces, and once formed continue downwards into the crystal as it grows further. This cannot happen where the (1 1 1) crystal is bounded by a ring facet, or, in the case of a (100) crystal, when the interface is concave. These are the conditions for the zero dislocation growth of silicon, and are established immediately after seed-on in a narrow neck, before proceeding on to enlarging the diameter to full size. As stated earlier, when a crystal is grown in the dislocation-free mode from its start, it is better able to resist the temperature gradient hoop stresses met later as the solid crystal cools, when i t is withdrawn from the hot zone in the puller. To avoid thermal shock at the end of the pulling process, when the crystal is with-

1 . 5 Czochralski Silicon

I /

Increasing growth rate

Overall isotherm I

JYq

Predicted crystal interface

(5) Facetted

Convex

Inversion

Peripheral ring facet

Concave

Figure 1-13. The changes in interface shape of a (1 11) orientation silicon crystal as the growh rate is increased. As the growth rate increases latent heat of solidification at the interface plays the most significant role in determining its shape (LHT, latent heat temperature profile; MHT, main heater temperature profile; hatching indicates the solid crystal). ( I , A) Low speed, small central facet, convex. ( 2 , B) Somewhat faster pull, larger central facet, still convex. (3, C) Even faster pull, latent heat generation now compensates for heat losses across the whole interface, which becomes a { 1 11 ) mirror surface: the point of inversion. (4, D) Speed of growth greater than for inversion, producing a wide ring facet and a small relatively shallow central concavity. (4, E) Speed faster still. The central cavity is deeper and wider so there is a narrower ring. (5, F) The pull rate is now very fast and any MHT/LHT compensation is outside the pheriphery of the crystal. Very deep concavity, no ring facet.

drawn from the residual melt, which can lead to stress-generated dislocations running- back up into the solid, so causing yield losses, the final part of the crystal is grown taDered in a cone to a point. Mastery of the zero dislocation growth mode, for both CZ and FZ techniques, at the end of the 1960% preceded the later machine development which led to the crystals weighing 200 kg or more with diameter of up to 300/400 mm in the current development. Many thousand

tons of dislocation-free silicon have been produced annually.

1.5.2 Constitutional Supercooling For epitaxial substrates, large amounts of very highly doped, n+ and p+, zero dislocation crystal are needed, which involves the particular problem of constitutional supercooling, as described for metals by Rutter and Chalmers (1953). At the crystal-melt,

1 Silicon P r o c e s s i n g

solid-liquid interface of a growing crystal impurity segregation occurs, its coefficient, different for each dopant, defined by concentration in solid = C, concentration in bulk liquid C,

kett = -

-2)

For a rejected impurity keff is less than 1 .O, but as a result of the rejection, a boundary layer builds up in the liquid at the interface, at a higher concentration than in the bulk, from which the crystal grows. Therefore the effective krff for a finite growth rate is higher than the equilibrium value, k,, and rises with increasing growth rate. The thickness of the boundary layer, 6, within which fluid motion is laminar, relatively slow, and hence nonrnixing, so that diffusion is the predominant transport mechanism, is determined by the crystal rotation stirring, and as the rotation rate increases the boundary layer gets thinner. This relationship is given by the Burton, Prim, and Schlichter (Burton et al., 1953) equation

where vg is the growth velocity, and D the impurity diffusion coefficient in the liquid, of the order of 5 ~ 1 0 cm - ~ s. This formula shows that keff varies continuously from k,, at very low growth rates, to 1 .O, at very high rates. The higher impurity level in the boundary layer results i n a silicon-dopant composition of lower freezing point, as seen in Fig. I - 14. The temperature gradient from the solid into the melt, necessary to allow growth at the chosen rate, is also shown in Fig. 1-14. At the higher rates needed to obtain the desired interface shape for dislocation free growth, and when the dopant leveis are also high, a region is formed in the liquid, ahead of the crystal, which is supercooled by virtue of its local constitution,

Temperature gradient into melt L

3 +

he Wdopant

W m

Position of maximum supercooling due t o local composition

I-

Distance into melt

Figure 1-14. Constitutional supercooling during crystal growth. k,= C,/C,, k c , , = C,/C,, 6 = 1.6 D”3 Y”’ w-iil , TcG: crystal growth temperature. As vg and 6 -+ 0, kef, + k , ; and as vg and 6 become large, k r f f 7, 1.0.

and in which nucleation and random crystallization can happen. As the advancing interface approaches this point, the single crystal rapidly becomes polycrystalline. The greatest risk of this occurring is in the later stages of n+, or p+ crystal growth, when segregation by normal freezing, as defined by Eq. ( 1 - l), further increases the already high initial dopant concentration. Studies of the onset of constitutional supercooling in these crystals (Wilkes and Perkins, 197 1-72), using striation etching to reveal the details, has shown that the initital perturbations, and formation of cellular structure, in (1 1 1) orientation silicon, originate on the inner edge of the ring facet, as shown in Fig. 1-15. Achieving high production yield and reproducibility for this material demands precise control of the pulling parameters.

1.5 Czochralski Silicon

Figure 1-15. The onset of constitutional supercooling at the inner edge of the ring facet during the growth of dislocation free, (1 1 I ) orientation, n+ Sb doped, silicon. Note: In the enlargements the arrow '? points outwards radially. At a later stage of growth, the whole interface breaks up into a hexagonal cellular structure, prior to the transition from single crystal to polycrystal.

1.5.3 The Incorporation of Carbon and Oxygen Most of the components in the hot zone of a puller are made of some form of carbon - graphite heaters and crucible holder, and carbon felts in the baffle assembly - but careful housekeeping can virtually eliminate these as a source of contamination. Maintaining the pullers leak-tight, using ultrapure argon as the purge gas, and employing rigorous purging schedules after loading the charge, remove air or moisture, which could otherwise react with the carbon parts to form CO, to dissolve into molten silicon; and as we have seen, polysilicon itself is very low in carbon - yet carbon can be a problem.

During the first step of meltdown of the polysilicon into the pure silica-glass crucible the system is at its hottest, up to around 15O0-155O0C, to achieve meltdown in a short time. Under these conditions reaction between the graphite crucible holder and the outer surface of the silica crucible releases carbon monoxide [see Equation (l)]. This is the prime source of the carbon impurity. After the meltdown is complete and the temperature is lowered, to around 1420-1430°C for the start of pulling, the reaction only continues at a much lower rate (Barraclough and Wilkes, 1986). In an atmospheric pressure puller, where the argon purge rate is commonly around 60 L/min, the initial carbon content in the crystal is around 2 ~ 1 0atoms/cm3; ' ~ but, if the

1 Silicon Processing

start is deliberately delayed, this steadily rises as more carbon is slowly dissolved. Operating the puller at a reduced pressure, of about 20 torr ( ~ 2 6 0 0Pa), with an argon input of 10 L/min at normal temperature and pressure, the effective gas displacement rate sweeping out the chamber is increased six-fold. and the silicon crystal produced contains far less carbon - by at least an order of magnitude. Under carefully regulated conditions, a large proportion of the crystal can be grown with carbon below its infrared absorption detection limit of 5 x lOI5 atoms/ cm'. In this case when meltdown is complete, and during crystal growth, further carbon transfer is insignificant. Today all large silicon Czochralski production pullers are operated at reduced pressure. While risk of carbon incorporation is essentially limited to the meltdown period, another reaction continues throughout the whole process - that between the silicon and the inner surface of the crucible, dissolving oxygen into the melt: Si + SiOz -+2 S i 0

(20)

which, at the same time, allows any other electrically active impurities present in the silica into the melt. Crucible quality depends on the quality of natural sources of silica. The superior crucible quality can be obtained by the use of fused synthetic SiO, made from semiconductor grade materials. CZ silicon growing using ultrapure polysilicon and synthetic quartz crucibles can result in resistivity greater than 200 Ohm-cm. Today, the use of commercial grade quartz crucible and polysilicon can produce C Z silicon with resistivity up to 50 Ohm-cm, nor p-type. Returning to the oxygen dissolution, as can be seen in Fig. 1-12b, this occurs primarily along the hotter inner wall of the crucible. and to a lesser degree across its base; and. while thermal convection transports

the S i 0 up to the free melt surface where it can evaporate, a small fraction of dissolved oxygen becomes incorporated into the growing crystal. This is a highly dynamic equilibrium, altering continuously as silicon is withdrawn from the crucible, and the ratio of melt volume to crucible surface contact area changes. In a normal C Z crystal, the oxygen concentration is highest at the seed end, and gradually decreased along its length. To a first approximation, the oxygen concentration incorporated is proportional to the total crucible area contacted by the melt. In the Czochralski system, melt fluid dynamics clearly play a vital role in the growth, and in the incoporation of all impurities, into the crystal; the prime contributors being the thermal convection and the mechanical drive provided by the crystal and crucible rotations - usually in opposite sense. The convective drive is influenced by several factors. In fluid flow adjacent to a hot vertical wall, the velocity is a function of the temperature gradient, height up the wall, 12, and Prandtl number, Pr (Schlichting, 1968):

v a f (AT) . fi - Pr-'

(1-4)

where the dimensionless Prandtl number, the ratio of the kinematic viscosity to the thermal diffusivity, is a measure of the relative ease of movement and heat transport i n a fluid element. The value of P r (Si, liq.) is 0.015, a lower value than that of mercury, 0.023. [In comparison Pr ( H 2 0 , room temperature) is 7, and Pr of glycerol is 300.1 Because liquid silicon has such a low Pr value, as heat flows through the wall into silicon it readily convects. (A stability analysis for convection links this low Pr to the rotationally coupled thermal oscillations, described in Sec. 1.4.4 above.) Therefore thermal convection is less in a relatively wide flat melt, as is normal in CZ

1.5 Czochralski Silicon

silicon, and decreases as the liquid diminishes. (Note: in the CZ growth of oxides, with Pr around 30, taller narrower crucibles are common.) Positioning the crucible lower in the heat field, with a greater power transfer into the upper part of the melt, also promotes a reduction in the convective drive. Again, the baffle configuration surrounding the heater - crucible assembly reduces the temperature gradients in the system, and can be arranged to keep the crucible wall cooler, so reducing its dissolution rate (Moody, 1986). For a given CZ growing system, i.e., fixed starting melt geometry and hot zone thermal distribution, etc., the parameters that can significantly alter the oxygen incorporation are crucible and crystal rotations and growth rate variations. The effect of crystal/crucible rotation on the fluid flow patterns were studied in the past by simulation using fluid of similar viscosity as that of silicon melt at room temperature (Carruthers and Nassau, 1968). In the real crystal growth, however, the flow patterns can be significantly altered by the presence of thermal convection. The results of the simulations provide very useful information on the effect of rotational parameters. Kakimot0 et al. observed thermal and forced convection flows of silicon melt directly during Czochralski growth using X-ray radiography with solid tracers, for various crystal and crucible rotation speeds. The effect of non-axial symmetrical temperature distributions on the thermal convection flows was clearly observed. The suppression of thermal convection by crystal rotation-induced forced convection was also evidenced. One way to gain information on the flow properties of a growing system is to analyze grown crystals following parametric growing experiments. One finds that forced convection is effective in controlled oxygen incorporation.

Crucible rotation develops radial pressure gradients which enhance the thermal convection flow arising from non-vertical temperature gradient. Therefore, fast crucible rotation helps the transport of oxygen from near the crucible wall to the growing crystal and enhances incorporation. Fig. 116 shows the effect of crucible rotation on the incorporation level. Fast melt flow also results in a thinner melt-crucible boundary diffusion layer, a condition that will enhance crucible dissolution. Crystal rotation rate determines the magnitude of the upward melt flow. This flow can serve as oxygen transport from crucible bottom to the growing interface. The net effect on the overall flow pattern and oxygen incorporation depends on its magnitude and rotational direction relative to the crucible rotation. Fig. 1-17 (Lin & Benson) shows several axial oxygen concentration profiles of silicon grown with several combinations of crystal/crucible rotation rates, under both

CRYSTAL ROTATION 28 RPM

0.2

0.4 0.6 FRACTION SOLIDIFIED

0.8

Figure 1-16. Oxygen profiles at various crucible rotation rates, with crystal rotation rate held at 28 rpm (From Moody, 1986).

1 Silicon Processing

0.1

0.3

0.4 0.5

0.6

0.8

FRACTION SOLIDIFIED

Figure 1-17. Axial oxygen profiles of silicon crystal grown with several combinations of crystal and Crucible rotation rates (From Lin & Benson, 1987).

counter- and iso-rotation conditions i n the same grower and a reduced pressure. These results show that the forced convection induced by crystalkrucible rotations has very significant effects on the melt flow pattern, even in the presence of thermal convection. The bulk of the incorporation behavior is

-z P P

consistent with, and can be interpreted from, the simulated flow patterns (Carruthers and Nassau, 1968). From previous discussions, it is seen that forced convection is an effective tool for controlling oxygen incorporation. In order to achieve a desired oxygen level with axial uniformity in a silicon crystal, the following procedure may be carried out. Experimentally, for a given crystal growing system, one can establish oxygen incorporation profiles as a function of crystal/crucible rotation rates via studies such as shown in Figures 1-16 & 1-17. Using selected rotational parameters at different stages of crystal growth, one can develop and tailor the growth processes to grow crystals of desired oxygen concentration with substantial axial and radial uniformity. Figure 1-18 (Lin & Benson) shows an example of using variable crucible rotation rates to change the oxygen incorporation levels during the growth, while the crystal rotation rate is maintained constant. It shows that the crucible ramping to a higher rotation rate effectively raises the oxygen

‘I 19

I-

z W 0

0 0

l5I

W W

TiLIL-l

0.1

0.2

0.3

0.4

0.5

0.6

FRACTION SOLIDIFIED

0.7

0.8

0.9V

Figure. 1-18. Axial oxygen profile of a silicon crystal showing the effect ofcrucible rotation rate on oxygen incorporation level (From Lin & Benson, 1987)

1.5 Czochralski Silicon

level and changes the oxygen concentration profile. The incorporation level can be further enhanced when alternate ramping-up and -down of crucible rotation at medium and high rates are employed, as shown in the Figure 1- 18. This process works well for the production of medium to high oxygen content material but good yields at lower oxygen concentration are difficult to achieve. This problem is now addressed in the next section.

1.5.4 Magnetic Czochralski Silicon Electromagnetic stirring and other effects in molten metals have been recognized for many years, and, in the intense radiofrequency fields within the heater coil of a float zoner, magnetic levitation in part supports the molten silicon. Some large Czochralski pullers have used a three-legged graphite picket heater, driven from a threephase AC mains supply at 50-60 Hz, the heavy heater current inducing rotational forces in the melt, where flow rates as high as 20 rpm have been observed. The latest puller designs have returned to using twolegged picket heaters and DC drive to avoid this effect. Today it is the application of static magnetic fields to dampen out the convection flows in Czochralski systems that is important. The early work by Chedzey and Hurle (1966) was initially directed towards the suppression of growth-striae in FZ, and then in CZ crystals (Hurle, 1967). Czochralski growth in a transverse magnetic field was reported by Witt et al. (1970), but it is the work, initiated by Hoshi et al. (1980), who applied very large electromagnets to commercial silicon pullers, that stimulated worldwide interest, and major developments. The results of Hoshi et al. show that products with a wide range of oxygen con-

tent can be made by Czochralski growth in a strong magnetic field; the technique offers the control of resistivity up to 5000 Q cm, and also higher than normal growth rates. Both electromagnets and superconducting cryomagnets have been used to provide fields in the general range of 1000-5000 G (0.1-0.5 T). Hoshi et al. (1980) and Suzuki et al. (1981) first used a transverse magnetic field, with the lines of force parallel to the melt surface; axial fields have also been applied (Hoshikawa, 1982; Hoshikawa et al., 1984; Cartwright et al., 1985). As the strength of the magnetic field is increased, fluid motion perpendicular to the lines of force is progressively dampened out until, in a high field, it is suppressed altogether. Thus in an axial, vertical, field the radial fluid flow across the surface is reduced; whereas in a transverse, horizontal, field it is the axial (upwards at the crucible wall, and downwards beneath the crystal) and azimuthal motions (rotational shear around the crucible wall) which are reduced but then not the radial flow. Clearly, in either mode there is a strong effect on thermal convection. Hoshi and Suzuki showed that a horizontal field of 0.15 T was sufficient to suppress the convection in a melt contained in a 25 cm diameter crucible. Again, the balance between field strength and the crucible and crystal rotations, both in their rates and relative senses, is apparent in the effects on impurity distribution. In a vertical field a wide range of oxygen concentrations is possible, but, because the radial flow is reduced, it is difficult to achieve acceptable radial uniformity, compared with the results possible in the absence of a field, whereas very good radial impurity distribution is possible using a transverse horizontal field. The two magnetic field modes are distinguished principally by the large differences in their temperature distributions, and gra-

1 Silicon Processing

dients, which to a considerable degree determine the alternative product properties. Using the vertical-field conditions the increased radial temperature gradients are larger than if no field were present, whereas in the same puller under horizontal field conditions the temperature gradients are reduced, and can be much smaller than with no field. As we have previously seen, the oxygen dissolution rate is set by the wall temperature, and experience now suggests that horizontal-mode growth is more suitable for the production of controlled lowoxygen silicon. While both modes sharply reduce the growth striae, produced by thermal fluctuations i n the melt close to the interface, which are a feature common to all zero field growth, again it is the low-temperature gradient beneath the crystal, available under transverse fields of around 0.25-0.3 T which permits growth rates some 50% higher than with no field, yet maintaining the correct interface shape required for dislocation-free growth. A more flexible use of magnetic field which minimizes the undesirable characteristics of the vertical magnetic field is the use of “cusp” magnetic field. A CZ system with cusp magnetic field (Hirata & Hoshikawa, 1989) uses two sets of coils (often superconducting) co-axially with the crystal, which are energized in opposing directions. In this arrangement, the symmetry plane between the two coils can be placed at the melt-crystal interface throughout the growth process. The resulting cusp field effect is such that there is orthogonal component on the crucible wall which damps the erosion effect (to dissolve oxygen) by the melt flow, while there is no orthogonal magnetic component exerted on the melt surface (free-surface evaporation is not retarded). The net effect is a decreased oxygen level. On the other hand, when the melt surface is located away from the symmetry plane of

the cusp magnetic field, the melt surface will be subjected to the effect of orthogonal magnetic components, resulting in reduced oxygen evaporation and increased oxygen level (Series, 1989). In summary, Czochralski silicon technology is indeed very complex. A large number of highly interactive, adjustable parameters are available in the thermal design of the core furnace, its heater and baffles, and in the aspect ratio of the melt; in the mechanical movements to position, lift and rotate the crucible and crystal; and now in the magnetic conditions, in mode choice, and field strength and position. It is, however, precisely this flexibility in design variables and growth control, not available to the same degree in float zoning, that gives the Czochralski technique its power to address the product requirements. 1.5.5 Evolution in Czochralski Crystal Diameter As semiconductor technology continues

to advance, the IC design rule is approaching 0.1 pm by 2006, if not earlier. In parallel with the design rule decrease, the increased circuit design complexity results in increased chip size. This has been the major driving force for increased wafer diameter for the last twenty five years, that is, to increase the required number of IC’s per wafer i n order to reduce IC manufacturing cost. In 1960, wafer diameter used was 1” when the IC was in its infancy. Today, 200 mm is the main stream, which was initiated in the late 1980s. In 1995, the development of 300 mm wafer was initiated, targeting for IC manufacture in 0.18 pm design rule generation. Concurrently, Japan has launched a project for development of the 400/450 mm wafer era technology. In the up-scaling of the wafer diameter, in the 300 mm-450 mm diameter range, the most significant techni-

1 . 5 Czochralski Silicon

cal challenges are in the crystal growth. The growing process is far more complex than in the past. Unlike small diameter crystals, the dislocation-free as-grown yield will dominate the cost of the manufacturing of 300/450 mm diameter wafers. To economically produce large diameter silicon crystals, one needs to employ large charge size for growing a long crystal. A charge greater than 200 kg for 300 mm diameter crystal growth or 400 kg for a 400/450 mm crystal is necessary At this melt size, thermal convection is severe. The temperature fluctuations associated with the thermal convection will make initial thin neck growth more difficult. The thermal convection would also result in higher oxygen incorporation in the crystal. It is common to apply an external magnetic field, such as a cusp magnetic field, to the large melt to reduce the thermal convection effect and to reduce the melt-crucible interaction. When growing a CZ crystal weighing 150 kg or more employing a thin neck growth to achieve the initial dislocationfree seed, one must consider the risk of fracturing of the thin neck due to the crystal weight exceeding the fracture strength of silicon. An estimate based strictly on fracture strength in tensile mode (Kim & Smetana, 1990) predicts that the crystal weight limit is about 200 kg when the smallest neck is - 4 mm in diameter (a targeted neck diameter commonly used for necking). However, for 400-450 mm diameter growth, the crystal weight needs to be in the range of 400-500 kg to be comparable with the 200 mm crystals in production economics. At this weight level and to avoid neck fracture, the “Dash Neck” diameter needs to be larger than 6 mm, a diameter that is difficult to achieve dislocation free structure in the necking process. One of the solutions is to devise a “crystal suspending system” to help support the crystal weight through a

“subsidiary cone” grown following the dislocation-free neck is established (Yamagishi et al.). Another crystal weight related problem is the “creep” phenomenon at the high stress concentration region at the “plastic temperature”, >9OO0C. The intersection of the crystal neck and “crown” is such a region (Chiou et al., 1997). When the stress from the crystal weight (plus the meniscus column and surface tension in the melt) exceeds the critical resolved shear stress for slip, slip dislocations will be generated and propagate down the crystal, along the slip systems, ( l l O ) / ( l l l ) . Two possible consequences may result. If the slip exits the crystal, the dislocation-free growing process will not be interrupted, but the crystal length above this point will not be useful. If the dislocation reaches the growing solid-liquid interface, the continued growth will not be dislocation-free. The latter case occurs when the crystal length, L, is less than L = R . Tan 54.74’, where R is the radius of the growing crystal. Besides weight related problems, the large diameter silicon requires growth rate reduction as well. As the crystal diameter is increased, dissipation of the massive latent heat of solidification from the freezing interface becomes more difficult, since the heat transfer paths are longer. This can be understood from the heat balance shown in Figure 1-12. In silicon crystal growth, a sufficiently high growth rate is essential to maintain a steady crystal growth i n order to maintain the dislocation-free structure. One can enhance the growth rate by enhancing the heat transfer rate via increased crystal surface cooling. Radiation shields have been used to reduce the radiation effect from the melt and from the heater (von Ammon et al., 1995). However, by doing so, the thermal gradient is increased resulting in more curved isotherms and interface shapes, enhancing the condition for higher

1 Silicon Processing

thermal stress. The stress induced slip can occur causing structure loss. In the severe case, the high thermal stress can cause crystal cracking. Eventually, the growth rate issue may be a limiting factor in determining the maximum diameter for CZ silicon. The increase in diameter has a profound effect on the crystal’s cooling rate and, therefore, the microdefect formation. The formation and density of grow-in microdefects, the so called D-defects (family of defects by vacancy clusters) and A-defects (interstitial clusters) are functions of growth rate and post-solidification annealing temperatures. (Umeno et al., 1997. Voronkov et al., 1997) Analyses show that an increase in diameter increases the dwell time of crystal in 900- 1 100 “C range (von Ammon, 1996). Slow cooling reduces D-defect density. Therefore, the diameter increase causes the reduction in D defect density. The D-defects on wafer surface cause oxide thinning and its density is directly correlated with the defect density i n the GO1 (Gate Oxide Integrity) test. Therefore. it appears that the diameter increase certainly has a positive effect on the microdefect density. It appears that large diameter crystals grown today and i n the foreseeable future will contain either vacancy or self-interstitial type microdefects, or both. A crystal growth process for growing defect-free materials is not yet available. In the CMOS processing employing thin gate oxides, <5 nm, and shallow junctions, clusters of vacancy-type or interstitial-type defects are undesirable. Therefore, IC makers may resort to epitaxial wafers or hydrogen annealed wafers (Kubota et al.. 1994). The epitaxial silicon layer has higher quality than the melt grown bulk silicon. The layer is essential free of interstitial oxygen, carbon and microdefects, and lower in surface particle and metal contamination than the bulk wafer. The DRAM manufacturing

group has been the largest user of the polished wafers. The microdefect problem associated with the bulk wafer may drive a significant fraction of the DRAM manufacturers to switch to epitaxial wafers. Two possible epi structures exist: p/p+ and p-lp-. The former has also been popular with the microprocessor and ASIC manufacturers, the advantages including improved gate oxide quality, internal gettering, latch-up imis useful to munity, etc. The p - / ~ approach “mask” the microdefect problems in the polished p- wafers. The microdefects, neither dislocation loops or voids are not found to extend into the epitaxial layer during the epitaxial growth (Shimizu et al., 1997).

1.6 Wafer Preparation Silicon semiconductor devices are mostly fabricated on polished wafers or epitaxial wafers. Thus, the first step in device fabrication is the preparation of mirror polished, clean and damage-free silicon surfaces i n accordance with the specifications. As the design rule of device fabrication advances into the deep sub-micron region, the device processing and performance are more sensitive to starting material’s characteristics. The requirements of the geometrical tolerance of the polished wafers as well as their bulk characteristics are becoming more stringent. The polished wafers are prepared through the complex sequence of shaping, polishing and cleaning steps after a single crystal ingot is grown. Although the detailed shaping processes vary depending on the manufacturer. The processes described below are generic in nature. Newly introduced processing technologies will be discussed where appropriate. Figure 1-19 is a flow chart showing a generic wafer shaping process.

1.6 Wafer Preparation

Figure 1-19. Flow chart describing generic steps involved in wafer prepara-

Wafer Shaping Process

tion employing modern technologies.

Ingot Surface Grinding, Orientation Flattening or Notching

4 Wafer Sllclng by ID or MultipleWire Saw

1 Edge I Notch Rounding

1. Lapping or Grinding (Both Sides) Edge Polishing Donor Anneal

Doubleside or Singleside Polish

Backseal Poly Si, LTO, etc.

(option)

(Final Polish)

The single crystal ingot is first evaluated for crystal perfection and resistivity before it is surface ground to a cylindrical shape of a precise diameter. Flat(s) or a notch with preferred crystallographic orientations are ground on the ingot surface parallel to the crystal axis. The primary flat or notch, for example, is positioned perpendicular to a (1 10) direction on a (100) wafer, is used for alignment of the wafer in the device processing with automated handling equipment. The primary flat, or notch, also serves as an orientation reference for chip layout, since devices fabricated on wafers are crystallographically oriented. The existence of secondary flat on the wafer, shorter than the

primary, is used to identify the wafer surface orientation and conductivity type (SEMI International Standards).

1.6.1 Slicing The slicing operation produces silicon slices from the ground ingot. Slicing defines the critical mechanical aspects of a wafer, such as thickness, taper, warp, etc. The slicing is commonly carried out by an inner diameter (ID) circular saw, Figure 119a, after the ingot is rigidly mounted to maintain an accurate crystallographic orientation as previously determined by X-ray diffraction. The ID saw uses a thin stainless

1 Silicon Processing

steel blade bonded with diamond particles on the inner edge of the blade. Recently, the development of multiple-wire saws has enabled the silicon slicing to result in high throughput and superior mechanical properties such as significantly reduced bow and wrap. Figure 1- 19 b shows a schematic of a multiple-wire saw. In this arrangement, parallel, equally spaced and properly tensioned stainless steel wires spun across two pulleys are part of a single stainless steel wire winding through a complex set of pulleys. Cutting of multiple slices results when the ingot is pressed against the traveling wires under injection of slurry. Although the cutting rate is much slower than the ordinary ID saw (ordinary ID saw is 80-100 times higher rate), as many as 300 slices can be produced simultaneously. Besides higher throughput, the multiple-wire saw has other major advantages over the ID saw. Slicing by the multi-wire is actually the result of low speed grinding/lapping action by the slurry. Improved bow, warp, TTV, and taper are much easily obtained than with the ID saw. In addition. the slow lapping action by the moving wire results in small kerf loss which affords more slices per inch of ingot. It is shown that the kerf size loss is very close to the diameter of the wire used. The multiple-wire saw offers material savings (reduces kerf loss by 30% compared to the ID saw), increased productivity and improved wafer mechanical properties. It has

Silicon Ingot

crystal Ingot

been used for slicing 200 mm and 300 mm diameter wafers and is expected to be used for the future “diameter generations”.

1.6.2 Edge Rounding The square edge of sliced silicon wafers is rounded by an edge grinder. The roundededge wafers greatly reduce mechanical defects, such as edge chips and cracks induced by wafer handling. Edge chips and cracks can serve as stress raisers which facilitate the onset of wafer breakage or plastic deformation and slip dislocations during thermal processing. In addition, the rounded edge eliminates occurrence of epitaxial crown (thicker epitaxial layer at the wafer edge) in the epitaxial deposition process and pile-up of the photoresist at the wafer edge. The shape of the rounded edge usually follows an industrial standard (i.e. SEMI standard) in which the edge profile fits within the boundary of a standard template. However, variations from the “standard” exist. In some applications, the rounded edge is modified to be more “blunt” i n order to facilitate the chemical mechanical polishing (CMP) operation for inter-level dielectric planerization. In this case, the “blunt” edge supposedly prevents the wafer from slipping out of the template during polishing. Other applications require more “rounded” edge shapes for increased strength. Often, a compromise on the edge profile is required.

ire

ID Saw

Multiple Wire Saw

Figure 1-20. Schematics showing the traditional ID saw and recently developed multiple-wire saw for silicon wafer slicing.

1.6 Wafer Preparation

1.6.3 LappinglGrinding The lapping of the silicon slice surface takes place when the slice is ground between two counter rotating cast iron plates in the presence of an abrasive slurry, usually a mixture of submicron-sized alumina or silicon carbide particles suspended in a solution. The purpose of lapping operation is to remove the non-uniform damage left by slicing, and to attain a high degree of parallelism and flatness, both global and local. In fact, post-lapping slices possess the best mechanical characteristics in the entire shaping process flow. The subsequent mirror-polishing operation generally degrades the flatness characteristics attained by the lapping operation. However, lapping with slurry also introduces fresh damage to the silicon surface which requires subsequent chemical etching and chemical-mechanical polishing for removal. Chemical etching and CMP of the silicon surface degrades the wafer flatness. To circumvent this situation, surface grinder (with a precision grinder bonded with diamond particles) on both sides of the wafer is employed to achieve surface flatness with reduced surface damage. With reduced surface damage, the need for chemical etching and CMP is also reduced and good mechanical properties may be retained.

1.6.4 Chemical Etching Chemical etching of the slices is done to remove mechanical damage induced during the previous shaping steps - ingot surface grinding and slicing . The etching can be carried out by either an acidic solution or a caustic etchant. The acidic system is mostly based on HN0,-HF system (or with modifiers such as acetic acid (Robbins & Schwartz, 1960). The surface material removal is the result of two-step reactions.

The Si surface is first oxidized by H N 0 3 to form S O 2 , followed by its removal by HF. The acid etch produces a smooth and shiny surface. However, since the reaction is exothermic, temperature control is critical in order to maintain uniform etching. Caustic etching uses a alkaline solution (Moreland, 1985), such as KOH, with certain stabilizers. The KOH etch offers a uniform etching rate, but produces a rougher surface than the acid etch, since KOH etching rate is crystallographic orientation dependent. Chemical etching of the slice may be repeated after subsequent mechanical operations such as edge rounding and lapping/surface grinding to remove mechanical damage.

1.6.5 Polishing Polishing is accomplished by a chemicalmechanical polishing process involving a polishing pad and a slurry. The polishing slurry is usually an alkaline colloidal solution containing sub-micron-sized silica particles. While CMP is used to remove surface damage and to produce a mirror-finished surface, it also degrades the wafer flatness achieved by lapping/grounding. Therefore, it is essential to optimize operational parameters so as to minimize the polishing time and flatness degradation. Double-side polishing (CMP on both front and back surfaces simultaneously) has been found to result in superior flatness than the single side polishing arrangements. The combination of surface grinding (on both sides of the wafer) and double-side CMP has shown to result in superior total indicator reading (TIR), total thickness variation (TTV) and local flatness. Such an approach is becoming a standard manufacturing process for large diameter wafers (2300 mm) preparation. The wafer preparation via mechanical methods (i.e., grinding, CMP etc.) has its

1 Silicon Processing

limits in the degree of flatness that it can achieve. To supplement and to fine tune the local topography for further improvement in local flatness, tools such as plasma assisted chemical etching (PACE) (Bollinger & Zarowin, 1988) have been developed. Such a tool employs a spatially confined plasma with a scanning mechanism to allow material removal to be controlled as desired over the wafer surface. The PACE utilizes low energy neutral ions (i.e. <1 eV) rather than energetic ions which are involved i n reactive ion etching. Therefore, PACE produces minimum or no subsurface damage. 1.6.6 Cleaning Wafer surface contamination can affect electronic device performance. The contaminants can be attached to the wafer surface physically or chemically. Cleaning of the wafers is necessary at many steps in device fabrication processes as well as during the wafer shaping processes. The silicon wafer must be free of contamination before it is shipped to the device fabrication line. The cleaning process for removal of surface contaminants during wafer shaping and polishing processes is discussed below. In general, the contaminants can be classified as molecular, ionic or atomic. Typical molecular contaminants include waxes, resins and oil used in polishing and sawing operations, and material from the plastic containers used for slice transport and storage. Molecular contaminants are absorbed on the wafer surface by weak electrostatic forces. They should be removed before subsequent cleaning involving chemical reactions. The ionic contaminants, such as Na+ C1-, F-, are present after wafer treatments in HF - containing or caustic solutions. They are attached to the wafer surface by chemical absorption. The atomic contaminants of

concern are transition metal atoms such as Fe, Ni, and Cu. The transition metals and ionic species can cause degradation in device performance. Chemical cleaning is an effective method to remove contaminants on wafer surface. Many chemical cleaning processes have been developed. The process that is widely used in the semiconductor industry is the so-called “RCA Clean” (Kern and Puotinen, 1970) which consists of two consecutive cleaning solutions including H20-H202-HN40H (Standard clean 1, S C l ) and H20-H,0,-HC1 (Standard clean 2, SC2). The SC1 clean, with volume ratios typically 5 : 1 : 1, is to remove organic contaminants by both the solvating action of NH,OH and strong oxidizing action of H20,. The NH40H can also form soluble complexes with some metals such as gold, copper, nickel and cobalt. The SC2 clean, with typical volume ratios of 6: 1 : 1, removes transition and alkali metals from wafer surface and prevents re-deposition from the solution by forming soluble metal complexes (with C1-). The SC 1 can also remove particles physically attached to wafer surface by etching effect of NH40H which detaches the particles from the wafer surface. The repulsion effect of the opposite charges transferred from the electrolyte NH; and OH- to the wafer surface and detached particle, respectively, prevent the particles from redepositing on the wafer surface. A modified RCA Clean (Kern, 1984), by adding a brief etch in diluted HF solution after S C l was designed to eliminate the thin oxide layer grown on silicon surface due to the SC1 process. The thin oxide resulted from the SCI was thought to hinder surface for cleaning by the SC2. Many modifications of the “RCA clean” exist (published and unpublished). Most of the modifications are on the volume ratios. For example, in order to reduce silicon surface roughness, there is

1.6 Wafer Preparation

a trend to greatly reduce the volume fraction of the NH,OH in SC1 from the original formula. The effect of surface roughness of silicon surface on the gate oxide integrity has been reported as significant when the oxide thickness is thinner than 5 nm, although the literature is often not consistent, probably due to different process conditions. Other chemical cleaning solutions/ processes, such as piranah (H,SO,H202-H20), ozonated water, etc. have also been shown to be effective. However, the “RCA clean” and its modified versions have been the most popular cleaning processes used by the semiconductor silicon manufacturers.

carrier surface recombination is very high in damaged material, but falls rapidly as the damage is removed by etching, providing another route to depth assessment (Buck and McKim, 1956). The decoration of dislocations and damage centers by copper, followed by infrared transmission microscopy, permitted the direct visualization of defects in silicon (Thomas, 1963), but the effects of decoration at 900 “C and quenching were questionable. An unambiguous measurement technique uses the X-ray double crystal diffractometer to study strain and defects in crystals. First introduced by Bond and Andrus (1952), applied to silicon, it has become a major tool in the study of machining. The X-ray system is shown in Fig. 1-21 a, where the double crystal configuration results in monochromatic radiation reaching the sample crystal. The signal to the detector, I (e), changes as the sample is turned through a small angle about the Bragg reflection, producing the rocking curve of Fig. 1-21 b. Provided that the reference crystal quality is good enough (Tanner, 1977), the angular width of the rocking curve is a measure of the defects and strain

1.6.7 Mechanical Damage in Silicon The subsurface damage in silicon which results from the processes of diamond grinding, sawing, or lapping, can be assessed by various means. An early method was based on the fact that damaged silicon is etched faster than undamaged material, so that plotting etch rate versus depth gave some indication of the extent of damage associated with a particular process. Minority

X-ray source 4 - t e s t -

(a)

‘

Rocking curve width

Test sample angle ( 8 )

Detector or film plate (b)

Figure 1-21. The measurement of strain and defects in crystals. (a) The double crystal goniometer. (b) The rocking curve measurement.

1 Silicon Processing

present i n the test crystal. The width of the rocking curve at half peak height - the half width - can be calculated from first principles using structure factors, and the angular beam spreads (Deslattes and Paretzkin, 1968; Batterman and Hildebrandt, 1968), where useful intrinsic half-width values, W,, for silicon are: (a) { 1 15) reflection from { 1 1 1 ) silicon: W , = 6.3", (b) ( 4 2 2 ) reflection from { 100) silicon: W , = 15.4". Observed half-widths greater than these intrinsic values measure the strain in the lattice, which may be quantified using the expression

where A W = (W,- W,), that is, the difference between the measured and intrinsic half widths. In addition to the rocking curve, this Xray method leads to topography. If the sample is rotated into a position where the signal is at a half-height value, and then the detector is replaced by a photographic plate, contrast across the image originates from the variations in signal intensity caused by localized strains around defects in the surface of the sample. Carbon is a smaller atom

than silicon and its substitution in the crystal leads to local strain, which, developed in the whole slice topograph (Fig. 1-11), shows its radial distribution. In both rocking curve and topography applications, the X-ray penetration depth is limited to no more than about 30 pm, and therefore the method is usually coupled with etch removal of known depths, to build up a total picture of the damage. Applied to slicing, Fig. 1-22 shows the X-ray topograph of a step-etched sawn slice, and the associated step site density versus depth plot. In this case most of the sawing damage is confined within about 20 pm depth beneath the surface. This is confirmed by the rocking curve plot shown in Fig. 1-23. Some low level of point damage sites persists beyond 20 pm, not readily seen in the topograph, but detected by the signal integration inherent in this measurement. When both sides of a slice are examined it is usually found that the damage levels are different, and that the slice is bowed. It is important to distinguish between transient and permanent bow. The surface damage in a silicon slice can be pictured as an abrasion by surface cracking along the weaker bonded [ 1 1 1 ) planes, with the stress caused by the wedging open of microcracks by abraded debris. The annealing of an abrasion scratch at 1100°C for

Figure 1-22. X-ray topography of a sawn and step-etched slice. Reflection: { 220}, Mo KaI radiation.

1.6 Wafer Preparation

Depth o f etch per side iprnl

Figure 1-23. The dept of damage beneath a sawn surface measured by the etch/X-ray rocking curve technique (AW = W , - W c ) ,

30 min, examined by interference contrast microscopy in Fig. 1-24a, reveals the { 1 1 1 ) slip lines, while the topograph in Fig. 1-24b shows the stress relief by plastic flow, creating an array of long dislocation loops on slip planes on either side of the scratch. Thus, in the presence of differential damage between two surfaces a slice bows - hollow on the least damaged side. If the bow, B , measured as the maximum depth of the hollowed side of the slice, diameter d, is taken to have a uniform radius of curvature, Y = d2/(8B), then the relation between bow and strain (Tamura and Sunami, 1972), is given by &=--

16 t,i B 3 d2

At temperatures below around 500 "C elastic deformation leads to brittle fracture as &>5x103, at a stress in the silicon > lo9 N m-2. At higher temperatures, the elastic bending gives way to plastic deformation as the stress is applied, shown in the plot of Fig. 1-25.

Figure 1-24. Surface damage in silicon. Annealing of an abraison scratch in a { 11 1 ] orientation polished slice (1 100°C for 30 min]. (a) Interference contrast microscopy revealing slip relief along [ 11 1 ] planes. (b) X-ray topograph showing the stress relief by plastic flow, creating a network of long dislocation loops on [ 1 1 1 ) slip planes on either side of the original scratch.

Since both silicon and germanium are hard brittle elements of the diamond cubic lattice structure, from the outset of the semiconductor industry diamond sawing has remained the prime route to slicing ingot material. Initially the sawblades were steel discs, slotted around the periphery, into which diamond grit particles were pressed. Such saw discs when rotated at high speed around 1500-2000rpm, with water as a coolant, cut both germanium and silicon

1 Silicon Processing

Figure 1-25. Deformation and fracture of silicon resulting from mechanical stress. Note: For silicon Y/(l - P ) = 1.8 x IO" ( N m->), and so, approximately, the stresdstrain ratio is 2 x 10" ( Y : Young's modulus, P : Poisson's ratio). Hence for example at a stress of 10' N m-? the corresponding strain is 5 x

1500 r

W L

500 I-

Elastic deformation

0 ' 10'

lo8

1O'O

Yield stress (Nrn-')

well. However, to cut thin slices accurately such blades have to be thicker than the wanted slices, and this is obviously very wasteful of the crystal material. As a result, these peripheral blades were rapidly superseded by internal diameter blades. Thin high tensile rolled steel sheet is punched out into large discs with a central hole around which a band of diamond of closely controlled particle size is electroplated. This blade is clamped into a mounting frame which is stretched over an outer ring in high tension, sufficient to enlarge the central diamond saw hole towards its elastic limit, so providing a thin but extremely rigid blade, capable of very precise slicing with minimum kerf loss of material. Very considerable effort has gone into the development of the internal diameter sawing machines and blades to meet the continuing scaling up of slice diameters. When an internal diameter diamond blade, stretched in tension over an outer ring and rotating at high speed, is driven forward into silicon to saw a slice, the tension is slightly relaxed and the blade vibrates (wobbles) slightly. The ingot on one side of the kerf slot is rigid, whereas the partially cut slice on the other side of the sawblade can relax a little. As the blade edge vibrates. the diamond on its sides impacts

against the ingot and slice, causing differential damage, where, on the next cut, the newly exposed ingot surface becomes the other side of the next slice. Such slices may be cut perfectly uniform in thickness but bowed, until they are etched to remove the damage before polishing, when they relax to a very low bow value. On the other hand, if a blade is mounted and run incorrectly, so that it deflects during slicing, no amount of subsequent etching can correct the ensuing permanent bow. The forces which are generated at the blade edge during sawing can be followed by mounting the ingot on a dynamometer attached to an x - y - z - t chart recorder. The forces F,, F,, and F,, measured simultaneously as the blade traverses the full diameter of the ingot, are related to the operating conditions. Typical results, looking at variable cutting rates, are shown in Fig. 1-26. Here F , is the direct loading force between the advancing ingot and blade, F , is the tangential, dragging, force along the blade periphery, and F , is the smaller, but very important, vibrational force perpendicular to the blade. At a low feed rate the saw is only in gentle contact with the silicon and free to vibrate; then, as the feed rate is increased towards its optimum, the blade is held more firmly and vibration decreases . .. and on the

1.6 Wafer Preparation

- 160 -

- 120 -9 ’c

{

0.4 -

-80

.-VI

0.2 -

:40

-I

i A

Saw feed r a t e Icm rnin-’1

(a1

-3

-2

-1 0 1 2 3 Saw blade deflection (pml

(b)

Figure 1-26. Damage during silicon slicing. In (a) the force measurements and bow were recorded using distilled water as the cutting fluid ( 0 Fx, x F y , + F,, 0 bow). The effect of replacing this by a 1 % solution of polyethylene glycol (6000 mol wt.) is seen in a force F, ( A ) of 0.04 N, and a bow ( 0 ) of under 10 Fm, Subsequently in (b) it is necessary to etch the sawn slices to reveal the true distortion associated with blade deflection. + marks the zero bow, zero saw blade deflection intersection of the two axes.

slices sawn so does the bow. Finally, as the feed rate is set too high, the pressure between the ingot and the blade begins to relax the blade tension, F , starts to rise again and the bow becomes severe. Taken further, beyond its stress limit, the blade ruptures. The role of the cutting fluid, “lubricant”, can also be studied. As an example: at such high rotation rates, around 2000 rpm, centripetal forces rapidly remove the cutting fluid from the blade edge, and the liquid film whose thickness should provide a cushion against F , is very thin. The long chain molecule polyethylene glycol both improves the streamline flow of high speed liquids and increases their viscosity, so maintaining a thicker film. Applied to silicon slicing under otherwise optimum feed conditions, the F , is halved, and the bow reduced even more. It is recognized that the slicing quality has key influence on the yield on the subse-

quent polished wafer manufacturing steps, and has major impact on the overall production cost. For ULSI fabrication, the mechanical specifications for wafers are stringent and tolerances are tight on parameters such as local flatness, TTV, thickness distribution. To improve these parameters for large diameter wafers (>200 mm) the ID saw is being replaced with multiple-wire saws as previously discussed in the section on sawing. During later device processing the slice meets several high-temperature stages in which, if residual peripheral damage is still present, the heating and cooling gradients will lead to slip, and yield losses. This is shown in Fig. 1-27. Here the transistor printout marking of rejects on-slice at Test1, matches the slip, revealed by etching the back of a slice, which had been inadequately etched after grinding. Lapping is a very different issue. While it is used after slicing to provide slices of

1 Silicon Processing

Figure 1-27. Device failures from slice fabrication. The Test-I printout on-slice of UHF transistor rejects in (a) is linked directly to the process induced crystallographic defects revealed by selectively etching the reverse back face. seen in ( b ) .Note the high incidence of failures initiated from the periphery. particularly near to the reference flat. contributed to by insufficient ingot etching after grinding.

the close thickness uniformity necessary to proceed on to etching and polishing, to remove any saw marks, and to improve the planarity and parallelism, fundamentelly i t is a retrograde process. The abrasive pressure is directed into the silicon surface. Under very low load, i n hand lapping, the depth of damage generated is proportional to, but somewhat greater than the abrasive particle size (Buck and McKim, 1956). When the pressure is increased, as is necessary to achieve useful stock removal rates from commercial lapping machines, both the depth of damage. and the site density. rise steeply - under normal operating conditions to at least 3-4 times particle size. For example using a 20 pm, close particle size distribution, water classified alumina. WCA, at a load of 30 g/cm’, the damage extends to a depth of around 90 pm - worse than in the original sawn slice. Where lapping is part of the slice machining, deep etching is needed subsequently to remove the subsurface structural damage i t has caused. The issue of residual mechanical damage and flatness requirements in the large slices,

of diameter 200 mm and above, required for the latest ULSI microprocessor and memory chip applications has focused attention on the lapping process and possible alternatives. The new standards of flatness in the final polished wafers are measured in hundredth of a micrometer (pm). This is needed because, in the fabrication of ULSI circuits, the lithography uses submicrometer dimensions with minimum feature sizes currently around 0.2W0.18 p m but decreasing and expected to be down to 0.1 pm by the year 2006. Associated with these dimensions, the thickness of gate oxides is now below 50 A, and with close tolerances of f a few angstroms, and is decreasing. Thus the underlying substrate surface has to be polished to display required surface micro roughness in additional to the local flatness. The requirements of the wafer characteristics for ULSI processing for the current and future design rule generations is mapped out in the National Technology Roadmap of Semiconductors (SIA, 1997). Overall, mechanical damage and its elimination play an important role in determining the wafer manufacturing process and final mechanical properties of the polished wafers.

1.7 Oxygen in Czochralski Silicon 1.7.1 The Behavior of Oxygen in Silicon The oxygen incorporation behavior in a CZ growth system is the result of dynamic balance between crucible dissolution, melt surface evaporation, thermal convection and forced convection induced by crucible and crystal rotations. Since “oxygen i n silicon melt” is a dynamic system, the oxygen concentration profile along a grown CZ

1.7 Oxygen in Czochralski Silicon

crystal depends on the growing process. Although one can obtain an “effective” segregation coefficient from such an oxygen profile assuming normal freezing behavior, however, the coefficient so obtained has no relationship with the “equilibrium segregation coefficient”, k,. The k, is a physical constant related to the binary phase equilibrium of silicon and oxygen. In general, a segregation coefficient less than unity implies an eutectic phase diagram. The melting temperature of silicon containing oxygen is lower than pure silicon. On the other hand, if k,> 1, the solidus would terminate with a peritectic reaction. The k , = 1 would indicate a situation where liquidus and solidus merge, a condition not consistent with the phase rule. The k, for oxygen in silicon has been widely studied for the last 25 years. The reported values range from greater to less than unity, including unity. Ekhalt and Carlberg (1989), in their study of oxygen solubility, proposed a phase diagram in which the slope of the liquidus near Si is consistent with k , c l . Jackson (1988) calculated the solidus, liquidus, the eutectic point and temperature of the S i - 0 phase diagram at the Si end, using k, = 0.3. The resulting phase diagram is consistent with the properties observed in the silicon containing oxygen. The microscopic oxygen incorporation behavior is, however, intimately related to the equilibrium segregation coefficient, k,, of oxygen, as described by the Burton, Prim and Schlichter (BPS) equation (Eqs. 1-3). Investigations based on crystal growth experiments and the analyses via BPS relation have shown that oxygen does segregate during solidification and assume a non-unity k , value between 0.2-0.3 (Lin, 1996). While carbon enters the lattice as a substitutional impurity occupying a silicon site, oxygen does not, but instead enters as a bound interstitial impurity, bonding be-

tween two adjacent silicon atoms, in a structure which permits more complex vibrational modes (Newman, 1973). The broad 9 p m infrared absorption band, seen at room temperature, arises from a number of vibrational modes of similar energies. The concentration of bound-interstitial oxygen in silicon is measured by the 9 p m absorption (ASTM Standard F-121), and if any oxygen is precipitated within the crystal, by heating in the range 105O-60O0C, the absorption decreases. Reheating at a high temperature, > 1300 “C, disperses the precipitates and restores the absorption. However, if the temperature is held at around 450 “C, any unprecipitated interstitial oxygen present forms “thermal donors”, which cause major resistivity changes in the crystal. This thermal behavior pattern was first established by Kaiser et al. (1956) and then expanded (Kaiser, 1957; Kaiser et al., 1958). Long Czochralski crystals, which are grown over a period of many hours, slowly withdrawing into a cooler chamber, experience a different thermal history between the seed and tail ends, depicted in Fig. 1.28. The thermal history of the grown CZ silicon has profound effects on the precipitation kinetics of interstitial oxygen during the subsequent heat treatments. The oxygen precipitate gettering has been related to the reduction of leakage current yield losses of DRAM and other devices (for example, Steinbeck, 1980a, b; Lin and Moerschel, 1986). Other studies have shown device failures associated with crystal defects, either present at the start of the fabrication process or formed during it, and also linked to the oxygen status. From defect etching studies, many observers noted that where a high density of surface defect features (e.g., oxidation induced stacking faults, seen after the first furnace step) was found on one side

1 Silicon P r o c e s s i n g

Heat losses: Conduction along crystal and convective transfer from surface to gas

Carbon via

"o"~

Precipitate growth

900°C1

10000[

Oxide precipitation on nuclei - C, or condensing interstitial:

/ /

High temperature radiation

fault defects high Si interstitial concentration

1&20°C

Melt stirring and convection

ion into m e l t at w a l l

Figure 1-28. The variable thermal history of an as-grown Czochralski silicon crystal

of a slice, the opposite face had a very low density. In one direction, this was soon linked to residual damage remaining after slice polishing. Similar work demonstrated the relation between oxidation-induced stacking faults, the slice heat treatment temperature, and oxygen precipitation (Matsush*ta, 1982). Much device engineering research was explored the generation and suppression of oxidation-induced stacking faults during fabrication (Stimmel, 1986), but to use bulk silicon it is necessary to understand the basic precipitation mechanism.

1.7.2 The Precipitation of Oxygen in Silicon In normal CZ growth processes, the interstitial oxygen incorporated during solidification is on the order of 1 0 ' 8 / ~ m 3This . oxygen concentration is above its solid solubility limits at the subsequent thermal processing temperatures, Le., the oxygen is supersaturated. The kinetics of the precipitation varies depends on the thermal history, the oxygen concentration and degree of oxygen supersaturation and heat treatment temperatures. Research into bulk crystallization from liquids, to produce, for example, fertilizers and salts, has contributed much to nucleation concepts, and in particular the particle

1.7 Oxygen in Czochralski Silicon

of critical radius rc. In a supersaturated liquid, or solid, at the outset tiny atomic clusters form and redisperse in a highly dynamic situation, but some merge and grow, until, reaching a certain critical radius, they become stable, and from then on will not redissolve. In such a process there is an initial incubation period during which sufficient nuclei reach r,, then faster precipitation, which dies away as the equilibrium solubility is approached. Many systems exhibit this behavior, including the solid state precipitation of oxygen in silicon, where at 750°C, the process has still not reached equilibrium after over 1000 h - solid state reactions are very slow. In this approach it should be expected that the nuclei formed by other impurities present will affect the initial nucleation induction step. Thus in the silicon case, the distribution of oxide precipitates across a slice after heat treatment closely maps the grown in carbon distribution shown in Fig. 1-1 1 (Wilkes, 1983), and also influences the actual precipitation kinetics (Kishino et al., 1979; Craven, 1981; Shimura et al., 1985; Barraclough and Wilkes, 1986). After nucleation, the main precipitation process reduces the bound interstitial oxygen concentration, developing different numbers and sizes of particles according to the temperature employed. A simple model can be used to predict the qualitative behavior correctly, and provides a basis for understanding the theoretical approach. Suppose two similar, adjacent, samples of the same impurity content, and with the same high background nucleation site density, are annealed for a long time, but at different temperatures in the supersaturation range. (1) In the sample heated at the high temperature the supersaturation driving force for precipitation is low, whereas the

diffusion rate of oxygen through the silicon is high. Once a few particles exceed the critical radius, rapid precipitation reduces the oxygen concentration, leading to the formation of a low density of large particles, making use of only a few of the available nucleation sites. (2) Conversely, in the sample heated at a low temperature, by the same reasoning, the supersaturation is high, but now the diffusion is low. The second phase must precipitate, but, since the oxygen only moves slowly and through a short range, a high density of small particles is predicted, making use of many of the available sites. (3) Since the native oxide film on the surface of the silicon sample is effectively a particle of infinite radius, present at time zero, and needing no incubation period, the supersaturation-diffusion model provides a simple and obvious explanation for the existence, close to the surface, of denuded zones, free of any precipitation. From the start of the heating process, oxygen close to the surface can diffuse out into the native oxide layer, so reducing its concentration and inhibiting precipitate formation in this region. The depth of this denuded zone is expected to be of a similar magnitude to the distance between particles in the bulk - deeper when formed at a higher temperature, but very shallow from a low temperature anneal. Again this is as observed in practice. In a quantitative approach, the mathematics of diffusion-limited precipitation (Ham, 1958) have been applied to the case of oxygen in silicon. The starting concentration of bound interstitial oxygen, C,, is assumed to be uniform. After a short induction period

1 Silicon Processing

small precipitates are formed, whose density, N , remains constant throughout the remainder of the process. The particles are assumed to grow by diffusion with a spherical shape, and a common radius, ro(?),small compared to the interparticle distance, and taken to be a constant corresponding to the final value ro, at r -+ The particle are a form of silica containing oxygen at a concentration C,, while that in the matrix close to the particle is C,,, the equilibrium solid solubility at the temperature chosen. The Wigner- Seitz approximation replaces the cubic cells around each particle, accounting for the total volume, by equivalent spheres of radius R, defined by (4/3) II R3 N = 1. The oxygen concentration profile as a function of position, and time, C ( r , t ) can be represented by a Fourier series:

In this result 5, has the dimensions of inverse length, and can take an infinite number of discrete positive values, which are the required solutions. Expanding this in a power series for small values of the argume nt gives (1-1 1)

CQ.

If a particle does not nucleate, ro = 0; there is no oxygen diffusion, and the supersaturation is maintained indefinitely. Normally, after an initial transient, the first term of the Fourier series in Eq. (1-7) dominates when

(1-13) (1-7)

satisfying the boundary conditions C = C,, at r = ro, and where z,, is the relaxation time constant. Fick's diffusion equation i n spherical coordinates may be written

while the requirement that there be no net oxygen flux across the outer sphere boundary is defined by =0,

(1-12)

ri=O

-D($)

and

( 1-9)

D#O

r=R

Differentiating Eq. ( 1-7) with respect to r and t and substituting into Eq. (1-8) leads to the core expression given by Ham: tan [A,?(r-r0)]= A,, r ,

r =R

(1-10)

The constant A, & has the dimensions of concentration and a value somewhat less than Co- C,, . The oxygen distribution so described is essentially uniform, with a value slightly less than C,, throughout the diffusion volume, except i n a small region of radius about 5 ro, around the particle, in what may be described as a random-walk - well model, as shown i n Fig. 1-29. Further manipulation of the equations leads to two important expressions: (1-14) and

If it is reasonably assumed that the oxide is close to SiO, in its composition, then a

1.7 Oxygen in Czochralski Silicon

(SANS) to validate the theoretical model (Livingston et al., 1984), as shown in Fig. 1-30.

10j

Temperature (“0 1100 1000 900 800 700 I

(

10l4

I ,/’ !/

,’

/ I

;

I,’\, \

’.

1013m-.

‘\\

‘,

‘.

10’2

-a6 c .-

) I

10’0

-.-al 109 ; Y

Figure 1-29. The random-walk - well model of dif-

108

fusion limited precipitation.

’” 7.0 Only within a region of about 5 x the particle radius does a diffusing oxygen atom become trapped to a particular site and the number of particles formed is strictly defined.

value can be assigned to C,. The values of C,, C,,, and the relaxation time constant, zo, are obtained from the infrared absorption measurements used to follow the precipitation process (Binns et al.; Newman et al., I983 a; Wilkes, 1983). Hence, values for the particle density, N , and its radius, Y, can be obtained at various annealing temperatures, based solely on kinetic data. This can then be compared with direct measurements obtained from integrational etch pit counts, and scattering. By near infrared transmission the optical scattering from the large particles formed by high temperature anneals can be used to calculate Nand Y. Similarly, the very small particles, with radii less than 100 A, can be measured by small angle neutron scattering

8.0

9.0

10.0

11.0

10’

ioL/ T [ K - l I Uxygen precipitation in silicon. 1he particle radii and their corresponding number densities, based on the four methods shown, all assume spherical geometry. However, in the random walkwell theory the particle shape does not significantly affect the overall data given. The symbols are: 0 radius derived from kinetics, radius from etch pit measurements, x radius from neutron scattering, + radius from optical scattering.

kigure

1-JU.

Figure 1-31. Direct lattice image of a platelike oxide precipitate in silicon. Finlike features extend above, and probably below, the main (100) habit plane. Sample annealed at 750°C for 431 h .

1 Silicon Processing

The analysis of SANS results also provides information about the shape of the particles, which has recently been allied to high resolution transmission electron microscopy, to reveal platelet precipitates, shown i n Fig. 1-31 (Bergholtz et al., 1989). The total assembly of particle radii from these various techniques, plotted against reciprocal temperature in Fig. 1-30, shows a remarkable coherence of results, i n spite of the different nature of the experimental methods and approximations involved, and the diffusion-limited precipitation theory underpins the qualitative model set out earlier.

1.7.3 Thermal Donors and Enhanced Diffusion The problems surrounding the understanding of thermal donors, their formation, and behavior, are aggravated by the lower temperatures involved, 350-5OO0C, in any kinetic study, and by the complexity of their structure, where work suggests that four interstitial oxygen atoms are involved i n a TD center (Newman and Claybourn, 1988). Following the oxygen precipitation kinetics at low temperatures requires a more sensitive method than infrared absorption; this is provided by the technique of the relaxation of stress induced dichroism (Corbett and Watkins, 1961), which has been applied to the silicon-oxygen system (Benton et al., 1983; Newman et al., 1983b). In this procedure, a small silicon rod sample, cut with a [ 1 1 11 axis, is heated at a temperature of 45O-50O0C, under a high pressure applied along the axis; subsequently the sample is cooled while still under stress. As a result of diffusion while stressed, the number of bound interstitial oxygen atoms, n , , linking matrix silicon sites in the [ 1 1 11 axial bonds becomes less than the number, n 2 , in each of the bonds in the [ T I T ] , [TTl].and [lTT].directions. Ifnow

linearly polarized 9 ym infrared light is used to measure the oxygen absorption coefficient, in directions parallel and perpendicular to the stressed [ 1 1 1 ] axis in the samples, the following relations apply:

from which

(aL-q )= const . ( n 2- n l )

(1-17)

When such a prepared test sample is then annealed at some chosen temperature but under no load, further diffusion allows the oxygen to return towards a random distribution, relaxing the induced stress dichroism, by a first order kinetic process, with a relaxation time constant z*.Using a normalized dimensionless parameter ( aL- aii)/a, the constant z* is given by the slope d [log (aL-al~)/a,]/dt, and is equal to z/8 where l / t i s the fundamental frequency of a single diffusion jump at the temperature concerned. The diffusion coefficient then follows from the simple relationship that D = ai/@ t),where a. = 5.42 A, the lattice constant of silicon. An early problem in the understanding of thermal donors arose from their speed of formation, requiring only a short heating time to reach an equilibrium resistivity. The role of lattice defects in this process is now recognized to be a major contributor. In their stress dichroism study, Benton et al. (1983) observed that, if the silicon was given a 9OO0C/2 h heat treatment followed by quick cooling to eliminate donors (but thereby freezing i n excess silicon sei€-interstitials) before going into the stress dichroism procedure as described above, the value of the diffusion coefficient, D, was enhanced by nearly two orders of magnitude. Another way to alter the intrinsic defect balance in silicon is by irradiation. Newman et al. (1983 b) used 2 MeV electrons onto a

1.8 Gettering Engineering

stressed silicon sample target held on a water-cooled block at well below 60°C. After irradiation the 9 pm signal was lowered, while the generation of oxygen-vacancy ( 0 - V ) A-centers was measured by their infrared absorption at 830 cm-’. On subsequent relaxation, the induced dichroism now decayed exponentially - with D several orders higher. Oxygen can also trap mobile silicon self-interstitials, to form an (0-1) center, with absorption at 935 cm-I. Tin is an efficient trap for vacancies in silicon; as-grown Sn-doped crystals have similar (0-1) center concentrations to undoped silicon, but substantially lower ( 0 - V ) A-center levels, and in this material the relaxation of stress dichroism is retarded by a factor of approximately 6. Involvement of both vacancies and interstitials in this diffusion was proposed by Gosele and Tan (1983). A simplistic view of a single jump could be that either oxygen traps a vacancy to form an Acenter, which then intersects a self-interstitial, or, alternatively, an (0-1) center is formed, which then traps a vacancy. The reality is more complex than this. Enhanced diffusion is seen after metallic contamination by copper or iron. Carbon enters into a number of low temperature centers with oxygen and silicon, and as nucleation sites for self-interstitials (Davies, 1989). Free electron effects have been used to provide an explanation for dopant concentration-dependent thermal donor kinetics (Wada, 1984; Wada and Inoue, 1986); while in the precipitation of oxygen in heavily doped, n’ and p’, silicon, Bains et al. (1990) have observed both enhanced (p’) and retarded (n’) precipitation, which they also link to the free electron model. Finally the thermal donor formation in p-type, 0.3 0 cm, material at 450°C is accompanied by the simultaneous loss of substitutional boron (Newman and Claybourn, 1988). Overall, while the diffusion-limited

precipitation model provides a sound basis for understanding the behavior of oxygen in dislocation-free silicon, which is applied in the “crystal engineering” discussed next, there is still much to be learned about the detailed mechanism of enhanced diffusion and thermal donors.

1.8 Gettering Engineering In the preceding sections of this chapter, reference has been made at various points to the ability of defects to act as gettering sites, sinks, for fast diffusing impurities. Also the serious deleterious effects of such defects, where they intersect device structures, has been emphasized. In addition the very slow nature of solid-state oxygen precipitation, seen above, has to be overcome if any use is to be made of such bulk precipitates. The controlled application of external surface mechanical damage (extrinsic gettering), and internal bulk oxide particles (intrinsic gettering) is now addressed. 1.8.1 Extrinsic Gettering in Silicon Mechanical damage in a silicon surface has to be quantified in both density and depth, where as seen in Figs. 1-22 and 1-23, only a few damage sites extend to any great depth. Since etch rates are a function of the intensity of damage, they fall rapidly during the initial stages of etching, so it is very difficult to leave a well-controlled residual damage level on the back side and achieve the required slice thickness tolerances by trying to limit the etching. This also leaves more to be polished off the front surface. What is required is to create intentionally a high density of relatively shallow lattice disorder, whose associated stress relaxes into stacking faults and dislocation loops early on the device thermal processing, to

1 Silicon Processing

provide a high gettering capacity. The lattice distortion around the dislocations sets up strained regions, the actual gettering sites, which, in accommodating the diffusing impurities, relax further into stable lower energy atomic configurations. There are several controlled backside damage options available from polished slice suppliers, aimed to match the individual device processes: MOS, bipolar, etc. The damage is reinserted starting from well-etched slices. One method, widely used, employs a high adjustable-pressure water jet system, commonly used at around 1000 psi (=70 bar), which contains fine ground silica of well-defined particle size (about 1 pm). The grades of damage generated by the impingement of this jet on slices traversed beneath are achieved by varying the pressure, number of jets, and the traverse speed. Afterwards the front surface is polished in the normal way. Typical site densities obtained by this treatment range between 5x 1 O3 cm-’ to 5x10’ cm-’. An example of a higher damage level slice, before and after treatment, is shown in Fig. 1-32, while the rocking

Figure 1-32. Extrinsic gettering by silica-high pressure water jet treatment. Note the well-etched surface to remove uncontrolled damage prior to treatment, and the uniformity of mechanical damage sites generated ( S E M photograph).

curve broadening from this process is low to moderate: AW = 10” to 30”. (Note other values: deep-etched slice 0” to 4/8”, sawn slice 80” to loo”, lapped slice AW> 120”.) Lighter damage is most suitable for MOS device processes when, during the first oxidation at around 1000-1 IOO’C, stacking fault gettering sites are formed on the treated back surface at a density of around lo5 cm-2, which has a negligible effect on the subsequent mechanical behavior, warp, etc. However, as device feature sizes continue to shrink, there is strong emphasis on reducing both the maximum temperatures, and the total thermal inventory, used in fabrication. At temperatures below 1000°C the stacking fault generation is more complex and influenced by the oxidation ambient (Claeys et al., 1981). Again, if the damage is too light, instead of forming getter sites on heating, a large proportion may be annealed out. This is seen when first stage polished surfaces, with some submicrometer damage, are compared by etching to reveal defects before and after an 1100°C thermal cycle, when most of the damage sites disappear, and too low a stacking fault density results. The gettering performance, extrinsic or intrinsic, is monitored by etching the front polished surface, in which the device structures are fabricated, to reveal point defect sites: S-pits - shallow saucer etch pits, or haze, which are known to be related to the presence of heavy metal impurities, to low carrier lifetimes, and to emitter-collector leakage, which are all detrimental to yields. Again where the device process involves a number of high temperature stages, the extrinsic gettering performance gradually falls, and a higher initial damage level is necessary to counter this. For bipolar applications the same rules stand, but now the process employs higher temperatures, up to 1200 “C, where shallow

1.8 Gettering Engineering

damage sites are more easily annealed out, and gettering performance falls more rapidly through the successive high-temperature stages. While damage depths around 1-1.5 pm may be adequate in an MOS process, bipolar conditions can demand 24 pm, and even then the efficiency may be lower. Alternative approaches for inserting the mechanical back-surface damage, also widely used, are brush damage, or abrasive polishing, of the deep-etched slice, an example of which is seen in Fig. 1-33. By choice of materials and operating conditions (soft or hard brush, abrasive size, pressure, etc.) well-controlled products result, suitable for both MOS and bipolar applications. Finally, in a further development of extrinsic gettering, it has been recognized that fine grain polycrystalline silicon is an excellent, high temperature resistant, gettering material. Using low pressure chemical vapor deposition (LPCVD) and a silane source, in a process closely similar to that employed during the fabrication of polysilicon interconnects, a thin, 1-2 pm, layer is deposited on the deep-etched slices, at a temperature of 6O0-65O0C, prior to the polishing stage, which becomes the extrinsic gettering backside of the slice. Known as enhanced gettering (EG) this additional step is obviously rather more expensive to manufacture than the other routes described for providing extrinsic gettering, but its performance, particularly in the multistage higher temperature applications, such as in bipolar circuits, is superior, maintaining very low S-pit densities, and high lifetimes, as shown in Fig. 1-34. Achieving the best results in this field involves very close liaison between the slice manufacturer and the consumer device engineer' in Order to match the incoming material to the specific fabrication process.

Figure 1-33. Extrinsic gettering by abrasive (brush) treatment: (a) and (b) show lower and higher damage, respectively. Note the well-etched underlying substrates.

10'

1 Silicon Processing

r 3 4 5 Number o f oxidation cycles

I 6

Figure 1-34. Enhanced gettering by deposited polysilicon. Compariton between EG and mechanical backside damage ( M B D ) treatments. Material: Medium oxygen content, p-type, (100) orientation. Test: bipolar oxidation cycle - 1 I O O T , steam, 2 h. S p i t s : x : lifetime: orientation: 0.

1.8.2 Intrinsic Gettering in Silicon The beneficial effects of oxygen precipitates in the bulk of a device structure, and also in the substrate of an epitaxial slice, were reported by Tan et al. (1977) and Yang et al. (1978). Now there are many papers on this topic, which, since it directly interfaces to device processing, has attracted much attention. The single stage heat treatments described in Sec. 1.7.2 are obviously far too slow to provide crystal-engineered slices tailored to meet device specifications. However, this is not the only constraint. Any useful process must make consistent intrinsically gettered slices using input silicon slices containing the varying amounts of oxygen typical of normal Czochralski growth. Earlier work concentrated on two-step processes, with a first high temperature heat treatment, followed by a second at a lower temperature, the so-called HI-LO, treatment. Typical times and temperatures used

are: 16 h at 1150°C and 64 h at 650°C (Yamamoto et al., 1980). While other variants of two-step treatments have been proposed, this HI-LO process shows the principles, using the models developed in Sec. 1.7.2 above. In the first step, the high temperature, 1 150"C, anneal is in a range where the supersaturation of bound interstitial oxygen is relatively low but diffusion high; any preexisting microprecipitates near the surface tend to dissolve. Oxygen readily diffuses to the surface oxide, so developing a concentration gradient near the surface, while deeper in the bulk, precipitates start to form. In addition to conventional analysis methods, for example, by a SIMS profile on a cut section through the slice, the concentration gradient from the out-diffusion can also be measured by reheating the sample at 450 "C, to generate thermal donors from the remaining interstitial oxygen, and then making a microresistivity scan on a beveled section, to calculate the gradient profile. The results from material with a bulk value [O,] around 8 x lOI7 cme3 show the surface concentration falling to around 5 x 1017 after 6 h, with a precipitate denuded zone 20 pm deep, while after 16 h the values are around 3-4 x I O l 7 with a denuded zone up to 50 p m deep. While the interstitial oxygen content is lowered at step 1, in the following low temperature step 2 at 650 "C the supersaturation is still high and precipitate growth continues at the sites formed at step 1 but there is little added fresh bulk nucleation. The desired intrinsic gettering structure, bulk precipitates and a surface denuded zone, is achieved - but there are problems. The amount of bound interstitial oxygen precipitated by this process, and whether or not a denuded zone is formed, are a direct function of the original oxygen content, as shown in Fig. 1-35. In addition, in this plot

1.8 Gettering Engineering

Lo, 0

7.0

Denuded zone

No denuded

8.0

, 9.0

, 10.0

Initial oxygen concentration [ O , I ( 1 0 ~ ~ 3 )

Figure 1-35. Two-stage oxygen precipitation in silicon. Thermal cycles: 1 150°C, 16 h; 6 5 0 ° C 64 h. Other two-stage processes exhibit similar behavior, with no denuded zone formation below an initial oxygen concentration of around 8x 10" atoms/cm3.

the wider scatter of results from material of lower initial oxygen content reflects the effects of other contributory factors. For example, in the influence of carbon on nucleation, where using material of normal high oxygen content but ultralow in carbon, < 3 x 1015 atoms/cm3, the precipitation is heavily retarded, and there is no denuded zone formation (Wilkes, 1983). The effects of not precipitating enough oxygen have been demonstrated by de Kock (1982), who found that, during an n+ phosphorus diffusion into an epitaxial layer, under the diffused region the denuded zone width shrank, in one case from 50 to 25 ym, in another from 25 y m to zero. His interpretation of the denuded zone shrinkage under the diffused islands is that the rapid formation of critical nuclei and secondary precipitation is due to the local injection of a large excess of silicon self-interstitials. This links to the diffusion jump mechanism and enhanced diffusion described in Sec. 1.7.3. Such secondary precipitation is quite general, and may build up throughout a multistage process, rather than at one particular

step. Again, during lower fabrication temperature CMOS device processing, using substrates of medium to high oxygen content, difficulties are often encountered because of thermal donor formation, which make voltage threshold adjustment steps necessary. Reducing the residual oxygen concentration eliminates this problem. Thus, while many intrinsic gettering studies have concentrated on the aspects of denuded zone depths, and the precipitate sizes and number densities, the residual bound interstitial oxygen concentration present afterwards is a crucial performance parameter. Some two-step gettering processes rely on the first oxidation in the MOS fabrication line, at a temperature of 1000-1 lOO"C, to provide some further precipitation, but as the oxides required get thinner, and oxidation times shorter, this is insufficient. An intrinsic gettering process, which overcomes these problems and permits matching, to optimize the material characteristics to individual device lines, is provided by a three-step system which separates control of the desired parameters. The concepts are illustrated in Fig. 1-36, which shows the purpose of each step. The highest oxygen concentrations, normally met at the top of Czochralski crystals, are around 1x10'' atoms/cm3 which corresponds to a maximum solid solubility temperature of approximately 12OO0C, lower for the remainder of the crystal which contains less oxygen. In step 1 the slices are heated at a temperature chosen in the range 11001200"C, above the solid solubility values for most slices, while even in the "worst cases" the supersaturation is very low. There is no precipitation and any pre-existent grown-in nuclei (Fig. 1-28) are dispersed, to ensure that all the material is in a uniform state. Out-diffusion reduces the oxygen content substantially as described above, the time, commonly in the range of

1 Silicon Processing

5-10 h, defining the chosen depth of the denuded zone to follow, Fig. l-36a. Next, in step 2, the slices are given a low temperature heat treatment, for example, at 750°C for times between 5 to 30 h. In accord with the theory a large number of small nuclei form and begin to grow slowly, except in the reduced oxygen content layer close to the surface, where very few are formed, any that are being of very small size, Fig. 1-36b. The assemblage so produced has a statistical particle size distribution, increasing slowly as longer times are chosen, while, as required by the Ham theory and depicted in

Fig. 1-36c, their total numbers remain near constant. The concept of the stability of particles of greater than some critical radius, rc, has been introduced above. The value of this radius depends on a number of factors: (a) The surface free energy of the particlematrix interface, 0, and the volume free energy change of the precipitate, AF'" (Burke, 1965), where (1-18)

Diffusion

Distance from surface X

(a)

Temperature

Distance from surface X id)

(b)

IO, 1

Oxygen diffuses t o growing

Denudedl zone I

Distance from surface X

(el

Figure 1-36. Three stage oxygen precipitation in silicon. Crystal engineering: (a) stage 1 : outdiffusion of oxygen to surface at 1 IOO'C; ( b ) stage 2: nucleation at 750°C; ( c ) particle size distributions at stage 2; (d) critical radius, rc, for particle growth as a function of temperature; (e) stage 3: particle growth at 1000°C.

1.8 Gettering Engineering

(b) The degree of supercooling, AT, the difference between the chosen anneal temperature, T , and that higher temperature at which the solute oxygen concentration, C,, is at saturation equilibrium, and the activation energy, E,, for the formation of a nucleus of the critical radius, are related by

( 2)

N , = Co exp -~

(1-19)

where N, is the concentration of precipitate particles. (c) The volume free energy is related to the supercooling and the enthalpy of reaction, AH, by (1-20)

..=(?)AT

Finally the surface free energy for the precipitate-matrix interface is obtained from (1-21) L

Values for critical radii have been calculated for various temperatures and degrees of supersaturation (Freedland et al., 1977; Osaka et al., 1980). These are all very small, ranging from around 10 A at a temperature of 1050"C, which corresponds to nuclei containing clusters of about 100 atoms, down to only 3 - 4 A and clusters of 6-10 atoms at 650°C. While these numbers are very small, it should be remembered that the final precipitates grown at 6 5 0 ° C while of platelet structure, have an "equivalent" spheroid radius of only around 30 P\ (see Fig. 1-30). The form of the temperature dependence of the critical radius is shown in Fig. 1-36d. Further extension of this model to the rates of nucleation leads to predictions

of incubation times at the outset of single stage anneals, while stable nuclei are being formed, in accord with observations (Capper et al., 1977; Hu, 1981; Inoue et al., 1981). However, the important point to note is that the critical radius is temperature dependent, and at 750 "C is much smaller than at 1000°C. Therefore, when in stage 3 the slices are heated for some hours at 1000°C most of the small particles generated at stage 2 redissolve, leaving only those at the upper end of the statistical distribution to continue to grow. A longer heating time at stage 2 leaves more larger nuclei - so this stage defines the number density to particles from the overall precipitation process. The final stage then determines how much of the oxygen initially present is to be precipitated, and so the particle size, see Fig. 1-36e (Wilkes, 1988). The matrix of Fig. 1-37, taken from the work of Huber and Reffle (1983), shows this three-stage process in operation. All the slices were given the same stage 1 out-diffusion of 10 h at 1 100"C then groups were nucleated at 750 "C for increasing times, before the final precipitate growth at 1000 "C again for 4 increasing times. The expected pattern is seen with all having about the same denuded zone depth, while the particle density increases with stage 2 time, down the figure, and the particle size with stage 3 time, from left to right across the figure, in a well-controlled manner. The ability of the threestage process to handle a wide range of input oxygen concentrations is shown in Fig. 1-38 in comparison with two-stage results, where the high and consistent reduction in the initial oxygen level achieved ensures minimal further precipitation during subsequent device fabrication. In summary then, a three-stage intrinsic gettering process can overcome the earlier problems met in two-step methods. It ac-

1 Silicon Processing

Figure 1-37. A three-stage precipitation matrix. Note the clear separation of stage functions defining: (1) the denuded zone depth, ( 2 ) the number density, and (3) the precipitate size. Stage ( I ) was outdiffusion at 1100°C for 10 h. The initial oxygen concentration was 8 . 1 5 ~ 10” atoms/crn3. (By kind permission of Huber and Reffle, 1983.)

cepts a wide input oxygen range, and the functions are separated, with stage 1 defining the denuded zone, stage 2 the particle density, and stage 3 the particle size and the total amount of supersaturated bound interstitial oxygen removed from solid solution. The three stages allow the parameters to be

varied to meet individual customer requirements to match the material to the specific device fabrication process. Today closer links between the silicon suppliers and the users are essential. The crystal engineering of large diameter wafers has been noted previously in regard to the

1.9 Acknowledgements

Figure 1-38. The reduction in bound interstitial oxygen after two-stage (0)and three-stage annealing (x). The marked superiority of the three-stage process is obvious.

Initial oxygen concentration 110’~atoms/cm3)

rising demands for the control of the oxygen level in pf and n+ substrate materials, in addition to the attention already paid to this in normal p and n silicon. Both intrinsic and extrinsic gettering have been studied and practiced for many years. Properly engineered CZ crystals incorporating internal or external gettering or both have been shown to benefit device performance. As in the other sectors examined in this chapter, in wafer manufacture the market pressures have been linked closely to the advances demanded in the technical attributes engineered into the material. Knowledge of the interaction between crystal microdefects and impurities, and device fabrication and performance has increased dramatically, and has impinged on the whole process, from crystal growth onwards, which has become more and more specialized, in the hands of the high capacity merchant producers. It is here, where the closest collaboration between the silicon material vendors and the device makers is most essential.

1.9 Acknowledgements The work described here represents over 30 years of continuing research and development. The author is indebted to his many colleagues in the Materials Departments at Philips/Mullard, Southampton for their years of valued, exciting, and enjoyable, support. Particularly I must record my thanks to Dave Perkins, Roland Kingsnorth, Dave Griffiths, and Ian Baldwin, and, for their encouragement, to Stand Bradshaw, and Dr. Max Smollett and Dr. Brian Avient. I also wish to recognize our long collaboration with the U.K. teams led by Prof. Ron Newman (Reading University), Dr. Keith Barraclough (RSRE, Malvern), and Prof. Ed Lightowlers (London University), in a wide range of joint projects. The contributions to my understanding of the silicon field from many friends in the major equipment and materials suppliers, and device houses around the world must be noted. In particular, Bob Lorenzini (Siltec), Rem0 Pellin and Gordon Martin (Monsanto), Ken Jackson (Bell Labs.), Ed Giess (IBM), and Don Jackson (Motorola), have shared and discussed new developments

1 Silicon Processing

over a long period. The close links with Dr. Erhard Sirtl and Dr. Dieter Huber (Wacker Chemitronic) have contributed directly to the preparation of this chapter. Figure 1-37 (first published by Wilkes, 1983) came from the work of Huber and Reffle, and was reproduced with their permission, while Horst Fleischmann has been a prime source for my awareness of the market pressures and industry trends.

1.10 References Abe, T., Kikuchi, K.. Shirai, S . , Muraoka, S . ( 1 9 8 1 ~ in: Srmicoriductor Silic,ori 1981: Huff, H. R., Kriegler. R. J . , Takeishi, Y. (Eds.). Pennington. NJ: Electrochem. Soc.. PV81-5, p. 54. Akiyama. N., Yatsurugi. Y., Endo. Y., Imayoshi, Z.. Nozaki, T. ( l973), Appl. Phys. Lett. 22, 630. Amouroux, J., Morvan. O., Apostolidou, H., Shootman. F. (1986). Electrochem. Soc. Exretided Abstr. No. 298. PV86-I. 441, Aulich. H. A,, Eisenrit. K. H., Schulze, F. W.. Strake. B.. Urbach, H. P. (1985), 6th E.C. Photo\dtuic Energ? Conf London: Comrnun. Eur. Cornmutiities Rep. EUR 10025. p. 95 I , Bains. S . K., Barraclough. K. G.. Griffiths, D. P.. Series. R. w.. Wilkes. J . G. (1990), J . Electrochem. Sac. 137, 647. Barraclough, K. G . (1982), in: S y m p Aggregtirioti Phenomenu of Point Defects in Silicon, ESSDERC, Munich: Sirtl, E., Goorissen. J . , Wagner, P. (Eds.). Pennington, NJ: Electrochem. Soc., P V83-4, p. 176. Barraclough, K . G.. Series, R. W. (1988), Patent GB 8 805 478. Barraclough, K. G., Wilkes, J. G. (1986), in: Seniicotiductor Silicon 1986: Huff, H. R., Kolbesen, B. 0.. Abe. T. (Eds.). Pennington. NJ: Electrochem. Soc., PV 86-4, p. 889. Batterman, B. W., Hildebrandt. G . ( 1968), Actu Crystallogr: A24, 150. Benton, J. L., Kimmerling. L. C.. Stavola, M. (1983). Physicti B 116, 271. Bergholtz, W.. Binns, M. J., Booker, G. R.. Hutchins o n . J . C.. Kinder, S. H.. Messoloras, S . , Newman, R. C.. Stewart. R. J.. Wilkes. J. G . (1989). Phil. Mug. R 59, 499. Binns, M. J . , Brown, W. P., Livingston, F. M., Messorolas, S . . Newman, R. C., Stewart, R. J., Wilkes. J. G. (19831, Appl. Phys. Lett. 42, 525. Bischoff. F. (1954). Patent DBP 1 134 459. Bloem. J., Classen, W. A. P. (1980), J . Cpsr. Growth 49. 435 (part I ) , and 807 (part 2). Bloem. J . . Classen. W. A. P. ( I 983-84). Philips Tech. Rei: 41. 60.

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2 Compound Semiconductor Processing

J Brian Mullin

Electronic Materials Consultancy. Malvern. Worcestershire. U.K.

List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Historical Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Purification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 2.3.1 General Purification Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Zone Refining and Related Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 Problems with Specific Compounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3.1 InSb and GaSb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3.2 InAs and GaAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3.3 InP and G a P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3.4 II-VI Compounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Technical Constraints to Melt Growth Techniques . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Chemical Reactivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 Melting Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 Vapor Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 2.5.1 Horizontal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 Vertical Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 Crystal Pulling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 Liquid Encapsulated Czochralski (LEC) Pulling . . . . . . . . . . . . . . . . . . . . . . . 2.5.4.1 The Low Pressure LEC Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4.2 The High Pressure LEC Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Crystal Growth of Specific Compounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 InSb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.2 InAs and GaAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.3 InP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4 II-VI Compounds: General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4.1 Bulk Hg, -,Cd, Te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4.2 CdTe and Cd,-,Zn, Te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4.3 ZnSe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.4.4 ZnS and CdS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Fundamental Aspects of Crystal Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7.2 Temperature Distribution, Crystal Shape and Diameter Control . . . . . . . . . 2.7.3 Solute Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

69 70 70 73 73 74 74 75 76 76 76 77 78 79 79 79 80 82 84 86 86 86 87 88 88 90 92 92 93 94 94 95 96 96 99

2.7.4 2.7.5 2.7.6 2.8 2.9

2 Compound Semiconductor Processing

Constitutional Supercooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Facet Effect. Anisotropic Segregation and Twinning .................... Dislocations and Grain Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wafering and Slice Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

100 102 105

106 107

List of Symbols and Abbreviations

c,, c,, c, solute or dopant concentration (in the solid, in the liquid, at the interface)

depth of volume of convecting gas diffusion coefficient temperature gradient Miller indices latent heat of fusion dopant distribution coefficient equilibrium dopant distribution coefficient thermal diffusivity gradient of liquidus gas pressure pressure of gas, pressure of dissociation vapor of components Rayleigh number temperature growth velocity

D G h, k, 1 Hf k k0

KO m P PG, pd Ra

T V

boundary layer “thickness”, parameter of BPS model angle kinematic viscosity crystal density thermal conductivity interfacial energies angular rotation rate

ACRT BPS CRA HG LEC LPE MBE MCT MOVPE PBN PPba PPm QA RF SI TGZM THM VGF VP

accelerated crucible rotation technique Burton, Prim and Slichter cast recrystallize anneal horizontal growth liquid encapsulated Czochralski (techniques) liquid phase epitaxy molecular beam epitaxy mercury cadmium telluride metal organic vapor phase epitaxy pyrolytic boron nitride atomic parts per billion parts per million quench anneal radio frequency semi-insulating temperature gradient zone melting traveling heater method vertical gradient freeze (technique) vertical pulling

Qs 0

hi$S,

4 G

2 Compound Semiconductor Processing

2.1 Introduction

2.2 Historical Background

This chapter reviews the general principles and practice governing the preparation and processing of compound semiconductors and their alloys, how they are purified, how they are prepared as single crystals and how they are converted into wafers suitable for epitaxial growth. The range of materials which can be classified as compound or alloy semiconductors is vast and covers the whole of the periodic table. It includes IV-IV, 11-IV, I-v, 11-v, 111-v, I-VI, 11-VI, 111-VI, IV-VI. v-VI, I-111-VI, I-IV-VI, I-vVI, 11-IV and 11-111-V compounds. However, because of the enormous cost of developing these materials as high-quality semiconductors most of these compounds are currently in a relatively primitive state of development when compared with Ge or Si. Indeed the only compounds which have been developed to a state of significant commercial application are to be found in the 111-V and 11-VI semiconductor groups of materials. It is with these classes of materials that this chapter will be mainly concerned. The efficient processing of semiconductors in a form suitable for device application requires a sound understanding of the practical technologies involved together with a knowledge of the scientific principles underlying these technologies. Both the technology and the science of the processing will be covered in this chapter. However, it is important to appreciate that the technology as opposed to the science of semiconductor processing is undergoing a constant evolution driven by ever more demanding specifications arising from of an ever increasing range of devices.

Probably the most important event which promoted significant scientific and technological research in the processing of semiconduction materials was the discovery of transistor action in germanium by Brattain and Bardeen (1948) which had been stimulated by the predictions of Shockley (1949). As a result serious international interest developed in the search for new semiconductors. 11-VI compounds had of course been known since before the beginning of the century, but the early work of Welker (1952, 1953) and his colleagues in Germany on 111-V compounds following the discovery of transistor action marked the beginning of the evolution of compound semiconductor processing. Our knowledge of semiconductor processing (Mullin, 1975 a, b, 1989; Thomas et al., 1993), indeed of all aspects of semiconductors and the solid state, is rooted in research on Ge in the 1950s. Even early work in this period highlighted the two overriding requirements for semiconductors, the need for high purity and the need for single crystals. The first requirement resulted in the creation of new methods of purification and the evolution of a most significant concept, the concept of semiconductor purity. This specified the need for unprecedentedly low levels of impurities, typically less than 10 parts per billion atomic (ppba) of electrically active impurities. The second requirement resulted in the development of new technologies for producing completely single crystals free from defects including dislocations. At the forefront of this materials work aimed at fulfilling these demands of purity and crystalline perfection was the development of the science and technology of crys-

2 . 2 Historical Background

tal growth. In less than a decade the intense research and development effort resulted in the melt growth of Ge developing from an art to a science. In the case of the compound semiconductors, the less difficult materials, like InSb, followed the pattern of evolution of Ge, and single crystals containing less than carriers/cm3 (1 ppba is equivalent to atoms/cm3) were state of the art 2.9 x well within a decade. However, in the case of the more difficult materials like GaAs, InP and Gap, their evolution has taken over three decades and is still in a development phase. For the very difficult materials like ZnSe no melt growth technology has yet been devised that can achieve reproducibly and readily acceptable quality single-crystal material, although there are promising developments (Rudolph et al., 1994). For ZnSe, vapor growth techniques are pioneering the way to semiconductor quality (Cantell et al., 1992). The key to the development of Ge was the creation of new melt growth technologies. Very significant contributions to our knowledge resulted from the pioneering work of Pfann (1966) on zone melting and Teal (1958) on the vertical pulling of single crystals. Pfann (1966) initiated the concept of zone melting. This generic term covers a range of related horizontal crystallization technologies. The simplest technology is the single zone freeze in which a horizontal boat containing a molten charge is progressively frozen from one end. Other procedures were developed involving the translation of a liquid zone through a solid ingot. In particular it created two very powerful processing technologies, zone leveling and zone refining (see Sec. 2.3.2). Zone leveling was initially applied to Ge and resulted in a very successful crystallization technology for the production of

uniformly doped single-crystal material. This process involves the formation of a liquid zone in a solid ingot and its movement through the ingot in one direction and subsequently, for ideally uniform material, in the reverse direction. The liquid zone acquires a constant dopant concentration l / k times that in the solid, where k, the distribution coefficient, is given by k = Cs/C, and C, and C, are the concentrations of dopant in the solid and liquid respectively. This process levels out the dopant concentration in the solid so that the dopant concentration of the solid being melted is the same as the concentration in the solid being crystallized. The horizontal technologies were not only used for zone leveling and for purification by zone refining but they were also developed for the growth of single crystals. This was achieved by arranging for a molten zone to melt-back into a single crystal seed positioned at one end of a polycrystalline ingot. The solid which crystallized on the seed as the zone was moved through the ingot took up the orientation of the seed and resulted in the formation of a single crystal. In addition to H G for the growth of single crystals, the use of VP of crystals from the melts was pioneered by Teal (1958). The technique has its origins in the Czochralski technique. Czochralski (1917) arranged to dip a thin rod which acted like a seed into a molten melt of metal and withdraw it from the melt. As the liquid was pulled away from the melt it crystallized, giving regions of single crystal metal. However, this technology is far removed from modern crystal pulling technology. The modern pulling technique (Teal, 1958) was developed during the initial phase of semiconductor research at Bell Labs in the 1950s and early 1960s. The most important innovation was the intro-

2 Compound Semiconductor Processing

duction of rotation using a pull rod. A single-crystal seed was mounted in a chuck on the pull rod which could be raised and lowered at a set rate. In the pulling process the crystal nucleated on the seed and its diameter was controlled by adjusting the power to the melt. This concept had profound consequences for the semiconductor processing of single crystals. Theoretical work on crystal pulling has also had an important influence on the development of the technology. The work of Burton, Prim and Slichter (BPS) (Burton et al., 1953) on solute distribution during crystal growth proved to be most significant. They modeled solute transport in the melt adjacent to the rotating crystallizing surface using concepts developed by von Karman (1921) and Cochran (1934). BPS established the flow normal to the disc as a function of the crystal growth parameters enabling quantitative estimates to be made of the solute distribution from the interface into the melt. Use of the BPS model has stimulated much research and laid the foundations of a great deal of our understanding of the science of crystal growth from the melt. It has been used, for example, in the modeling of heavy doping during crystal pulling. This has resulted in a predictive theory of constitutional supercooling (Hurle, 1961; see Sec. 2.7.4). This knowledge is directly relevant to the crystallization of compound semiconductors from nonstoichiometric melts, where constitutional supercooling is a very common occurrence and can be a major problem seriously affecting crystal quality. The causes of nonuniform dopant or impurity incorporation are a major consideration in understanding the mechanisms of crystal growth. Of particular significance has been the discovery of the facet effect (Hulme and Mullin, 1959) and anisotropic

segregation (Mullin, 1962) of dopants during crystal growth. Also important are impurity striations, which are a common occurrence. Crystal rotation introduces periodic impurity incorporation due to the growth rate variations imposed by the rotating crystal. The incorporation of dopants will be developed in further detail in Sec. 2.1.5. The science of horizontal growth (HG) has lagged significantly behind that of vertical pulling (VP). In H G there is no effective working theory for convection in the molten zone and transient control of doping as opposed to uniform doping is not possible as it is in VP. The VP technique thus evolved as a favored tool for investigating the science of crystal growth from the melt. From an historical viewpoint it is instructive to follow the evolution and role of H G and VP techniques in relation to the science and technology of Ge and Si. The horizontal growth of Ge, a technology that pioneered purification by zone refining and the production of doped single crystals by zone melting, gradually emerged as the more cost effective crystal growth process and replaced the VP technique. Ultimately however, the semiconductor applications of Ge were taken over by Si, eliminating the need for Ge altogether with the exception of a few specialist applications such as the growth of very large crystals for detectors. These are fulfilled by pulling. It is interesting that the VP technique that was developed for Ge created the conditions for the single-crystal growth of Si. Silicon with its superior device properties has emerged as the dominant semiconductor and as such has had and continues to have a profound influence on every aspect of semiconductor processing. The VP technique has been refined and developed for Si and is still the dominant industrial tech-

2.3 Purification

nology for Si. But, also of major importance for Si is the float zone technique, in which a liquid zone out of contact with the container is moved through a vertical rod of Si. This zone refining action produces the very highest grade of single-crystal Si, a very important industrial requirement. Nevertheless, it is important to recognize that some of the unique properties of the compound semiconductors have also stimulated developments in semiconductor processing. Undoubtedly the very rapid expansion in our knowledge of semiconductor processing can be attributed to the relative ease of handling Ge and in particular to the ability to hold and crystallize molten Ge with negligible contamination from silica apparatus. The technology of Si is in many ways very different to that of Ge. It reacts with SiO, and cannot be crystallized in a silica boat. It also forms a tenacious oxide which requires special techniques to prevent its formation. Hence the importance of the pulling technique and the noncontacting float zone technique in its development. Technology never stands still. Zone refining has been developed (Hukin, 1989) for Si using a horizontal water-cooled Cu boat. A liquid zone is formed and levitated out of contact with the boat using RF fields. Two-meter, 125 cm2 section solar cell grade Si can be produced in this way. The 111-V and 11-VI compounds present different problems again to those of Si. The antimonides are similar in their attributes to Ge but the arsenides and the phosphides, selenides and tellurides suffer dissociative decomposition near their melting points, resulting in the loss of one of their component elements. As a result, closed-tube techniques needed to be developed in order to prevent vapor loss. This has stimulated new technologies such as

liquid encapsulation and more recently the vertical gradient freeze (VGF) technique to overcome this problem. The relatively slow development, over three decades, of these compounds is in no small way due to the difficulties associated with dealing with compounds which have a significant vapor pressure at the melting point. In addition the number of point defects at the melting point is high -10” cm-3. This leads to extended defects and doping nonuniformities and a range of problems not found in Si and Ge. The continuing challenge of processing technology is to understand and control these problems.

2.3 Purification The cost of developing the knowledge and technology to be able to process raw materials into device quality semiconducting compounds is enormous and inevitably involves a very significant research and development effort involving both purification and crystal growth. As a consequence, there are only a few highly developed compound semiconductors. These include InSb, GaAs, InP, GaP and CdTe and its related alloys with HgTe. Most of the IIVI compounds are still not readily available in wafer form as high-quality singlecrystalline material. The basic aspects of the purification technologies required to produce high-purity semiconducting compounds will now be considered. 2.3.1 General Purification Procedures

It is convenient to identify two stages in the purification of semiconductor compounds, firstly the purification of the elements themselves and secondly the purification of the compounds. From an historical perspective the role of the more con-

2 Compound Semiconductor Processing

ventional chemical purification procedures has been more useful than zone refining in purifying the elements. This can be appreciated from the early reviews in Willardson and Goering's book on 111-V compounds (1962). It is evident that work on zone refining of group I11 metals as well as phosphorus and arsenic was clearly not seen to be markedly effective. This coupled with the fact that zone refining represented an additional costly batch process meant that its use has always been problematical, especially for elements like In and Ga which are low melting point readily alloyable metals with a tendency, in the case of Ga, to supercool. Whilst zone refining has not been particularly useful for the common elements of groups I11 and V, in the case of groups I1 and VI zone refining has proved to be a very effective process for the production of ultra-pure Cd and Te. This development was made possible by military funding since these elements arse used in the preparation of HgCdTe for infrared detectors. Here very high purity elements, having less than 1 part in lo9 electrically active impurities are essential. It is evident that zone refining is most effective for strongly bonded materials which crystallize well and in which impurities have a low solubility. These criteria apply particularly to the compounds themselves. Thus many compounds can be zone refined but most compounds have their own peculiarities, demanding specialized processes. These will be considered for the more important compounds later.

purification procedure for Ge. The impurities that are less soluble in the solid, or more soluble in the liquid ( k , < l ) , are moved in the direction of crystallization towards the finish (last to freeze) end of the ingot whereas the impurities that are more soluble in the solid ( k , > l), that is, less soluble in the liquid, are moved to the start end of the ingot. Provided the distribution coefficients k , are not close to 1 - a condition satisfied by Ge - this very simple process can after very few zone passes produce semiconductor purity in an ingot. A remarkable result. One can appreciate the effectiveness of zone refining from the graphs in Fig. 2-1, where the theoretical ultimate distributions for impurities having different distribution coefficients are given. Orders of magnitude improvement in purification are indicated. However, these dramatic results must only be taken as a guide since solid-state diffusion and vapor transport can reduce the effectiveness of impurity removal.

2.3.2 Zone Refining and Related Techniques

' The equilibrium distribution coefficient k , of a solute (dopant, impurity or excess component) is the ratio of the concentration of the solute in the solid, C, to the concentration of the solute in the liquid, C,,if the phases are kept in contact for a sufficiently long period for them to come to equilibrium.

Zone refining, which involves the motion of a liquid zone or zones through an ingot, is the most important and effective

2.3.3 Problems with Specific Compounds Processing by conventional zone refining or chemical purification methods is often insufficient on its own as a means of achieving semiconductor purity in compounds. Inevitably there is some problem or problems, some difficult-to-remove residual impurity or some quirk of contamination that needs to be dealt with in an unconventional manner if the ultimate goal of semiconductor purity is to be achieved.

2 . 3 Purification

log

Initial concentration

I -24

-30I

Length solidified

Figure 2-1. Theoretical ultimate distributions for dopants having different distribution coefficients ( k ) after multiple zone refining passes in an ingot where the zone length is 10% of the ingot length. It is assumed that there is no back reflection of dopant from the freezing of the last zone length. The results highlight the potential of zone refining (see Pfann, 1966).

In this section problems or aspects of purification will be considered which have proved to be important in the achievement of semiconductor purity of the more important compound semiconductors. It should be stressed that achieving semiconductor purity in compounds is a very demanding and generally costly process and one that is frequently underestimated. The processes of purification and the avoidance of contamination represent a continuous battle if the ultimate in semiconductor performance is to be achieved. In the case of many of the 11-VI compounds for example the presence of impurities could still be the principal problem preventing their effective development.

2.3.3.1 InSb and GaSb Indium antimonide (Hulme and Mullin, 1962) has attracted much more research and development (R&D) over the years than GaSb. Major factors in this interest are of course the device applications of the material. InSb, for example, is an impor-

tant infrared detector material suitable for detectors working in the 3-5 pm region of the spectrum. The low melting point of InSb, 525"C, combined with the negligible vapor pressure of Sb over its melt make InSb an ideal candidate for conventional zone refining procedures. However, the straightforward process is of limited value because of troublesome impurities, particularly Zn and Te. Not only do they exhibit anisotropic segregation (Mullin, 1962), but in the case of Te the value of its effective distribution coefficient, keff (see Sec. 2.7.5) can range from -0.5 for growth in an non[lll]direction to -4.0 for growth on a (1 11) facet. Thus Te would be distributed in polycrystalline material as though the effective k were some weighted mean of these values, that is, close to one. Zinc has a value of keffranging from 2.3 to 3.0. But more troublesome is its volatility at the melting point of InSb. Vapor transport of Zn above the ingot can reduce the efficiency of zone refining. This problem has been overcome by using the volatility of Zn to advantage in a two-stage evaporation and zone-refining procedure (Hulme, 1959). Zone-refined Sb in excess of that required to form stoichiometric InSb is added to high-purity In in a boat in a modified zone-refining apparatus and melted under vacuum. Both Zn and Sb evaporate from the molten charge and condense on the cooled upper surface of the outer containing tube. The excess Sb traps in the very small quantity of the more volatile Zn. After a timed period when the excess Sb has evaporated the ingot is cooled and frozen. It is then zone refined under an atmosphere of H,, a condition where the Sb has negligible volatility. The purification process is highly reproducible, resulting in the production of very high

- -

2 Compound Semiconductor Processing

purity InSb with some 60% of the ingot having a carrier concentration less than i 1014 cm-3. GaSb has not been developed in this way but it can be zone refined. The incentive to purify the material further, however, is limited by the belief that the residual p-type carriers per carrier level, - 2 x cm3, is determined by fundamental aspects of the band structure of the compound.

2.3.3.2 InAs and GaAs InAs and GaAs present additional handling problems because at their melting points the As dissociation pressures are respectively -0.3 and 1.0 atm. Nevertheless, considerable R&D effort has been carried out on GaAs using conventional hot wall technologies. However, a major problem encountered on zone refining GaAs has been the failure to achieve purities with carrier levels below 1OI6 to 10’’ n-type carriers per cm3. This has been shown by Hicks and Greene (1971) to be due to the reaction between Ga in the liquid Ga, As melts and the silica containing vessel, which introduces a fairly constant level of Si into the ingots at about one part per million: (2- 1) 4Ga(L)+Si02(S)=2Ga20(V)+Si(soln)

The problem can be overcome by using BN or graphite boats. However, the zonerefining process has generally been superseded and simplified by in situ compounding of very high purity Ga and As which are now available as a result of improvements in chemical purification methods (see Sec. 2.6.2).

2.3.3.3 InP and GaP The very high vapor pressures generated by these compounds at their melting points, some 27 atm and 32 atm for InP

and GaP respectively, makes zone refining a difficult and potentially hazardous process. The compounds can nevertheless be prepared in horizontal systems by distilling the P, into the molten group I11 element contained in a silica or BN boat. By limiting the amount of group V distilled so that the group I11 element is in excess of stoichiometry the working vapor pressures are reduced. Crystallization under these conditions has an additional advantage; there is a very much greater purification effect for impurities from group I11 rich liquids than from stoichiometric melts. The disadvantage of course is that crystallization occurs under conditions of constitutional supercooling, which can result in trapping of the impurity-rich group I11 element in the solid. With the availability of purer starting elements, formation of the compounds from stoichiometric melts is now more usual. Nevertheless, further purification is generally required, and is now often achieved by pre-pulling charges using the liquid encapsulation technique. InP having 1015carriers/cm3 can be produced in this way. A similar purification procedure for GaP can be used. The current commercial demands on GaP are somewhat less than on InP since it is either used as doped material or as a substrate on which active layers are grown. There is clearly scope for the development of further purification procedures for both these compounds.

2.3.3.4 11-VI Compounds The state of development of the 11-VI compounds is significantly behind that of the 111-V compounds even though they have a much longer history. Many of the 11-VI compounds, especially the higher energy gap oxides, sulfides and selenides, are not accessible by melt growth tech-

2.4 Technical Constraints to Melt Growth Techniques

niques and as a consequence there is a much greater emphasis in the use of vapor growth techniques to grow these difficult compounds. Our knowledge of the use of vapor growth as a purification technology is primitive. There is no equivalent to zone refining. Hence there is a more general tendency to rely on the use of elements that have been purified chemically or by zone refining. The elements Hg, Cd and Te, components of the exceptionally well developed infrared detector material Hg, -$d,Te, are now available as very high purity elements as a result of multiple zone refining technologies (Cd and Te) and distillation techniques (Hg). Hence compounds of these elements are prepared in situ by direct reaction. Most of the other elements Zn, Se and S although currently available in conventional high purity form are generally not as pure as the detector materials and do not form very pure semiconducting compounds. Zone refining of the 11-VI compounds is not efficacious because of the volatility of both the group I1 and group VI elements as well as the compounds themselves. Hence there has been little development of conventional zone-refining technology for the compounds. However, a related zone-refining technology called the traveling heater method (THM) or sometimes the traveling solvent method has attracted much interest and development for the 11-VI compounds. In the traveling heater method a molten zone is moved through the ingot as in zone refining, but in THM the zone comprises a solvent of Te or Se. Thus the compound dissolves at the leading edge of the zone and crystallizes out at the trailing edge. This has two advantages. Firstly, it reduces the temperature of crystallization significantly below the melting point of the

compound, thus markedly reducing the vapor pressure of the components of the compound, effectively eliminating evaporation. Secondly, it provides a group VI rich solution in which impurities are exceptionally soluble, a condition which results in the crystallization of a very pure compound. Because of the reduced growth temperature it is also possible to eliminate sub-grain boundaries. The technique, however, has not yet been developed to grow large completely single crystals. The process has been exploited particularly by Triboulet (1994) and the CRNS Bellevue group for the preparation and purification of Hg, - $d,Te, Hg, - .Zn,Te, CdTe, HgTe and ZnTe, as well as CdMnTe. It clearly has scope for the preparation and purification of ZnSe and various alloys of the compounds. The potential disadvantage of the technique is that the crystallization occurs under conditions of constitutional supercooling and solvent trapping can occur and give rise to group VI rich precipitates toBether with impurities. Nevertheless it would appear that by optimizing the temperature gradients and the gradient of constitutional supercooling (see Sec. 2.7.4) the worst effects of solvent trapping can be avoided.

2.4 Technical Constraints to Melt Growth Techniques The processing of compound semiconductors by melt growth techniques both for purification and crystal growth is generally much more difficult than the processing of Ge because of constraints imposed by the properties of the materials. Some of the significant properties which lead to constraints in the use of melt growth and related processing are listed in

2 Compound Semiconductor Processing

Table 2-1. Material properties of main semiconductors. Compound

Melting point ("C)

Vapor pressure at M.Pt.(atm)

InSb GaSb InAs GaAs InP GaP HgSe H gTe CdSe CdTe

525 712 94 3 1238 1062 1465 799 670 1239 1092

4 x lo-' 1 x 10-6

ZnSe ZnTe Ge Si

1526 1300 960 1420

0.5 0.6

0.33 1.o 27.5 32 12.5 0.3 0.65

CRSS at M.Pt (MPa)

0.7 0.36

0.2

0.70 1.85

Table 2-1. Consideration of a wider range of properties, chemical reactivity, melting point, vapor pressure, critical resolved shear stress and ionicity are important in understanding the suitability, or more often, the unsuitability of a particular technology.

2.4.1 Chemical Reactivity Although not specifically listed in Table 2-1, chemical reactivity is an important constraint in all processing. The main problems arise from the reactivity of the molten semiconductor with the container or the gaseous environment. In this respect container materials have proved to be the dominant source of contamination for compound semiconductor melts. Vitreous silica is widely used as a crucible or boat material and is essentially stable against attack from the lower melting point materials like Ge (937"C), InSb (525°C) and GaSb (712°C). But, for higher melting point materials there is gen-

References

Muller and Jacob (1984) Muller and Jacob (1984) Van der Boomgaard and Schol(l957) Arthur (1967); Thomas et al. (1990) Bachmann and Biihler (1974); Thomas et al. (1990) Nygren et al. (1971) Mayer (1984) Harman (1967); Strauss (1971) Bassam et al. (1994); Lorenz (1967) Isshiki (1992); Strauss (1971); Balasubramanian and Wilcox (1992) Isshiki (1992); Lorenz (1967) Isshiki (1992); Lorenz (1967) Thomas et al. (1990) Thomas et al. (1990)

erally contamination with silicon due to the reduction of the SiO, by the melt, in the case of GaAs (1238°C) it is typically above the part per million (ppm) level in the crystallized material. Pyrolytic boron nitride PBN can be used to overcome this problem and is well suited to the growth of 111-V compounds since it is a 111-V also and does not appear to give rise to electrically contaminating impurities. It is however expensive. Graphite is also used since it is stable in an inert atmosphere and does not appear to directly cause electrically active doping by contaminating melts. Graphite will react with silica at high temperature, but at lower temperatures ( < 900 "C) it is a very useful material and is used as a slider boat material in liquid phase epitaxy (LPE) and as a boat material for 11-VI compounds. But, carbon can be electrically active as an acceptor in GaAs for example. It can be introduced on an As vacancy site via CO under Ga-rich growth conditions, hence the importance of removing 0, and H,O.

2 . 5 Crystal Growth

Another potential source of impurity contamination are the impurities such as S etc. in the graphite. These can generally be removed by vacuum heat treatment at very high temperatures ( > 1500"C). Graphite is a very useful material but since it varies in quality must be used with care. The gaseous environment is also a major cause for concern. Processing in vacuum is possible, but the volatility of the group V, I1 or VI components needs to be taken into account. This is discussed later. All the melts and compounds oxidize readily and it is vital to remove all sources of oxygen such as 0, and H,O from the source materials and the environmental gases. Pure H, or forming gas are very effective reducing agents and will remove oxides readily at temperature. Hydrogen does however react to form unpleasant poisionous 'hydrides and extreme precautions need to be taken to avoid leaks not only with pure H, but also with forming gas (N,/H, mixture). Pure inert gases such as N, ,A or He are safer and consequentally are more frequentally used.

2.4.2 Melting Point The melting point affects the choice of crucible material, and with it the extent of chemical reaction. Also, above about 1000°C radiation fields tend to dominate thermal distribution, creating design problems and the need for radiation baffles. Also, above 1100-1200°C silica starts to soften, which generally means it needs to be supported by another material such as graphite.

2.4.3 Vapor Pressure Vapor pressure is probably the most crucial parameter affecting melt growth technologies. The long delay in the development of GaAs, InP and GaP is attributable

in part to the problems posed by the vapor pressure of the group V component generated on melting these compounds. Thus a melt of these materials will rapidly lose its group V component unless there is a pressure of the group V component above the melt at least equal to the equilibrium vapor pressure over the melt. Two types of technology have emerged to deal with this problem: hot wall technology and liquid encapsulation (see Sec. 2.5).

2.5 Crystal Growth The main techniques for growing crystals of compound semiconductors can conveniently be grouped into four categories: horizontal growth, vertical growth, crystal pulling and liquid encapsulated Czochralski (LEC) pulling. Although this classification differentiates the techniques by the physical disposition of the different growth processes it is very important to appreciate that each technology gives rise to different crystallization conditions which affect the quality and efficiency of production for different 111-V compounds. Factors such as the ease of seeding for crystal growth, crystal shape, twinning, the effect of growth in a constrained volume, temperature gradients, visibility and the economics of production and ease of automation are critical factors in the choice of a particular technology. The suitability of these techniques for particular compounds, which are listed in Table 2-2, have evolved with time and experience. They have all been refined for particular applications and are still undergoing both research and commercial development. Their application to the growth of particular compounds will be discussed in later sections.

2 Compound Semiconductor Processing

Table 2-2. General applicability of growth techniques. a Technique: Compound ~

Zone melting horizontal Bridgman

VGF vertical Bridgman

Conventional vertical pulling

Liquid encapsulation pulling

Vapor growth

InSb GaSb InAs GaAs InP GaP HgSe H gTe CdSe CdTe ZnSe ZnTe HgS ZnS CdS

*** *** *** *** * *

* ***

P P P

c*** : L*** c * : L** c * : L**

** *** ** *** ** **

*** *** *** ***

*** ***

P P

P P P P

P P

***

*** *** *** *** *** ***

The more stars, currently the more appropriate the technique. P: potentially applicable; C: conventional VGF; L: LEC VGF.

2.5.1 Horizontal Growth

Horizontal growth (HG) is used here to cover all the horizontal crystallization techniques. They represent a subset of the zone-melting technologies described by Pfann (1966). A typical horizontal growth arrangement is shown schematically in Fig. 2-2 and discussed more fully in relationship to the growth of GaAs in Sec. 2.6.2. The growth of a single crystal can be carried out by controlled freezing of an ingot of molten semiconductor in a boat. The singularity of the ingot is achieved either by relying on self-seeding or through the use of a single-crystal seed which initially contacts the melt. The technique is often referred to as the horizontal Bridgman technique when the ingot is withdrawn from a furnace. The furnace can of course be moved relative to the ingot and this can be beneficial in that there may be less mechanical disturbance to the ingot and the crystallization process.

In the case of compound semiconductors the main problems generally concern the need to accurately control the thermal profiles, hence the movement of large furnaces tends to be undesirable and a combination of power control and the movement of small independent heaters is generally preferred in order to carry out the crystallization process. These benefits can also be achieved by using furnaces with independently controllable windings so arranged that the thermal profile can be moved. The attraction of H G stems from its relative simplicity and ease of automation. The method can be applied readily to compounds that can be processed in vitreous silica, that is, for compounds melting at temperatures less than about 1250 "C having vapor pressures at the melting point not significantly in excess of one atmosphere. An advantage of the HG is that it can be used to prepare the compound from the elements as an ingot which can then be subsequently zone refined in the same ap-

2.5 Crystal Growth

Figure 2-2. Schematic of a conventional horizontal growth apparatus used for the preparation and zoning of 111-V compounds. The ingot in the boat B is contained in a sealed tube A. C is the boat used to hold the volatile component prior to its distillation into the group I11 element in A in order to form the compound. D is an anticonvection bame and E the tube support for the thermocouples H and their support tube. F is a multiple section furnace. G is the traveling heater for the zone formation and movement.

paratus. Such an ingot can also be grown as a single crystal and even zone refined as a single crystal without taking it from the same apparatus. In situ compounding of the elements can also be used in vertical pressure pulling systems (Sec. 2.6.2), but the ability to zone refine in a horizontal system is a distinct advantage when superpure elements are not available. An important advantage of the H G technique is that its design readily lends itself to the establishment of low temperature gradients at the solid-liquid interface without creating a control problem. This contrasts with the situation in the pulling process where relatively high temperature gradients are needed to maintain control of the shape of the crystal. Low temperature gradients are extremely important in minimizing stress induced slip on crystallization and hence in minimizing dislocation formation. In the case of the H G growth of GaAs it is possible to grow low dislocation density material, typically

around IO2 dislocations/cm2, a factor of 100 less than currently found in routinely grown LEC vertically pulled crystals. This is very important for laser diodes based on GaAs, where even a single dislocation can readily bring about device failure. There are, however, disadvantages to the horizontal techniques. These can be of a scientific fundamental nature, such as constitutional supercooling or stress, or they can be preparation-related and involve, for example, growth orientation, contamination, or shape. One of the fundamental problems which is not widely recognised is constitutional supercooling, which can occur as a result of a nonstoichiometric melt due to inaccurate vapor pressure control. This can be especially troublesome with low temperature gradients as is analyzed later in Sec. 2.7.4. The most troublesome problems occur as a result of the contact of the melt and the grown crystal with the boat. The long

2 Compound Semiconductor Processing

period of contact can be a source of impurities by reaction with the boat. Silicon as noted previously is a major problem with GaAs, but also the diffusion of impurities through the silica with the higher melting point compounds can also result in crystal contamination. Misnucleation from the walls of the container can give rise to twinning, grain boundaries and more often polycrystallinity. Also crystallization in a confined shape with materials like III-V compounds which expand on freezing, especially if combined with localized sticking, will inevitably lead to stress, slip and dislocation formation. However, provided nonwetting surfaces are used for the containing boats and a nonconfining boat shape is used, this problem can be minimized. Most of the disadvantages are qualitative rather than absolute. They detract from the versatility and universality of the technique. In certain cases they may not be significant, such as in the case of the growth of low resistivity GaAs, for example, for especially for material which is subsequently sliced and diced for the fabrication of small discrete devices such as laser diodes. However, for integrated circuit applications where large area uniformity is crucially important H G is unattractive. Indeed the D-shape of H G ingots alone appears to have ruled them out for integrated circuit applications. Also the growth of very large cross section ingots as single crystals is fraught with difficulty. 2.5.2 Vertical Growth

Crystallization of ingots in a vertical container by the Stockbarger or vertical Bridgman techniques used to be associated with the growth of high-quality singlecrystal optical materials like CaF,. But, in the last few years the technology has been

refined and developed as a vertical gradient freeze technique for the growth of GaAs, InP and GaP (Gault et al., 1986; Clemens et al., 1986; Bourret, 1990). The relatively recent application of the VGF technique to the growth of GaAs occurred in response to the need to find a cost effective solution to the production of uniform GaAs wafers compatible with integrated circuit technology. Here there is a requirement for circular wafers having precise dimensions and very good electrical uniformity. “Conventional” wisdom would consider that crystallization in a vertical rigid container would give rise to unacceptable stress due to the expansion of the liquid GaAs on freezing. In the event this has not apparently been a problem. The growth process is fairly straightforward and is illustrated in Figs. 2-3 a and b. In the study by Gault et al. (1986), which was a development of earlier studies (see review by Bourret, 1990), the VGF growth of large diamater Gap, InP and GaAs was reported. No B 2 0 3 encapsulant was used. The type of apparatus is illustrated in Fig. 2-3 a. However, it appears that for the reproducible growth of GaAs it is necessary to use a B 2 0 3 encapsulant in a BN crucible (Bourret, 1990) such as that illustrated in Fig. 2-3b. The B,O,, which is now more generally used for InP, is not only a more effective encapsulant, making for a safer and simpler system, but the nonwetting characteristics of the GaAs melt with respect to the container wall reduce the twinning probability. The vertical gradient freeze technique involves the controlled freezing from the bottom up of a molten charge of material held in a tube-shaped vertical container. The freezing is best brought about not by the movement of the furnace relative to the tube, but by the use of a furnace comprising separate independently controlled

2.5 Crystal Growth

.-A

-B

--A

-B

-C

-D

-D - LE

-E

-F

-E

-F

-G

-H

-G

-H -L

-I -M

-J

-K

-L

-M

Figure 2-3. Schematic diagrams of crucibles used in the vertical gradient freeze technique, (a) “Conventional” VGF showing compound F, melt E and separate holder J containing group V component K at a controlled temperature in order to maintain sufficient pressure of V to avoid the dissociation of the compound. Plug B allows pressure equilibration between the crucible and the outer chamber. Loss of group V into the outer chamber is inevitable even when PG> pd and is one of the drawbacks of the technique. A, furnace; C, BN crucible; D, main containing vessel; G, seed: H, crucible support; I, gap for group V transport; J, crucible for holding V; K, source of group V; L, base support; M, holder. (b) Liquid encapsulation VGF with PG> pd; symbols have same meaning as above. B,O, encapsulant LE covers the melt and prevents the loss of the volatile component.

2 Compound Semiconductor Processing

heating elements. Adjustment of the heating elements controls the position of the thermal profiles so that the movement of the liquid-solid interface can be raised smoothly to bring about the crystallization of an ingot. The technique provides two important growth conditions. I t naturally lends itself to low temperature gradients, which in turn favor low dislocation densities. And, secondly, it provides an ingot of ideal shape of the required diameter. Provided the interface shape is flat or at least the growth surface is slightly convex the expansion problem on freezing does not appear to be serious and any stress can be annealed out. The main problems appear to be those involving design difficulties of the thermal furnaces, the choice of boat material, BN is generally used, and the choice of conditions which allow seeding and the growth of [loo] crystals without twinning. The ingots are usually encapsulated with B,O,. Whether the technique will supersede the LEC technique for the growth of GaAs is an open question. This can only be effectiveiy assessed when commercially sensitive information on single-crystal growth yield comes available. 2.5.3 Crystal Pulling

The Teal and Little crystal pulling technique which was developed successfully for Ge was naturally tried for the 111-V compounds, but the problem of the volatility of the group V elements and their rapid loss from melts in the case of the arsenides and phosphides presented insuperable problems. The antimonides which have low dissociation pressures at their melting points can, however, be grown by any of the Ge-type semiconductor technologies. The crystal growth of the aluminum com-

pounds by either the horizontal or the vertical pulling techniques has never been developed because of the extreme reactivity of the A1 with traces of oxygen or water and with the silica boats. Any bulk material simply oxidizes in the atmosphere. The VP technique is illustrated in Fig. 2-4. The main factors affecting the design concern the type of heating, the crucible and the outer jacket. Heating can be by resistance heating or, for more versatility, induction-coupled RF power to a conducting crucible, generally graphite or a graphite support to a silica or PBN crucible. The outer jacket is usually silica and for strength reasons can only be used with internal gas pressures not in excess of about 2 atm. The growth of a single crystal involves lowering a seed mounted in a seed holder or chuck on the pull rod into a melt of the compound just above the melting point. After melting back a small amount of the seed, the seed-on process, the power to the melt is controlled so as to allow crystallization of the melt on the seed as it is gradually rotated and withdrawn from the melt. The shape of the crystal is controlled by the shape of the meniscus under the seed (Sec. 2.7.2). The whole process requires considerable operator skill and judgment. The growth can be automated by using a sensor to monitor the crystal diameter and provide feed back to the power control (Sec. 2.7.2).Constant diameter crystals are needed for producing standard sized wafers for device fabrication. This basic process can only be applied to the growth of compounds that have virtually no vapor pressure at the melting point. This is a very restrictive condition for the growth of compounds which generally dissociate near the melting point to some extent. In the case of the 111-V compounds and the 11-VI compounds the technology

2.5 Crystal Growth

is only really suitable for the growth of InSb and GaSb. As a consequence, considerable effort has been devoted to developing alternative technologies for the growth of compounds. Two types of technology aim to overcome the vapor pressure problem and loss of group V component. These are hot wall technology and liquid encapsulation technology. In hot wall technology the walls of the containing vessel surrounding the 111-V compounds are kept sufficiently hot to prevent condensation of arsenic or phosphorus on the walls. This requires temperatures of 600 "C or 700 "C, respectively, for the two elements. This condition is possible to apply in the case of horizontal crystal growth involving the use of a sealed silica tube but it creates serious technical problems in the case of a thermally complex vertical pulling apparatus since it requires the seals, pull rod and bearings, etc., to be heated and inert to the hot reactive component elements. Nevertheless, the problems of hot wall technology have been tackled by a variety of pulling methods with varying degrees of success. They are the syringe pulling and magnetic pulling methods, which have been reviewed by Gremmelmaier (1962) and Fischer (1970), and the pressure balancing technique, which has been proposed by Mullin and coworkers (1972). The principal problem is that of devising a pulling mechanism which prevents the volatile group V elements from being lost or from condensing of the on the walls of the system. Syringe pullers use a pull rod, generally ceramic, which is a close tolerance fit in a long bearing. Although such a seal is not perfect the loss of volatile elements can be minimized. The magnetic puller is a tour de force in which the whole ceramic pulling system contained in the pulling chamber is

Figure 2-4. Vertical pulling apparatus for low pressure liquid encapsulation. The silica outer vessel N with viewing port J is held between end plates 0 and P. The induction heating coils couple into the graphite surround F mounted on Q.The seed A is fixed in the chuck on the pull rod K which rotates and moves through the bearing and seal L. The crystal C grows from the seed through a necking process at B and on withdrawal pulls out a layer of B,O, over its surface. Loss of the volatile group V component from the seed, crystal and melt is prevented if PG > pd.

2 ComDound Semiconductor Processing

kept above the condensation temperature of the volatile component. Translation and rotation are achieved by magnetic coupling to suitably sited and protected magnetic material on the pull rod. Neither syringe pullers nor magnetic pullers have achieved any significant following. They are expensive, technically difficult and not entirely satisfactory technologies. An alternative technology proposed and demonstrated by the author has been referred to as the pressure balancing technology (Mullin et al., 1972). This method overcomes loss of the volatile component up the pull rod by arranging for a liquid seal at the top of the bearing housing through which the pull rod is pulled. The inside of the BN bearing has a screw thread so that rotation of the BN pull rod causes the B 2 0 3 liquid sealant to be "wound up" the shaft and kept in the upper reservoir. The inert gas pressure in the system is kept above the dissociation pressure and through the use of a u-tube gauge internal and external pressures can be kept the same. Of course the whole of the apparatus has to be kept above the condensation temperature of the volatile components. The pressure balancing technology works surprisingly well but was not developed and exploited because of the success of liquid encapsulation technology, which has transformed the whole of 111-V pulling technology for the arsenides and phosphides.

2.5.4 Liquid Encapsulated Czochralski (LEC) Pulling Liquid encapsulation often referred to as the liquid encapsulation Czochralski (LEC) technique is illustrated in Fig. 2-4. The liquid encapsulation technique (Mullin et al.. 1965, 1968; Mullin, 1989) avoids the need for hot walls and permits the use of

conventional pull rods. It is elegantly simple. It involves the use of an inert layer of transparent liquid, usually B,O, , which floats on the surface of the melt, acts as a liquid seal and prevents the loss of the dissociating volatile component provided the pressure of external gas P, is greater than that of the dissociation vapor pressure P, of the volatile component. The encapsulant should possess additional properties. It should be immiscible with the melt and be unreactive towards it. But, most importantly, the encapsulant should wet the crystal and the crucible. Further, its viscosity and the temperature dependence of its viscosity should be such as to allow it to be drawn up with an encase the emerging crystal as a thin film of encapsulant. The latter property is desirable in order to prevent the decomposition of the hot crystal throughout the course of the crystal growing process after it has pulled clear from the layer of the encapsulant. Although many glass-like encapsulants have been tried only B 2 0 3and related mixtures fulfill sufficiently well these characteristics.

2.5.4.1 The Low Pressure LEC Technique For compounds that have dissociation pressures not in excess of about two atmospheres it is possible to apply the liquid encapsulation techniques using Ge-type crystal pulling chambers. For this low pressure liquid encapsulation technology it is possible to use an outer jacket of the growth chamber made of silica such as that illustrated in Fig. 2-4. Such a system would be suitable for the growth of InAs or GaAs (Sec. 2.6.2).

2.5.4.2 The High Pressure LEC Technique Silica growth chambers are not strong enough for compounds having high dissociation pressures ( > 2 atm) and steel or

2.6 Crystal Growth of Specific Compounds

metal pressure vessels are used. Pressure vessels have been designed for working upto 200 atm. The use of such steel pressure vessels has enabled the development of a unique technology which has been applied to the crystal pulling of InP and Gap, compounds which have dissociation pressures at their melting points of -27.5 atm and -32 atm respectively. The technology effectively simplifies the growth of these compounds so that the growth process is very similar to that of Ge except that an encapsulant is used and the pulling is carried out under a high pressure of inert gas in a steel pressure vessel. The process can be viewed directly via an optical window using a video camera. An example of a research system is shown in Fig. 2-5. The technical success of the LEC high pressure technology lies in the confinement of the chemically reactive elements such as arsenic and phosphorus to the region of the melt under the liquid encapsulant and out of contact with the chamber wall, the pull rod assembly, bearings seals, etc. Indeed the pressure chamber walls and the pull rod seals need only be capable of withstanding the inert gas pressure at relatively low temperatures, thus avoiding difficult design problems. Of course, the inert gas pressure must such that P, is greater than P, in order to avoid vapor loss. The overall effect of this technology has been to revolutionize the growth of these compounds, enabling them to be grown commercially.

2.6 Crystal Growth of Specific Compounds In discussing the crystal growth of specific compounds emphasis will be given to what is considered to be the most effective technique for general application. The main considerations under discussion will

Figure 2-5. 200 atm high pressure LEC crystal puller developed at RSRE showing water cooled steel pressure vessel and two optical ports for viewing, one fitted with a video camera. Below the steel pressure vessel is a large chamber containing the weighing cell for diameter control.

relate to the problem areas of diameter control, dislocations, grain boundaries, twinning and purity. A factor which can be important in the growth of compound semiconductors is the anisotropy introduced by the presence of two dissimilar atoms in the zinc blende lattice (Sec. 2.7.1). Thus the [ l l l ] direction where the surface terminates with group V atoms [some authors confusingly use the reverse designation: see discussion in Hulme and Mullin (1962)l differs in properties and behavior from the [TTT] which terminates in group I11 atoms. The designation [111]A or [111]B, where A and B represent the group I11 and group V atoms respectively, avoids ambiguity. The anistropy al-

2 Compound Semiconductor Processing

so holds of course for all ( h k f ) versus directions. This anistropy is important for all compounds but is particularly important in the case of the growth of the In compounds and is directly relevant to the problem of twinning.

(hm)

2.6.1 InSb Both the H G and the VP techniques are used for the preparation of single crystals of InSb. The former method is attractive for obtaining a controlled shape and the highest purity compound whereas the VP technique is more versatile and offers scope for growth in specific orientations. The compound can be formed by heating the elements together since molten In will dissolve Sb. Hence the horizontal technique is not required for preparing the compound. However, the technique does offer scope for the growth of single crystals which can be zone refined in order to obtain very high purity uniform crystals. It is particularly important with InSb to avoid growth in the [ l l l ] direction since (111) facet formation gives rise to the facet effect and can cause very nonuniform crystals. The H G technique also enables single crystal zone refining in growth directions, which minimizes facet formation on the growth surface at the solid-liquid interface, such as the [211]Sb or [311]Sb orientations. The technique has been used successfully for the growth of high purity p-type single crystals for detectors but requires considerable care in control of the growth conditions in order to avoid twin formation. Crystal pulling using a Ge-type puller is a more versatile technique and is probably now used more frequently but it does suffer from the same twinning problems as already discussed. The (1ll)Sb facet is more stable, requiring a greater supercool-

ing for nucleation and growth on its surface than the (TTT)In facet. As a result, twinning tends to be more probable on the (1 1 l)Sb facet when it is present at the edge of crystals, where it is subject to liquid motion, exposure to the gas environment and greater temperature fluctations than when it is at the center of a pulled crystal. Thus growth in the [111]Sb direction is least likely to cause twinning even though there is a central (111)Sb facet whereas growth in the reverse [TTiIIn direction has the greatest likelihood of twinning since there is then the possibility of the formation of three (1 11)Sb-type edge facets. Although growth in the [l ll]Sb direction offers the greatest opportunity to avoid twinning and the preparation of completely single crystals it is not to be recommended for undoped crystals or for doped crystals with dopants which exhibit a marked facet effect since the usual capricious size behavior of the central or principal (111)Sb fact can give rise to very nonuniform crystals. Growth in the [211]Sb or [311]Sb direction is usually recommended. Twinning and trapezoidal shape problems for the crystals may ensue, but by careful control of temperature gradient and temperature stability these effects can be minimized.

2.6.2 InAs and GaAs The growth characteristics of both of these compounds are similar and both can be grown by the horizontal technique and by liquid encapsulation. However, the R&D carried out on GaAs vastly exceeds that on InAs. All the early work on these compounds involved their preparation in an H G apparatus (Sec. 2.5.1) in which As was distilled into the liquid group I11 element contained in a boat. The temperature of the liquid alloy was raised to the melting

2.6 Crystal Growth of Specific Compounds

point of the compound as the composition of the liquid approached stoichiometry. Finally the melt was progressively crystallized to form an ingot. A fairly high yield of self-seeded single crystal ingots could be obtained in this way. As an alternative a single-crystal seed at one end of the boat could be used to give controlled nucleation, but this is not a simple process and requires considerable development. Although crystals can be grown in low temperature gradients, resulting in low dislocation densities, scaling up the process to cut circular sections is not an efficient or very successful process. It is understandable then that the advantages of the VP technique using the liquid encapsulation technique has resulted in LEC becoming the industry standard for the growth of GaAs and InAs. The role of liquid encapsulation was considerably enhanced by two significant developments: in situ compounding and the production of semi-insulating (SI) GaAs without recourse to Cr doping. In situ compounding of the elements Ga and As was made possible by the introduction of steel pressure vessels. Liquid As at the melting point of GaAs 1238°C has pressure of -80 atm. Thus progressively raising the temperature of a crucible containing a charge of elemental Ga and As under a layer of B,O, in a pressure vessel containing inert gas at 100 atm to a little in excess of 1238 "C is a convenient way of of forming a GaAs melt whilst avoiding significant loss of As. This in situ compounding has eliminated the need for compounding using a horizontal apparatus, a significant simplification. An additional important development was the use of BN crucibles. This had two effects, it avoided contamination by Si, which is endemic with the use of SiO, crucibles, thus giving a convenient very

rapid processing route to the formation of very high purity GaAs charges for LEC growth. Also, and somewhat inadvertently, it provided a route to the production of SI GaAs. Swiggard and coworkers (1979) reported that GaAs prepared in BN crucibles generally had very high resistivity and furthermore the electrical properties of the product were relatively stable to the type of heat treatments needed to anneal out ion implantation damage. This was a very important result in connection with the use of GaAs for integrated circuits since SI material provided an excellent insulator on which integrated circuits could be fabricated using ion implantation. A complete explanation of the reasons for the formation of SI GaAs and for its semi-insulating character is the subject of continuing scientific debate which is beyond the scope of this article. However, the materials science of the processing of SI GaAs is important. It is evident that the SI properties are fundamentally connected with the EL 2 center, which is a complex defect involving an As antisite, that is, As on a Ga site. EL 2 is a well characterized electron trap 0.75 eV below the conduction band. In detailed studies it has been shown that the acceptor carbon combines with the EL 2 donor to control the resistivity of the GaAs. From a processing point of view a critical preparation parameter was shown to be the melt stoichiometry (Holmes et al., 1982). Thus the As atom fraction in the melt needed to be greater than 0.475 in order for the resulting crystal to be semi-insulating. This result is qualitatively consistent with the concept of an As antisite being responsible for the SI properties. The LEC technique is now a well established industrial process for the production of 2 inch and 3 inch diameter GaAs either as doped n-type material for use as sub-

2 Compound Semiconductor Processing

strates in the fabrication of devices such as light emitting diodes or as SI material for ion implantation and the fabrication of integrated circuits. However, in the last few years the VGF technique has assumed increasing importance as a means of preparing SI and doped GaAs crystals. As noted earlier the VGF technique involves the progressive crystallization of a molten charge in a vertical crucible by continuous adjustment or programming of the thermal profiles. It is a simple concept but its practical implementation is particularly demanding because of the lack of visibility and inability to follow exactly what is happening in the growth process and identify the onset of defect formation. This is a consequence of the use of nontransparent BN crucibles. Pressure vessels, often used for safety reasons, can also be a hindrance to visibility. Nevertheless, the quality of VGF crystals can be as good if not better than LEC crystals, indeed their dislocation densities are generally lower and more importantly uniformly distributed, a consequence, as with the horizontal technique, of the design resulting in low temperature gradients. The major unknown factors in both techniques are the average reproducible yields of single crystals that can be obtained. Yield is an overriding consideration in any growth process in the assessment of its commercial viability. One of the major factors which affects yield is twinning. The precise cause or causes of twinning in any growth run is difficult to identify, and whilst the general process is understood, what exactly brings about a twin misnucleation, be it an impurity, temperature fluctuation, foreign body or facet size, is rarely identifiable as a cause and effect relationship. As a result, trial and error development effort is normally expended in finding suitable twin-free growth conditions.

Twinning can be a serious problem in the VGF process not least because of the need to use [loo] seeds in order to meet industrial demand for (100) wafers. Here there is the additional problem of seedingon blind. The lack of visibility is a big handicap in VGF. Thus unlike the situation in the LEC process it is not possible to identify, for example, the causes of poor crystal quality and or twinning except by inference after growth. With LEC, twins are generally visible and crystals can often be regrown to eliminate them. Nevertheless, VGF is now a commercial process for GaAs and one must assume that sufficiently twin-free conditions can be developed in the growth process. General crystal growth experience would suggest that B,03 quality, boat material, interface shape and thermal stability would need to be carefully controlled. Indium arsenide has similar processing problems to GaAs, although here the melting point is lower and the vapor pressure at the melting point is -0.3 atm. But there is very much less commercial interest in InAs and only the horizontal growth and LEC techniques appear to be used. Twinning is possibly an even more troublesome problem with InAs than with GaAs. The problem is multiple laminar twinning. Again its origin is uncertain, although it is possible to develop twin-free growth conditions.

2.6.3 InP The application of the concept of liquid encapsulation to the growth of III-V compounds was initially reported for the growth of InAs and GaAs by Mullin and his colleagues (1965). The use of B,O, is well known metallurgically and has a long history in protecting molten metals from oxidation and vapor loss. In the case of the IV-VI semiconductors Metz et al. (1962)

2.6 Crystal Growth of Specific Compounds

used B 2 0 3in the crystal growth of volatile compounds of PbTe and PbSe. However, the most significant advance in the III-V compounds came with the application of liquid encapsulation to the concept of high pressure pulling in steel pressure vessels. Liquid encapsulation high pressure pulling was initially applied to the growth of InP and GaP (Mullin et al., 1968) and represented a breakthrough in the growth of these materials as high-quality single crystals. There is now considerable commercial interest in InP due in part to the InP-based structures used in the fabrication of very high quality lasers. It is becoming the laser material par excellence. The principal method of preparation of the raw material uses a pressurized horizontal technique involving distillation of P4 into a boat of molten In as discussed earlier. Crystal growth using the LEC technique is often carried out using a pre-pulled charge of InP. The LEC growth of InP has analogous problems to those of GaAs with respect to temperature gradients and the loss of the group V component. However, in addition, twinning of the crystals during growth is more of a problem. The effect of evaporation from the surface of the hot crystal after it has emerged from the B20, is more troublesome than it is with GaAs even though the absolute temperatures are less. The loss of P, from the crystal as it merges from the B 2 0 3 is connected, firstly, with the very high gas velocities near the crystal surface, and secondly with the temperature of the crystal surface, which is controlled by the temperature gradients. The high gas velocities are caused by Rayleigh convection driven by the high pressure, large temperature differences and relatively large dimensions of the Benard cells in the growth chamber. Convec-

tion that can occur in pressure pulling systems correlates with the magnitude of the Rayleigh number R,, which is given by (Chesswas et al., 1971)

ATg d3 P 2

(2-2) TKovo where AT is the temperature difference of the depth of volume of convecting gas (the temperature difference between surfaces driving the Benard cell), and T is an average gas temperature, d is the depth of volume of convecting gas, KO is the thermal diffusivity, v o is the kinematic viscosity and P is the gas pressure. Note that R, depends on the square of the gas pressure, the cube of d and the temperature difference between surfaces driving the convective Benard cell. It is important therefore in the pulling systems to avoid large free volumes with large temperature differences between the hot and cold surfaces. The temperature gradient effects are basically similar to those encountered in the LEC pulling of GaAs. Attempts to reduce the temperature gradients in order to reduce the dislocation density cause a slower rate of fall off in surface temperature of the crystal surface above the layer of B 2 0 3 with consequent loss of the B 2 0 3encapsulating film. The very high dissociation pressure of the InP also exacerbates the problem of P, loss. The loss of P, results in the deterioration of the surface quality of the InP involving the formation of In droplets which can move into the bulk InP under the applied temperature gradient by temperature gradient zone melting (TGZM) towards the solid-liquid interface. The need for low dislocation density is very important for device applications and there is an imperative need to reduce them well below the norm of lo4 to lo5 cm-2 generally found in undoped and lightly =

2 Compound Semiconductor Processing

doped material to lo3 or nearer IO2 cm-2 for many device applications. Attempts to reduce the temperature gradients and the dislocation desities have been reported by Hirano et al. (1992). They used a system of double heat shields or baffles in order to reduce the temperature gradients. This was done in a way that minimized P, loss presumably by minimizing gaseous convection.

2.6.4 II-VI Compounds: General The status and development of II-VI crystal growth is very different to that of the III-V compounds. Most strikingly there is no successful pulling technology and it is only in the last few years that large-area CdTe and Cd,Zn - ,Te singlecrystal material has become available. The reasons for this are partly historical and partly materials property related. A significant R&D effort was deployed on the IIVI compounds in the 1950s and 1960s, but following the lack of any significant commercial device promise the major research companies stopped work on the II-VI compounds. The enthusiasts continued, but the problems were formidable and progress was slow. In this phase of development, bulk vapor growth of the II-VI compounds was the most successful crystal growth technology. However, in the early 1980s there was a resurgence of interest in the II-VI compounds partly at least following the availability of the newer low temperature epitaxial technologies which were developed in the 1970s and 1980s for the III-V compounds. The constraints to the melt growth of the II-VI compounds are fundamentally similar to those of the III-V compounds but practically very much more difficult to overcome. All the II-VI compounds exert significant vapor pressures of their compo-

nents at the their melting points. ZnS and CdS have inaccessibly high melting points for melt growth. The more ionic nature of the compounds compared with the III-V compounds gives rise to low critical resolved shear stresses and ease of deformation of the compounds. The high point defect concentrations of the compounds near the melting points conspire with the high diffusion rates in the II-VI compounds, they are orders of magnitude greater than in the III-V compounds, to allow polygonization of dislocations and the formation of grain boundaries and especially subgrain boundaries. The latter are virtually unknown in III-V compounds. Liquid encapsulated pulling cannot be used to overcome the volatility of the compounds since B,03 is partially miscible with II-VI melts. Even if LEC could be used, the ease of deformation would probably limit the value of the technology. The emergence of II-VI epitaxial device structures stimulated new developments in the crystal growth of the II-VI compounds. One can readily identify requirements which were and still are responsible for creating the need for this work: bulk Hg,-,Cd,Te for 3-5 pm and 8-14 pm detectors, CdTe and Cdl -,Zn,Te substrates for epitaxial Hg, -,Cd,Te and ZnSe for blue light emitting diodes and lasers. 2.6.4.1 Bulk Hg

- ,Cd,Te

Research on mercury cadmium telluride (MCT) has never waned since its discovery and it is still an active topic of materials R&D. Three main bulk techniques have been developed, the vertical Bridgman technique, the American quench anneal technique, an equivalent UK technology called the cast recrystallize anneal (CRA) technique and a traveling heater technology.

2.6 Crystal Growth of Specific Compounds

The vertical Bridgman technique involves sealing the pure elements in a thickwalled (3 mm) silica tube, a requirement needed to handle the Hg pressure, which can exceed 20 atm for melts used in the preparation of Hg,.,Cd,,,Te. After melting and mixing in a rocking furnace, the charge is frozen as an ingot and transferred to a VB apparatus where it is again completely melted and then slowly crystallized by withdrawal from the furnace. The resulting ingot has a composition gradient which varies from an x of 0.3 to less than -0.18 depending on the start composition. Much effort has been devoted on devising controlled mixing schemes to maximize the yield of x=0.2 and 0.3 detector material. These attempts have included work on the accelerated crucible rotation technique (ACRT), which involves increasing the rotation of the crucible in one direction from rest, slowing it down, and then repeating the operation. This can then be carried out in the opposite direction, but this is not essential. A great deal of study has been carried out by Capper and his colleagues (1994) at Mullard/Philips Research Laboratories (now GEC-Marconi) on this technology with very good results. The melt mixing conditions have attracted much study and whilst a great deal has been discovered the interactions between the complex transient Couette flow the spiral shearing and the Eckman flows across the solid-liquid interface are still not understood. The need to prepare very uniform MCT has resulted in the development of a unique technology, that of quench anneal (QA) or CRA. The method involves rapidly casting a melt of the appropriate MCT compositions in order to produce a macro uniform solid. On a micro scale, however, the material is extremely nonuniform a consequence of the dendritic growth as N

well as the effects of constitutional supercooling. Advantage is then taken of the very high interdiffusion in these compounds and the material is recrystallized in a temperature gradient. This gives uniform MCT but also a high acceptor concentration, which equates to the high Hg vacancy concentration. This is eliminated by a final Hg anneal at low temperature. This is an astonishingly well developed technology, a consequence of support from a military infrared detector programme. The third bulk technology is the travelling heater method (Triboulet, 1994), which was described in connection with the purification and preparation of MCT in Sec. 2.3.3.4. This technique is also used for the growth of Zn,-,Cd,Te an alternative to MCT as a detector material. Material with very uniform x can be grown but the extent of material development is confidential and not available. Although bulk grown MCT is still used it is rapidly being superseded by liquid phase epitaxy (LPE) and by metal organic vapor phase epitaxy (MOVPE) and the less developed molecular beam epitaxy (MBE). These epitaxial technologies require highquality substrates which is the main reason for the extensive development of CdTe and Cd - ,Zn,Te.

2.6.4.2 CdTe and Cd, -,Zn,Te The most developed technology for these materials is the vertical Bridgman technique, where 2 inch and 3 inch diameter crystals, principally of Cd, -,Zn,Te, for use as substrates for MCTZ are under development. Again the technique involves the withdrawal of a molten charge of material from a furnace. The growth of both CdTe (Rudolph, 1995) and Cd,-,Zn,Te (Sen and Stannard, 1995) have recently been reviewed. The major

2 Compound Semiconductor Processing

problems affecting the production of highquality single crystals are the avoidance of twins and both large and small angle boundaries. Tellurium precipitates cannot be avoided during growth but can be eliminated by a post-growth anneal in Cd vapor. The unequivocal correlation of the causes of the defects with the growth conditions is difficult to establish but it would appear that the main requirements for good growth are a flat to convex growth surface (relative to the solid) together with low axial and radial temperature gradients. The use of too low an axial temperature gradient can cause a condition of constitutional supercooling and hence a compromise value needs to be selected. Naturally a stoichiometric melt is needed which strictly requires a controlled separate Cd vapor source. However, since the effective distribution coefficient of Zn is 1.3 its segregation can also result in a condition of constitutional supercooling and hence it is important to grow ingots slowly to give time for rejected solute to diffuse into the melt and not build up as a solute boundary layer. The horizontal growth technique has also been developed over the last few years to grow high quality CdTe and Cd, -.Zn,Te. Crystals allowing the selection of single crystal sections greater than 2.5 inch in dimension have been grown from 4 kg ingots (Liao et al., 1992). Larger systems are under development. Seeds are mounted in a raised section at the top of the boat. Seeded growth propagates freely across the top of the surface of the liquid, resulting in the formation of large singlecrystal areas. There is very little detailed information available on the reasons for the good growth other than it is important to avoid propagation from the multiple grains which can be initiated by growth

nucleated on the bottom silica surface of the boat.

2.6.4.3 ZnSe The very high melting point of ZnSe, 1526 "C, makes the vertical Bridgman technique very difficult and most studies have been carried out using vertical gradient freeze technology. But neither of these melt growth techniques give really good quality crystals. Significantly, using a bulk seeded physical vapor transport technique better ZnSe crystals have been obtained by Cantwell et al. (1992). This method is now used by Eagle Picher as a production method. The technique uses 2 inch diameter seeds at either end of a quartz tube. A charge is situated half way between the seeds and is transported to the seeds using an appropriate temperature gradient. The growth of up to 2 inches of crystal has been reported. Very good quality ZnSe having etch pit densities of - 5 x lo4 cm-2 has been grown. It is evident that growth at temperatures below the melting point are very important for ZnSe. Indeed bulk vapor growth could be the technology of the future for the II-VI compounds.

2.6.4.4 ZnS and CdS The very high melting points of ZnS and CdS mean that melt growth is not possible. As a consequence considerable effort has been devoted to the development of vapor growth techniques for these compounds. A variety of physical vapor transport arrangements have been attempted. Probably the most successful has been the PiperPolich technique (Piper and Polich, 1961). This is illustrated in Fig. 2-6a. It uses a tube having a coned tip. The charge can first be transported by an appropriate temperature gradient away from the tip. Growth is achieved by physically moving

2.7 Fundamental Aspects of Crystal Growth

Figure 2-6. Schematic illustrations of vapor growth techniques. (a) Piper-Polich technique showing the growth crucible A supported by an outer jacket B mounted inside the furnace F. Movement of A relative to the heater (thermal profile) causes vapor transport of the charge G and its crystallization in the cone of the crucible. (b) Controlled vapor pressure method; growth crucible A has a long side tube D containing the elemental source E which controls the vapor pressure of the more volatile component; note seed crystal C and charge G and thermal profile.

the tube so that the tip sees a progressively lower temperature than the charge. A single crystal can be grown from the tip. An important factor in the growth of most 11-VI and other compounds is the necessity to maintain similar vapor pressures of both components during growth. This requirement can be fulfilled by using a separate source of the more volatile component. Its vapor pressure can then be independently controlled and adjusted to that of the other component. The concept is illustrated in Fig. 2-6 b. A major problem with this and all the other earlier vapor growth technologies is that the crystal grows against the silica tube, often sticking to it. On cooling, differential contraction between the crystal and the tube causes strain and stress, resulting in the introduction of dislocations. Attempts have been made to develop freegrowing systems for CdTe and other 11-VI

compounds in which the crystal grows out of contact with the tube but it is not an easy technology and very carefully designed thermal systems are required.

2.7 Fundamental Aspects of Crystal Growth The purpose of this section is to provide a brief insight into the origin and mechanism of those dominant phenomena which are of practical importance in the processing of compound semiconductors and which can affect crystal quality and perfection. Only the significant aspects of structure, vapor pressure, temperature distribution, diameter control, facet effect, anisotropic segregation, twinning, solute distribution, constitutional supercooling, dislocations and grain boundaries will be considered.

2 Comoound Semiconductor Processing

2.7.1 Structure Germanium and Si have a simple diamond cubic structure, which is centrosymmetric, and as a consequence there are no significant growth anisotropies. However, in the case of the compounds the different atoms have different electron affinities and as a result on finds a polarization of properties. In the case of the 111-V and 11-VI compounds the crystal is either zinc blende or wurtzite. This conveys a polar nature to the structure, and as result for the zinc blende, for example, growth in the [hkl] direction is different to growth in the [hkl] direction. The crystal structure shown in Fig. 2-7 highlights this difference. The bond directions are (1 11) or (TIT) where the (TTT) direction terminates in a singly bonded group I11 atom and the opposite (1 11) terminates in a triply bonded group V atom. The (111) planes therefore have different polarities from the {TTT} planes and hence different stabilities. Thus each will require a different supercooling in order to initiate nucleation and growth. One of the most significant phenomena associated with structure is the development of (111) or {?Ti) type facets on growth surfaces. These can give rise to the facet effect and correlate with twin formation (see Sec. 2.7.5).

2.7.2 Temperature Distribution, Crystal Shape and Diameter Control One of the more difficult problems in growing crystals from the melt is the problem of arranging for the most suitable temperature distribution and temperature gradients in the growth chamber. Thermal modeling should ultimately provide a quantitative scientific background to the process but in practice it is still an operation requiring considerable skill and know-how.

Modeling horizontal growth is of course very much simpler than modeling vertical pulling. From the practical viewpoint it is important to appreciate that the relatively low temperature gradients normally used in the growth of compounds means that very small practical changes in the growth chamber, such as a small movement of a heat shield can often have a dramatic effect on crystal growth. It also is evident that many thermal models do not take full account of practical thermal arrangements. A major problem in HG and in VGF is the control of interface shape. It is generally recognised that the growth surface should be flat or slightly convex. Concave growth surfaces frequently result in crystal growth defects such as grain boundaries or trapped-in solute. Unfortunately, many heater designs involving a simple extra heater zone used to form a liquid zone are naturally prone to form concave growth surfaces. The use of modeling and the introduction of better thermal design concepts is beginning to overcome this problem. Vertical pulling apparatus, in contrast, is very difficult to model thermally, especially in the critical region of the solid-liquid interface. Unlike HG, where shape is controlled by the shape of the boat and is not an experimental problem, in VP shape or diameter control is a major problem, and one on which a vast amount of R&D effort is expended. The critical parameters controlling interface shape are the thermal heat balance at the solid-liquid interface and the surface tension forces operating between the solid, liquid and gaseous surfaces. The simplest approximation of the heat balance at the solid-liquid interface is given by

2.7 Fundamental Aspects of Crystal Growth

Figure 2-7. Zinc blende lattice showing (1 11) and (TTT) bond directions and the nature of the lattice polarity.

2 Compound Semiconductor Processing

where G is the temperature gradient, cr is the thermal conductivity, e, is the density of the crystal and H, is the latent heat of fusion. The temperature gradient G,(Z=S, L) refers to the gradient normal to the solid-liquid interface. In crystal pulling a net loss or gain of heat normal to the crystal axis at the solidliquid interface will cause the growth surface to become convex or concave. The crystal diameter, however, is determined by the shape of the meniscus above the melt. Figure 2-8 shows the steady-state position of the crystal being pulled from the melt and the shape of the meniscus. To a first approximation a meniscus which increases in diameter from the crystal causes the growing solid to increase in diameter. A meniscus which decreases in diameter or waists in from the crystal causes a growing crystal to decrease in diameter. However, this model is only an approximation since shape is also controlled by surface tension forces. Crystals appear to fall into two categories depending on whether their melts completely wet their solids or not. Melts of diamond cubic or zinc blende do not completely wet their own solids i.e.,

Figure 2-8. Diagrammatic illustration of the meniscus contact between a melt and its crystal at an angle 0,(0: for a crystal growing at constant diameter) to the vertical where the edge of the crystal is at an angle 0, and at a height h above the melt surface.

< 4sL+ 4 L G , where 4rJ refers to the interfacial free energies of the respective pairs of the three phases solid, liquid and gas. Thus under equilibrium conditions where the crystal is growing as a right cylinder the meniscus will contact the solid at a specific angle 0, , but at a general angle 0 when growing in or out (see Fig. 2-8). Thus if @<@, the meniscus tends to waist in and the crystal diameter reduces, whereas if @>@, the crystal will grow out. It is important to note that 0, is not zero but has a positive value for semiconductors, being 11" for Si and 13" for Ge. Thus the actual pull of crystallizing atoms when the liquid meets the solid at a positive angle 0, gives rise to a right cylinder. Device technology - certainly that related to intergrated circuits - requires wafers having a tight specification on diameter, hence there is a need for diameter control in crystal pulling in order to grow constant-diameter crystals. Since the seeding process uses small-diameter single crystals for use as seeds, the pulling system needs to be able to be programmed to achieve a carefully controlled variation in crystal diameter both at the beginning and end of growth. A number of technologies (Hurle, 1993) have been proposed to monitor and control crystal diameter but the most versatile technique (Hurle, 1977) involves continuously monitoring the weight of the crystal (in practice the crystal plus pull rod), or the weight of the melt (in practice the melt plus crucible) and from a knowledge of the pull rate or, strictly, normal growth rate one can monitor continuously the crystal diameter. Diameter control involves either comparing the weight (weight mode) or the rate of weight change (differential weight mode) to the desired weight or desired rate of weight change and using the difference $SG

2.7 Fundamental Aspects of Crystal Growth

or error signal in order to control and vary the power to the melt. An example of a commercially produced weighing cell attached to a RSRE research crystal puller is shown in Fig. 2-5. The weight mode has the advantage of the ability to correct errors generated in the previous stage of growth. The signal-to-noise ratio is good and the system can be used down to low growth rates, but corrected errors can give rise to a damped oscillation in the shape which propagates down the crystal. The differential weight mode seeks to keep the diameter at its present value, ignoring previous history. The signal-tonoise is less good because of the signal differentiation. This mode tends to be a more stable servoloop, which is less sensitive to the thermal lags in the system. One of the problems of growing 111-V compounds using either of the weighing methods is that the immediate response of the error signal to a requested change in diameter is opposite to the intended change. That is, a request for an increase in diameter gives an error signal that causes a decrease in diameter. This so-called weighing anomaly arises from two effects. Firstly, 111-V compounds expand on freezing and, secondly the apparent weight of the crystal contains contributions arising from surface tension forces. A practical solution has been found in that the predicted anomalous error signal is subtracted from the total error signal to give a corrected error signal. This technology has enabled the controlled diameter growth of GaAs, InP, Gap, Ge, Si and many other crystals.

2.7.3 Solute Distribution Dopants and impurities are the main solutes of interest in crystal growth studies of Si and Ge. In the case of the compounds, however, there is an additional source of

interest and study, which is the solute effect of excess of one of the components. Such an excess is a very common problem in growth of compounds and readily leads to conditions of constitutional supercooling and heavily defected growth. Solute distribution during crystallization can be conveniently described in terms of distribution coefficients as illustrated in Fig. 2-9. As a result of crystallization, since the solute is less soluble in the solid in the example chosen, rejected solute increases in concentration at the solid-liquid interface and assumes a steady-state concentration as a result of diffusion and convective mixing away from the interface. It is convenient to define in this situation an interface distribution coefficient k* (k* = CJC,) and an effective distribution

SOLUTE

CONCENTRATION SOLID

ICs SUPERCOOL1NG

SI L INTERFACE

DISTANCE

Figure 2-9. (a) Solute (k, < 1) distribution during crystal growth showing interface and bulk concentrations C, and C, and the “mathematical” boundary layer 6. b) Liquidus distribution corresponding to the solute distribution above showing three different real temperature distributions P,, the stable situation, P,, the critical situation and P,, the unstable situation due to the zone of constitutional supercooling.

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2 Compound Semiconductor Processing

coefficient kerf(k,,, = C,/C,). The latter is the parameter measured experimentally since both the concentration in the bulk melt and the crystal are accessible to measurement. However, k* is not immediately accessible; it is simply the equilibrium distribution coefficient k , modulated by the growth process. If incorporation were an equilibrium process, for example involving growth under ideally slow conditions, then k* would equal k , . In practice, k* is often a function of orientation, growth rate and solute concentration. Most of our knowledge of transport in the melt and its effects, particularly on crystallization, have been obtained on pulled crystals, where the effects of stirring can be modeled. The relationship between k*, k e f , and the stirring conditions was derived by Burton, Prim and Slichter (BPS) (1953) in a classic paper in which they introduced a parameter 6, which was related to but was not the diffusion layer thickness. The mathematical convenience of 6 is that it can be used to model the height of the boundary layer at the growth surface under different stirring conditions. In the BPS model the relationship between kerf and k* is given by keff

k* [k* + (1 - k*)e-”]

(2-4)

where A = vG/D and 6 = 1.6D’I3 vAl6 u -l i 2 , where t’ is the growth velocity, D is the diffusion coefficient of the solute in the liquid, v , is the kinematic viscosity and u is the angular rotation rate. The model makes use of an earlier analysis by Cochran (1 934), who analyzed the flow velocity normal to a disc rotating in a semiinfinite fluid. From Eq. (2-4) the effect of growth rate and rotation rate on the incorporation of impurities and dopants can be predicted. Under good stirring conditions 6 -+ 0,

and hence kerftends to the value of k*, but where stirring conditions are poor 6 + 00 and kerf tends to 1. The model has been used in predicting the onset of constitutional supercooling in the growth of heavily doped melts (Hurle, 1961; Bardsley et al., 1962), but here its significance in the growth of compounds growing under nonstoichiometric conditions will be considered. 2.7.4 Constitutional Supercooling

Consider the segregation situation illustrated in Fig. 2-9. In (a) the rejected solute forms a boundary layer where the concentration of solute rejected decreases with distance away from the interface. This concentration distribution is represented in (b) by the liquidus temperature, or freezing temperature distribution. Superimposed on this is the actual physical temperature distribution. If the slope PI is greater than the slope of the liquidus distribution at the solid-liquid interface, then the temperature of the melt will always be greater than the liquidus temperatures in the melt ahead of the interface, giving a stable situation. However, if the actual temperature distribution is, as shown by P,, less than the slope of the liquidus at the interface then in the shaded region there will exist as shown in the diagram a region of the melt where the actual temperature is less than the liquidus temperatures, resulting in an unstable situation. The melt will be supercooled. Under these conditions a perturbation on the growth surface will experience greater supercooling, resulting in accelerating growth into the bulk melt. The critical condition for the onset of supercooling was taken by Hurle (1961) to be the condition when the gradient of constitutional supercooling became equal to or greater than zero. The gradient of con-

2.7 Fundamental Aspects of Crystal Growth

stitutional supercooling was defined as the difference between the gradient of the liquidus and the actual temperature gradient at the interface. Using the BPS model the gradient of constitutional supercooling (dS/dx),,, is given by

umC,(1 - k*) - GL D [ k * + (1 - k*)e-A]

(2-5)

where m is the gradient of the liquidus, CL the solute concentration and the other parameters are as defined in Eq. (2-4). Putting (dS/dx),,, = 0 one can obtain the critical growth velocity for the onset of constitutional supercooling. uCritgiven by ucrit

D G, [k* + (1 - / ~ * ) e - ~ ] mCL(l- k*)

(2-6)

Thus the critical (maximum) growth velocity for good stirring conditions (6 -,0) is DG,/(mCL) and for bad conditions (6 -,co),[DGJm C,)] x k*. If from Eq. (2-3) asGsis very much larger than UQJH~, we can substitute (as/oL) G, for GL. In the case of GaAs, if G, is 50 "Ccm - and as/ 0,=0.54, and m=3"C (at.%)-', C,=l at.% and D=10-4cm2 s - l for ideally good stirring conditions, the critical growth cm velocity uCritwould be equal to 9 x s - l (3.2 cm h-'). Under poor stirring conditions uCritis modulated by a factor of k*. Thus constitutional supercooling is very sensitive to small distribution coefficients. This is a very important aspect of the growth of compounds where it is often very difficult to control the stoichiometry of the melt of dissociable compounds. In the case of the arsenides and phosphides of the 111-V compounds, the excess component in nonstoichiometric melts behaves as a solute with negligible solubility in the The solid, that is with a k* of significance therefore is that it is extremely difficult to avoid constitutional supercool-

101

ing in the growth of compounds unless the melts are very close to stoichiometry. In the case of horizontal growth one has the additional hazard of low temperature gradients. The effect of growth under conditions of constitutional supercooling (Bardsley et al., 1962; Hurle et al. 1961) is illustrated in Fig. 2-10. A planar growth surface initially breaks up into a sinusoidal or rumpled surface. Where the solid-liquid interface becomes parallel to { l l l} planes the growth surface develops a ridge or roof-type structure delineated by (111) facets. The regions between the rooftops are valleys where the rejected solute gets trapped. The regions of the crystals grown behind the rooftops between adjacent valleys are the so-called cells; the growth gives rise to a cellular structure. The cells grow more or less independently of one another. Examples of cellular structure on the surface of a crystal can be seen in Fig. 2-11. The effect of progressive constitutional supercooling is to cause the crystal to de-

Figure 2-10. Effect of constitutional supercooling on a planar growth front 1. Rejected solute causes the growth surface to rumple 2 and then develop a faceted structure 3. The full cellular structure traps in solute as illustrated.

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slowly with good stirring and with as large a temperature gradient at the interface as possible.

2.7.5 Facet Effect, Anisotropic Segregation and Twinning

Figure 2-11. Crystal end showing the development of cell structure which is evident from the faceted grooves on its surface.

velop polycrystallinity. The trapping of excess solute initially represents a separate liquid phase for the case of a group I11 element. The trapped droplets move under the influence of the temperature gradient (TGZM) towards the solid-liquid interface. The droplets ultimately get frozen in since the crystal growth rate is greater than the diffusion-controlled transport rate of the droplets. The resulting two-phase regions create strain and dislocations and marked nonuniformity. Additionally the facets on the ridge structure exhibit the facet effect giving rise to additional nonuniform dopant and impurity incorporation. Great care is therefore required in the melt growth of compound semiconductors if constitutional supercooling effects are to be avoided. The basic need is to maintain stoichiometric melts and to grow crystals

Facets or atomically flat planes, which are generally of low index, so-called singular planes, are a feature of compound semiconductor growth; they can adversely affect both the yield and quality of crystal growth. The most troublesome facets are of the (111) or (TTT) type. Four of each type can occur over a closed volume. Facets develop when the (111) planes become tangential to the solid-liquid interface as illustrated in Fig. 2-12. The majority of the crystal surface, which comprises growth steps which are easy sites for nucleation, requires negligible supercooling for growth and thus follows the melt isotherm. However, where the isotherm becomes tangential to the (111) the facet plane truncates the growth surface, there are no growth steps on the (1 11) plane, and there

‘(111)

FACET

Figure 2-12. Diagrammatic representation of the formation of a (1 11) facet on a growing crystal showing the equilibrium melting point isotherm T,. The TM-AT isotherm illustrates the potential for the development of a maximum supercooling AT

2.7 Fundamental Aspects of Crystal Growth

is a difficulty of nucleation. The facet lags in growth behind the rest of the surface defined by the melt isotherm. The facet grows in size sufficiently in order to develop sufficient supercooling AT in the melt above its surface to initiate nucleation and subsequent growth. Hulme and Mullin (1959) discovered that many impurities are preferentially adsorbed on [111] planes. The effect known as the facet effect is dramatically large for the case of Te in InSb, where the distribution coefficient for growth on a { 11l} type facet was 4 whereas just off a { 11l} type facet it was -0.5, giving a facet ratio k[on (111) facet)]/k[off (lll)facet] of -8, which can result in very marked dopant nonuniformities. The diagrams at the bottom of each montage in Fig. 2-13 illustrate the relationship of the { 11l} planes for growth in the [TTTIIn and [loo] growth directions. For growth in the [iii]In direction there will be three (111) directions of the opposite type at 70.5" to the [TTIIIn direction. For the [loo] direction there will be two (iTT)In and two (111)Sb directions at 55" to the [loo]. Differences in facet behavior can be seen in Fig. 2-13, which is a montage of autoradiographs of slices cut from InSb crystals that were grown using radioactive lZ7Teas a dopant. The brighter regions are lz7Terich. The diagrams at the bottom of Fig. 2-13 illustrate the "spraying out" effect of the lz7Teradiation onto the autoradiography film. Slices were taken from different positions down crystals grown in the [TTT] and [loo] directions. The [TTi]In crystal shows the central or principal facet together with the three edge facets which are of the { 111}Sb type. The disappearance of one of the (111)Sb facets in the last slice is indicative of a recently formed twin. The [loo] crystal shows two opposite {TTT}In N

103

facets and two opposite (111)Sb facets, the differences in size clearly indicating that the (111)Sb facets are larger than the {ITT}In and require more supercooling for growth. Note the evidence of a small (100) principal facet. Figure 2-14 is a longitudinal section of a '27Te-doped (1 11) crystal which shows the coring effect of the (111) principal facet and also the rotational striations which have a periodicity of one per revolution. The autoradiographs clearly indicate that facet development is an important and critical phenomenon in crystal growth and can bring about very significant dopant and impurity nonuniformities. Twinning can be a particular problem in the growth of 111-V compounds and can strongly affect yield in any growth process. The growth twins occur on { 11l} planes, which is the twin composition plane and can be described as a rotation of 60" about the (1 11) direction. First nearest neighbor atoms are not affected by the rotation, only second nearest neighbors. The interaction energy associated with the marked increase in distance of the second nearest neighbors is thus quite small, a factor which enhances the twinning probability. The exact mechanism of twinning is not understood as a cause and effect phenomenon. Thermodynamic conditions for twinning on edge facets have been proposed by Hurle (1995) in a recent model. Differences in material behavior appear to be predicted, but to what extent kinetic effects are involved is still an open question. Thus anything that could allow an atom to go down on a (111) surface misoriented in rotation by 60" could be implicated, Impurity atoms, temperature fluctuations and stoichiometry have all been invoked but unequivocal proof as opposed to strong evidence, e.g. stoichiometry, has not been established.

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2 Compound Semiconductor Processing

Figure 2-13. Montage of autoradiographs of slices cut from (a) [ l l l ] In and (b) [loo] InSb crystals that had been grown from a '"Te-doped melt. The bright regions of Te-rich growth illustrate the development of facets: (a) the central or principal (TTT) In facet and the large edge (1 11) Sb facets - the disappearance of one facet effect in the last slice shows the momentary effect of twinning; (b) note the development of the opposite (111) Sb edge facets and the smaller (11 1) In facets as well as evidence of a (100) facet. The diagram at the bottom of each montage illustrates the crystallographic directions and the "spraying out" effect of the '"Te radiation into the autoradiographic film.

Twinning continues to be one of the more frustrating and annoying yield-limiting phenomena in crystal growth. Facet formation appears to be a necessary but not unique requirement for twinning. One correlation that is associated with twinning is that the avoidance of facet forma-

tion can reduce or eliminate twinning, However, any surface which is tangenital to a { 111) is prone to develop a facet. Under equivalent growth conditions the lower the temperature gradients, the bigger the facet, since a fixed supercooling is required for growth on a facet. Since low tempera-

2.7 Fundamental Aspects of Crystal Growth

105

Figure 2-14. Facet-effect nonuniformities illustrated with an autoradiograph of a longitudinal cross-section of an InSb crystal grown from a '"Te-doped melt. The principal (111) facet causes very marked nonuniformity. Note the oneper-revolution striations.

ture gradients are a basic requirement to minimize dislocation formation, it is often difficult to avoid facet formation and twinning in crystal pulling.

2.7.6 Dislocations and Grain Boundaries Dislocations and grain boundaries are a major impediment to the quality of 111-V (Jordan et al., 1980) and 11-VI compounds (Williams and Vere, 1987) grown from the melt. In the case of 111-V compounds and possibly in the case of the 11-VI compounds one of the main causes of dislocation formation during growth or under post-growth conditions are adverse temperature distributions that give rise to strain and resulting stress. Vertical pulling provides a classic example of this phenomenon. Steep temperature gradients can result in the inner region of the crystal being at a different temperature to the outer. This can give rise to a hoop stress which acts on the inclined (111) planes to produce slip and dislocation formation. Considerable effort has been

devoted to theoretically analyzing (Jordan et al., 1980; Volkl and Muller, 1989) this problem and to practically analyzing means of avoiding or minimizing the problem. Most research has been carried out on the LEC growth of GaAs although other useful information has been obtained from the growth of other 111-V compounds such as InSb, InP and Gap. There is now general agreement that steep temperature gradients which are conductive to good diameter control and pulling conditions are detrimental in LEC growth and lead to relatively high dislocation densities, around 5 x IO4 cm-' for GaAs and InP in the pulled crystals. These densities can be reduced typically by a factor of ten or more by using reduced temperature gradients but these lead to poor diameter control loss of B,O, from the surface of the pulled crystal with consequent deterioration in crystal quality. One of the critical regions requiring good thermal control is at the solid-liquid interface itself and the region around the surface of the B,O,. Thus Jordan and

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2 Compound Semiconductor Processing

coworkers (1980) have shown that the heat loss from the crystal to the B , 0 3 is 50 times as great as the heat loss from the crystal to the ambient gas. In effect the gas acts as a thermal insulator in comparison to the B , 0 3 . This situation favors hoop stresses. It also leads to considerable difficulty in crystal diameter control, thus the well-known phenomenon of the rapid decrease in crystal diameter as it emerges from the surface of the B,O, due to the reduction in temperature gradient due to reduced thermal loss from the top surface of the crystal. Jacob (1982) has advocated the growth of GaAs completely submerged under B,03 but the technique does not appear to have a large following. An alternative way of reducing dislocation densities is to harden the lattice by doping (Jacob et al., 1983). Dopants make dislocation motion difficult either by a pinning effect or by simply reducing dislocation velocities. However, rather high doping densities are required, typically above IOi8 atoms/cm3 and the technique has only very limited scope for heavily doped material for special applications. The current state of development is one where LEC is a commercially viable technique with versatile doping and growth orientation abilities, but where the ultimate low dislocation density, say IO3 cm-2 is not readily achievable. In contrast, VGF can achieve these low dislocation densities but it is not a versatile technique and is more suited to dedicated product applications. The melt growth of 11-VI compounds, unlike that of the 111-V compounds, gives rise to the formation of grain boundaries. The reason for the formation of grain boundaries is probably associated with the more ionic character of the 11-VI lattice and the considerably enhanced diffusion in 11-VI compounds compared with 111-V compounds.

The grain boundaries may be loosely classified as small angle, around IO-’ degree, and large angle, around a degree. Small-angle boundaries are very difficult to remove and indeed are quite stable. Large-angle boundaries can usually be seen visually by lightly grinding a surface. The minority carrier lifetime can be severely affected by grain boundaries, hence the development of methods aimed at eliminating grain boundaries is a priority in IIVI compounds.

2.8 Wafering and Slice Preparation The conversion of a bulk crystal into a form suitable for device fabrication is a vital and crucially important stage in processing. It is not a topic that attracts much published literature (Tada et al., 1990) if only because wafer processing is commercially sensitive, since wafer quality correlates directly with saleability. Most device fabrication procedures involve some form of planar technology. The machinery used for cutting and wafering of compounds is usually the same as that developed for the Si integrated circuit market, where the requirement is for accurately dimensioned circular wafers. In the case of the compounds the diameters are currently much less than the standard 6 inch Si. Two inch GaAs and InP is now being replaced by 3 inch material as the norm. The need for circular wafers is one of the main driving forces for the development of the LEC and VGF processes. The HG technique is supported only where it can achieve characteristics not readily achievable as effectively in other techniques, such low-cost production of very low dislocation density GaAs for laser diodes.

2.9 References

As-grown crystals are not ideally circular and after growth they are normally ground into a right cylinder having the correct diameter. The cylindrical boules are then sliced into wafers. In the Si industry this process is carried out using a high speed diamond slitting wheel. The compound semiconductors are structurally much weaker than Si and early attempts at using this technology often resulted in failure and broken wafers. In the research area slow speed cutting was developed. In an attempt to overcome wheel wobble, cutting wheels were used which were clamped and mounted and driven from their periphery. The narrower diameter internal edge of the wheel was used for cutting. The wheels were stressed to create stiffness. All cutting is a highly skilled process which requires exceptionally high quality machines in which vibration is totally eliminated. The boule is mounted on an adjustable table which fits both the X-ray orientation equipment and the cutting machine. In this way precisely oriented boules are sliced often to 0.1O or less. Commercial pressures and the need to reduce cutting times have resulted in improvements and developments in high-speed saws which can now be used successfully for cutting GaAs and InP and the 111-V compounds. All cutting gives rise to surface damage, which may be c 10 pm for Si, and up to 50 pm for GaAs and even more for 11-VI compounds. This damage must be removed. It can be achieved by a lapping process, but now that surfaces can be cut sufficiently flat it is usually sufficient to chemically polish the surfaces directly removing up to three times the depth of cutting damage at least. Often up to 100300 pm is needed to remove all trace damage and prepare the highest quality polished surface for wafers. The quality of epitaxial growth is crucially dependent on

107

the quality of surface finish on wafers. It is a major concern in the purchase of such wafers. The finishing treatment for wafers involves the use of final etches for two reasons. Firstly, even a chemical polish introduces minor damage due to the loading of the specimen, and secondly, there is a need to prevent electropositive elements like Cu plating back onto the highly polished surface since such contamination could be detrimental to subsequent device structures fabricated on the wafers. The technology and know-how of these processes, however, are generally commercially confidental.

2.9 References Al-Bassam, A. A. I., Al-Juffali, A. A., Al-Dhafiri, A. M. (1994), J. Cryst. Growth 135, 476. Arthur, J. R. (1967), J. Phys. Chem. Solids 28, 2257. Bachmann, K. J., Biihler, E. (1974), J. Electrochem. SOC.121, 835. Balasubramanian, R., Wilcox, W. R. (1993), in: Proc. E-MRS Conf. (Symp. F) CdTe and Related Cd Rich Alloys, Strasbourg, June 1992. Mater. Sci. Eng. B 16, 1. Bardeen, J., Brattain, W. H. (1948), Phys. Rev. 74, 203. Bardsley, W., Boulton, J. S., Hurle, D. T. J. (1962), Solid-State Electron. 5, 395. Bourret, E. D. (1990), Am. Assoc. Cryst. Growth Newslett. 20 ( 3 ) , 8. Burton, J. A., Prim, R. C., Slichter, W. P. (1953), J. Chem. Phys. 21, 1987. Cantell, G., Harsch, W. C., Cotal, H. L., Markey, B. G., MacKeever, S. W S., Thomas, J. E. (1992), J. Appl. Phys. 7 1 , 2931. Capper, P. (1994), Prog. Cryst. Growth Charact. Mater. 28, l . Chesswas, M., co*ckayne, B., Hurle, D. T. J., Jakeman, E., Mullin, J. B. (1971), J. Cryst. Growth 11, 225. Clemens, J. E., Gault, W. A., Monberg, E. M. (1986), AT&T Tech. J. 65, 86. Cochran, W. G. (1934), Proc. Camb. Phil. SOC.30, 365. Czochralski, J. (1917), Z . Phys. Chem. (Leipzig) 92, 219. Fischer, A. G. (1970), J. Electrochem. SOC.117, 41C. Gault, W. A,, Monberg, E. M., Clemens, J. E. (1986), J. Cryst. Growth 74, 491.

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Gremmelmaier, R. (1962), “Czochralski Technique”, in: Compound Semiconductors, Vol. I : Preparation of 111- V Compounds: Willardson, R. K., Goering, H. L. (Eds.). New York: Reinhold, p. 254. Harman, T~ C. (1967), “Properties of Mercury Chalcogenides”, in: Physics and Chemistry of IIVI Compounds: Aven, M., Prener, J. S. (Eds.). Amsterdam: North-Holland, p. 767. Hicks, H. G. B., Greene, P. D. (1971), Proc. 3rd Int. Symp. on GaAs and Related Compounds, Aachen. 1970, Inst. Phys. ConJ Ser. 9. Bristol: Institute of Physics, p. 92. Hirano, R., Kanazawa, T., Nakamura, M. (1992), 4th In!. Conf. on InP and Related Materials. Newport, JYYL. Yiscataway, NJ: IEEE, p. 546. Holmes, D. E., Chen, R. T., Elliott, K. R., Kirkpatrick, C. G. (1982), Appl. Phys. Lett. 40, 46. Hukin, D. A. (1989), in: Proc. 4th In!. Photovoltaic Science and Engineering Cony. Edge Cliff, NSW, Australia: International Radio and Electrical Engineers of Australia, p. 719. Hulme, K. E (1959). J. Electron. Control 6 , 397. Hulme, K. F., Mullin, J. B. (1959), Phil. Mag. 4, 1286. Hulme, K. E, Mullin, J. B. (1962), Solid-State Electron. 5, 211. Hurle, D. T. J. (1961). Solid-State Electron. 3, 37. Hurle. D. T. J. (1977). J. Cryst. Growth 42, 473. Hurle, D. T. J. (1993), J. Cryst. Growth 128, 15. Hurle, D. T. J. (1995), J. Cryst. Growth 147, 239. Hurle, D. T. J.. Jones, 0..Mullin, J. B. (1961), SolidState Electron. 3. 317. Isshiki, M. (1992), “Bulk Growth of Widegap 11-VI Single Crystals”. in: Widegap 11- VI Compounds for Opto-Electronic Applications: Ruda, H. E. (Ed.). London: Chapman and Hall, p. 3. Jacob, G. (1982), J. Cryst. Growth 58, 455. Jacob, G., Duseaux, M., Farges, J. P., Van Den Boom, M. M., Roksnoer, P. J. (1983), J. Cryst. Growth 61, 417. Jordan, A. S., Caruso, R., Von Neida, A. R. (1980), Bell Syst. Tech. J. 59, 593. Liao, P. K., Chen, M. C., Castro, C. A. (1992), in: 10th In!. ConJ on Crystal Growth, Sun Diego, C A 1992. Oral Presentation Abstracts. Thousand Oaks, CA: American Association for Crystal Growth, p. 161. Lorenz, M. R. (1967), “Crystal Growth of 11-VI Compounds”, in: Proc. Int. ConJ on II- VI Semiconducting Compounds, Providence, RI. New York: W. A. Benjamin, p. 215. Maier, H. (1984). in: Landolt-Bornstein: Numerical Data and Functional Relationships in Science and Technology, new series, Vol. 17: Technology of Semiconductors. Berlin: Springer, p. 5. Metz, E. P. A., Miller, R. C., Mazelsky, R. (1962), J. Appl. Phys. 33, 2016. Muller, G., Jacob, H. (1984), in: Landolt-Bornstein: Numerical Data and Functional Relationships in Science and Technology, New Series, Vol. 17: Technology of Semiconductors. Berlin: Springer, p. 12.

Mullin, J. B. (1962), Segregation in InSb, in: Compound Semiconductors, Vol. 1: Preparation of III- V Compounds: Willardson, R.K., Goering, H. L. (Eds.). New York: Reinhold, p. 365. Mullin, J. €3. (1975a), “Crystal Growth from the Melt: I. General“, in: Crystal Growth and Characterization, Proc. ISSCG2 Spring School, Lake Kawaguchi, Japan, 1974: Ueda, R., Mullin, J. B. (Eds.), Amsterdam: North-Holland, p. 61. Mullin, J. B. (1975b), “Crystal Growth from the Melt: 11. Dissociable Compounds”, in: Crystal Growth and Characterization, Proc. ISSCG2 Spring School, Lake Kawaguchi, Japan, 1974: Ueda, R., Mullin, J. B. (Eds.). Amsterdam: North-Holand, p. 75. Mullin, J. B. (1989), “Melt Growth of 111-V Compounds by the Liquid Encapsulation and Horizontal Growth Techniques”, in: 111- V Semiconducting Materials and Devices: Malik, R. J. (Ed.). Amsterdam: Elsevier, Chap. 1, p. 1. Mullin, J. B., Straughan, B. W., Brickell, W. S . (1965), J. Cryst. Growth 26, 782. Mullin, J. B., Heritage, R. J., Holliday, C. H., Straughan, B. W. (1968), J. Cryst. Growth 3/4, 281. Mullin, J. B., MacEwan, W. R., Holliday, C. H., Webb, A. E. V. (1972), J. Cryst. Growth 13/14, 640. Nygren, S. E, Ringel, C. M., Verleur, H. W. (1971), J. Electrochem. SOC.118, 306. Pfann, W. G. (1966), Zone Melting, 2nd ed. New York: Wiley. Piper, W. W., Polich, S. J. (1961), J. Appl. Phys. 32, 1278. Rudolph, P. (1995), Prog. Cryst. Growth Charact. Mater., to be published. Rudolph, P., Umetsu, K., Koh, H. J., f*ckada, T. (1994), J. Cryst. Growth 143, 359. Sen, S., Stannard, J. E. (1995), Prog. Cryst. Growth Charact. Mater., to be published. Shockley, W. (1949), Bell Syst. Tech. J. 28, 435. Straws, A. J. (1971), in: Proc. In!. Symp. Cadmium Telluride, Strasbourg, June 1971: Siffert, P., Cornet, A. (Eds.). Strasbourg: Centre de Recherches Nucleaires, p. l l . Swiggard, E. M., Lee, S. H., von Batchelder, EW. (1979), Proc. 7th In!. Symp. on Gallium Arsenide and Related Compounds, St. Louis 1978. Znst. Phys. Conf: Ser. 456. Bristol: Institute of Physics, p. 125. Tada, K., Tatsumi, M., Morioka, M., Araki, T., Kawase, T. (1990), Semiconductors and Semimetals, Vol. 31, Indium Phosphide: Crystal Growth and Characterization: Willardson, R. K., Beer, A. C. (Eds.), New York: Academic, p. 175; see especially pp. 222ff. Teal, G. K. (1958), Transistor Technology, Vol. 1: Bridgers, H. E., Scaff, J. H., Shive, J. N. (Eds.),, New York: Van Nostrand, Chap. 4. Thomas, R. N., Hobgood, H. M., Ravishankar, P. S . , Braggins, T. T. (1990), J. Cryst. Growth 99, 643.

2.9 References

Thomas, R. N., Hobgood, H. M., Ravishankar, P. S., Braggins, T. T. (1993), Prog. Cryst. Growth Charact Mater. 26, 219. Triboulet, R. (1994), Prog. Cryst Growth Charact. Mater. 28, 85. Van Karman, T. (1921), 2. Angew. Math. Mech. 1, 233. Van der Boomgaard, J., Schol, K. (1957), Philips Res. Rep. 12, 127. Volkl, J., Muller, G. (1989), J. Cryst. Growth 97, 136. Welker, H. (1952), 2. Naturforsch. 7a, 744. Welker, H. (1953), Z . Naturforsch. Sa, 248. Willardson, R. K., Goering, H. L. (Eds.) (1962) Compound Semiconductors, Vol. 1: Preparation of III- V Compounds. New York: Reinhold. Williams, D. J., Vere, A. W. (1987), .L Cryst. Growth 83. 341.

General Reading Bardsley, W, Hurle, D. T. J., Mullin, J. B. (Eds.) (1979), Crystal Growth: A Tutorial Approach. Amsterdam: North-Holland. Brice, J. C. (1965), Growth of Crystals from the Melt. Amsterdam: North-Holland.

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Hurle, D. T. J. (Ed.) (1993, 1994, 1995), Handbook of Crystal Growth: Vol. 1, Fundamentals; Vol. 2, Bulk Crystal Growth; Vol. 3, Thin Films and Epitaxy. Amsterdam: Elsevier Science. Malik, R. J. (Ed.) (1989), III- VSemiconductor Materials and Davices. Amsterdam: Elsevier Science. Includes chapter on “Melt Growth of 111-V Compounds by the Liquid Encapsulation and Horizontal Growth Techniques” by J. B. Mullin, p. 1. Miller, L. S., Mullin, J. B. (Eds.) (1991), Electronic Materials: From Silicon to Organics. New York: Plenum. Pfann, W. G. (1963), Zone Melting. New York: Wiley. Thomas, R. N., Hobgood, H. M., Ravishankar,P. S., Braggins, T. T. (1993), “Meeting Device Needs Through Melt Growth of Large-Diameter Elemental and Compound Semiconductors”. Prog. Cryst. Growth Charact. Mater. 26, 219. Ueda, R., Mullin, J. B. (Eds.) (1975), Crystal Growth and Characterisation. Amsterdam: North-Holland. Willardson, R. K., Goering, H. L. (Eds.) (1962), Compound Semiconductors: Vol. 1 , Preparation of III- V Compounds. New York: Reinhold. Includes a chapter on “Segregation in InSb” by J. B. Mullin, p. 365. Proceedings of the International Conferences on Crystal Growth. 1965, Oxford: Pergamon. 1968, 1971, 1974, 1977, 1980, 1983, 1986, 1989, 1992, Amsterdam: Elsevier.

3 Epitaxial Growth Thomas E Kuech

Department of Chemical Engineering. University of Wisconsin. Madison. WI. U.S.A,

Michael A Tischler

Advanced Technology Materials. Inc., Danbury. CT. U.S.A.

List of 3.1 3.2 3.2.1 3.2.2 3.2.3 3.3 3.3.1 3.3.1.1 3.3.1.2 3.3.2 3.4 3.4.1 3.5 3.6 3.6.1 3.6.1.1 3.6.1.2 3.6.1.3 3.6.1.4 3.6.2 3.6.3 3.6.4 3.7 3.8

Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 The Epitaxial Process: General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Surface Thermodynamics and Surface Structure . . . . . . . . . . . . . . . . . . . . . . . 119 124 Surface Transport and Incorporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Growth Behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Chemical Vapor Deposition: Technology and Issues ..................... 130 132 Reactors: Mass, Fluid, and Thermal Transport . . . . . . . . . . . . . . . . . . . . . . . . Fluid Behavior and Reactor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 135 Mass and Thermal Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Gas Phase and Surface Chemistry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Liquid Phase Epitaxy (LPE) Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 LPE Growth Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Molecular Beam Epitaxy (MBE) Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Specific Epitaxial Systems: Materials and Growth Issues . . . . . . . . . . . . . . . . 152 Silicon Chemical Vapor Deposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Silicon Chemical Vapor Deposition: Surface and Reactor Considerations . 152 Silicon Chemical Vapor Deposition: Growth Chemistry . . . . . . . . . . . . . . . . 156 159 Heterojunction Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Impurity Incorporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 GaAS MBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Growth of AlGaAs by LPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 InP Metal Organic Vapor Phase Epitaxy (MOVPE) . . . . . . . . . . . . . . . . . . . 170 Acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

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3 Epitaxial Growth

List of Symbols and Abbreviations A C

cis CS d

D DO

DS E G Gform Grnigr

H J k kB

Kn 1 L

m M n N

4 P pi

Q QWap

R S

S t

T Vms

W X

Xi CI

Y %A

,SEI

surface area; aperture area concentration concentration of solute (As) in the solid local concentration of diffusing species diameter of gas molecule; thickness of epitaxial layer diffusivity; gas phase diffusion coefficient diffusion coefficient surface diffusion coefficient energy free energy free energy of formation free energy of migration enthalpy flux rate constant Boltzmann constant equilibrium constant Knudsen number distance a reactor dimension slope of liquidus curve molecular weight number density of gas Avogadro’s number weight fraction of component i pressure partial pressure of component i activation energy heat of vaporization cooling rate; gas constant height of steps entropy time temperature mean stream velocity of gas work distance mole fraction of component i rate constant rate constant pre-exponential surface tension interfacial energy between solids A and B

List of Symbols and Abbreviations

energy of solid and vapor interface thickness of diffusional boundary layer energy per unit area of terrace ledge energy per unit length energy per kink site angle fraction of available adsorption sites terrace width; mean free path of gas molecule kinematic viscosity of gas kink density 2DEG AFM APCVD BEP CVD DEZ DFB DH FET FWHM GR LPCVD LPE MBE MOMBE MOSFET MOVPE PBN PL RHEED RTP SBH SI STM TBP TEI TLK TLV TMI UHV

two-dimensional electron gas atomic force microscope or micrograph atmospheric pressure chemical vapor deposition beam equivalent pressure chemical vapor deposition diethyl zinc distributed feedback double heterostructure field effect transistor full width at half maximum growth rate low pressure chemical vapor deposition liquid phase epitaxy molecular beam epitaxy metal-organic molecular beam epitaxy metal oxide semiconductor field effect transistor metal-organic vapor phase epitaxy pyrolytic boron nitride photoluminescence reflection high energy electron diffraction rapid thermal processing Schottky barrier height semi-insulating scanning tunneling microscope tertiary butylphosphine triethyl indium terraces, ledges, kinks threshold limit value trimethyl indium ultra-high vacuum

113

114

3 Epitaxial Growth

3.1 Introduction The development of modern semiconductor devices and circuits has required the integration of a large number of different materials. The formation of these devices requires the controlled deposition and processing of several types of materials: metals, semiconductors and insulators. Metals primarily form the interconnections between different semiconductor regions, while insulators serve to electrically isolate the metal wires from the semiconductor. The deposition of SiO, and other materials may also serve to form the active region of the device structure, as in the case of the Si-based metal oxide semiconductor field effect transistor (MOSFET). Materials deposition and surface modification of the semiconductors are required in order to form the individual elements in devices and circuits. Thus, resistors, pn junctions, transistors and a wide variety of other devices are formed by an assortment of materials processes. These processes, encompassing metals, semiconductors, and insulators, are produced in thin layer form on the surface of the substrate wafer or through modification of the near surface region of the wafer. A typical cross-section of a Si device structure is shown in Fig. 3-1. Many different types of processing steps and materials modification techniques have to be applied to develop such a structure and finally pro-

duce a working device. The formation of conducting regions in the semiconductor wafer, for example, in silicon, has traditionally been performed through the invention and application of processes which can modify the near surface regions of the wafer. The carrier concentration and conductivity type are modified through the processes of ion-implantation and solidstate diffusion. Silicon dioxide is grown through the thermal oxidation of Si or it is deposited, and serves as a local insulator. Deposition techniques, such as sputtering, thermal evaporation and chemical vapor deposition, have all been used to form semiconducting, insulating and metal or metallic conductive regions on the wafer surface. These important processes are discussed in other chapters within this volume. The processing and growth or deposition techniques will determine the final device structure, and hence device characteristics, as discussed in this chapter. The device characteristics depend crucially on the chemical, physical and structural properties of these deposited or fabricated layers, as well as on the interfaces between them. The local properties of these interfaces between dissimilar materials can be complex. The presence of a high concentration of structural defects or chemical impurities at the junction between n- and p-type semiconducting regions can drastically alter the electrical properties of a pn

Figure 3-1. The cross-section of a typical Si-based electronic structure. The device consists of many regions which have a difference in electrical properties. The technology used to generate these regions is indicated in this figure.

3.1 Introduction

junction. Similarly, structural imperfections or impurities at the interface between Si and SiO, can destroy the important passivation properties of the interface as well as degrading the electrical properties of the Si-SiOz junction in a MOSFET. Lastly, the interface between a metal and a semiconductor can yield rectifying or ohmic behavior depending on the electronic structure of the two materials and the physical characteristics of their interface. A major difficulty with many of these interfaces is the stochastic nature of the defects which control the interfacial properties. The rectifying Schottky barrier formed at most metal-semiconductor interfaces can, for example, be controlled only to & 10 meV out of a typical barrier height of 800 meV. This variation in the Schottky barrier height (SBH) of 5 1-2% is due to minor differences in the interfacial structure between the two structurally different materials and the level and distribution of chemical impurities at these interfaces. The growth or deposition of polycrystalline layers on an existing single crystal substrate always leads to micro-structural variations along the interface. As the lateral device dimensions are reduced through improvements in the primary patterning technique, photolithography, these lateral property variations are averaged over smaller areas. Device characteristics and their thermal stability will thus exhibit larger variations as device dimensions shrink. In circuit applications, such variability between adjacent devices could render the circuit inoperable. The trend toward smaller lateral dimensions has been accompanied by a similar decrease in the vertical dimension of device structures. The existing processing techniques have been refined and pushed to produce smaller and thinner structures. Many of the techniques which rely on the

115

modification of the near surface region of a wafer, such as ion implantation and diffusion, are reaching their limits in producing thinner and thinner regions of controlled properties. Both thermal diffusion and ion-implantation are limited by the stochastic nature of the process itself. The impurity distribution in the near surface region of the wafer, produced by both of these processes, typically results in a Gaussian impurity depth profile reflecting the underlying random nature of atomic motion of the process. In addition, these techniques require elevated temperatures for impurity activation, as in the case of ion implantation and impurity redistribution. These thermal treatments can result in non-equilibrium concentrations of native defects which can affect subsequent processing steps and materials properties. The development of smaller, thinner and higher performance devices will require tighter constraints on the thermal and physical extremes during the fabrication process. Each generation of devices has, therefore, spurred innovation in new processing techniques. The resulting processing trends for semiconductor device fabrication are towards low thermal budget (both temperature and time) processing and deposition techniques. Low thermal budget processing offers many advantages in these applications, resulting in a smaller concentration of defects in the material as well as a reduction in the extent of impurity redistribution within the device structure. While control of impurities is important in the development of electronic devices, the physical structure, and in particular, the interfaces between materials are becoming increasingly important as device dimensions shrink. Control over the structural details of the crucial interfaces has been more difficult to achieve over a broad spectrum of processing conditions.

116

3 Epitaxial Growth

Again the trends have been to lower thermal budget processes, where interdiffusion of and reaction between materials is minimized. In this chapter, we will discuss the nature and application of a set of processing techniques collectively called epitaxial growth techniques. In particular, these techniques have been applied to the formation of thin layer semiconductor structures which comprise the active device regions. In most cases. the semiconductor will be deposited, or grown, in a crystalline form. Under special growth conditions, the growing layer can assume or replicate the physical structure of the underlying substrate. This replication of the crystalline arrangement of the substrate is known as epitaxy. Epitaxial growth leads to a structurally perfect film in many cases and is critically important in the formation of most modern device structures. There are many deposition techniques which may be used for semiconductor epitaxial growth. The choice of the specific technique is dependent on several issues. The structure of the growing film, the electrical properties and the interface between the deposited layer and the underlying materials are the principal considerations. The approach taken to control these depends on the specific device application. Amorphous films also have applications in device fabrication and can also be produced by many of the growth techniques described in this chapter. The deposited atoms in the epitaxial growth process arrange themselves on the growing surface, bonding to the underlying atoms of the substrate. The atomic arrangement of the substrate atoms determines the subsequent arrangement of atoms in the growing film, the resulting film being a direct continuation of the atomic structure of the single crystal sub-

strate. In principle, since the film is replicating the substrate, an epitaxial film could be as structurally perfect and free from defects as the substrate itself. Since the type of the deposited atoms can be varied during the deposition process, the composition of the growing film can be controlled in the growth direction, during the deposition. Many deposition techniques can now produce multi-layered epitaxial structures in which the individual layers are less than a nanometer thick and the interfaces between layers are essentially atomically abrupt. The formation of such highly perfect interfaces requires the use of low-temperature epitaxial growth processes. The most widely encountered epitaxial growth process is the formation of Si layers on an existing Si wafer or substrate. This controlled growth of a material on a substrate of the same overall chemical composition, as in, for example, the growth of Si on Si, is referred to as hom*oepitaxial growth. The hom*oepitaxial deposition of Si on the Si substrate is often used to form very thin layers of Si in which the electrical properties of the growing layer can differ substantially from these underlying layers. The controlled addition of electrically active impurities, or dopants, during epitaxial growth then allows for the formation of electrical as well as compositional interfaces. For example, a pn junction is formed by the addition of first p-type and then n-type impurities to the growing layer. This transition from p-to-n type material can often occur over only a few atomic layers. Just as the doping of the film can be altered over a few atomic layers, the composition of the film can be changed over similar dimensions. The process of growing materials of different composition, as in the alloy Si,Ge, - x on Si, is referred to as heteroepitaxial growth. The growth of Si,Ge, - x on

3.1 Introduction

117

Table 3-1. Examples of CVD reactants used in the epitaxial growth of semiconductors. Semiconductor

Reactants

Pressure regime

General term for this form of CVD

Silicon

SiCl,H,, SiC1, SiH,, Si,H,

APCVD LPCVD and UHV-CVD

Germanium

GeH,

Sic GaAs

SiH, and C,H, Ga and AsC1, (CH,),Ga and ASH,

near atmospheric CVD near atmospheric CVD and LPCVD near atmospheric CVD and LPCVD near atmospheric CVD near atmospheric CVD near atmospheric CVD

APCVD, LPCVD, and UHV-CVD

InP A1,Ga -,As

near atmospheric CVD near atmospheric CVD

APCVD VPE MOVPE, MOCVD, OMVPE, or OMCVD MOVPE, etc. MOVPE, etc.

Hg,Cdl - xTe

near atmospheric CVD

MOVPE, etc.

near atmospheric CVD

MOVPE, etc.

Si substrates allows for a change in the electronic structure of the film. Such changes in local electronic structure form the basis of many of the new electronic devices. The heteroepitaxial growth of compound semiconductors, such as GaAs/ Al,Ga, -,As and InP/In,Ga, -,As,,P, -,,, is one of the most developed heteroepitaxial growth techniques. Quantum well lasers, high performance heterojunction transistors, and multilayer photodetectors are all products based on heteroepitaxial growth. There are several primary techniques used in the formation of epitaxial layers. The choice of the specific growth technique depends strongly on the required materials and the desired material structure. Physical deposition has been used for the growth of many films. In particular, molecular beam epitaxy or MBE has been used with great success in the fabrication of very thin layer device structures. In this technique, a heated substrate is exposed to

a flux of growth nutrients, usually elemental sources, within an ultra-high vacuum (UHV) environment. Materials growth from the gas phase at higher pressures is far more common and is referred to as chemical vapor deposition, or CVD. CVD techniques utilize high-vapor-pressure compounds of the elements comprising the film. A variety of CVD techniques are summarized in Table 3-1. The volatile source compounds, such as SiH, in the growth of Si, are transported to the growth front, at which point they react, and are incorporated into the growing layer. In all cases, the deposition of the film and the formation of the epitaxial structure proceeds through a series of elementary steps or processes: i) transport of the growth nutrients to the growth front, ii) their decomposition at the growth surface, iii) surface migration of the deposited species and iv) the subsequent bonding into the growth front. The slowest of these elementary processes becomes the rate-limiting step in de-

118

3 Epitaxial Growth

surface must also be very smooth in order to allow photolithographic patterning. Surface defects will reduce the usable area of the deposited film and therefore decrease the yield of devices and circuits generated from the material. There are also defects within the film itself which must be controlled. Defects in the film, in the form of missing atoms (vacancies), rows of atoms (dislocations), or extra or missing planes of atoms (stacking faults), schematically shown Fig. 3-2, must be controlled or eliminated. These structural defects can be electrically active and interact with the electronic or optical devices formed from the epitaxial layers.

termining the growth rate of the film. This chapter will deal with these elementary processes as they apply to CVD-based epitaxial growth and how they affect the formation of the epitaxial structure in the deposited layer. There are many issues associated with CVD of thin films. Since we are limiting our scope in this chapter to epitaxial films, the structure of the deposited layer or layers will have a definite relationship to the substrate. While this term describes the overall physical nature of the film, the details of the physical structure or perfection of the epitaxial layers is also important. In order to be useful. the deposited film must also possess other properties which bear directly on their utility within the overall device formation process. The deposited film must be uniform in thickness, composition, chemical, electrical and, perhaps, optical properties. Variations in the film properties correspond to changes in the resulting device properties over the wafer and from wafer-to-wafer. In general, the

... ... ... . . .. .

...

... ... ... ,.. .... .... .... s-*-.. .. .. .. .. .. .. .. .. .. .. .. .. .. .

The growth of an epitaxial film takes place on a crystal surface. This surface could consist of the same material, as in the epitaxial growth of Si on a Si substrate,

-T

* * .

t t

3.2 The Epitaxial Process: General Features

*--y--

T-

edge or misfit dislocation

E A

C E A C

E A

_ _ A-

-~ -

C -

_ _

E A

intrinsic stacking fault

' B

- - c

L -

c -

A .~

__ --

extrinsic stacking fault

6 A

Figure 3-2. 'There are many defects which can typically form in thin film structures. ranging from missing atoms (vacancies), missing rows of atoms (dislocations) to extra or missing partial planes of atoms (stacking faults) T is the shear stress and S and P define the plane of the dislocation.

3.2 The Epitaxial Process: General Features

or on a surface of a different material, such as Al,Ga, -,As on GaAs. In all cases, the nature of the surface composition, chemistry and structure will play a major role in determining the essential features of the epitaxial growth process. The growth rate, electronic properties, and film structure are determined by the chemical and physical reactions occurring at this growth front. This section will focus on the physical nature of the growth surface and elementary processes occurring there. These processes are important for all forms of epitaxial growth: physical deposition, as in MBE, CVD and liquid phase epitaxy (LPE). The thermodynamic description of the growth surface is the starting point for this discussion. A growing surface, by definition, is not at equilibrium. The rate of materials deposition is very slow, under many growth conditions, compared to those transport and chemical reactions which must take place in order to approach and reach equilibrium. The actual growth of materials can often be assumed to be a small perturbation to the equilibrium structure and composition of the growth front. There are, of course, many occasions when these chemical and physical reactions are very slow and non-equilibrium structures appear on the surface and in the growing film. In any event, a thermodynamic description of the surface serves as a good starting place for the discussion of epitaxial growth processes.

3.2.1 Surface Thermodynamics and Surface Structure Thermodynamics is typically used to describe the relationship between bulk phases. This description, in general, does not recognize that the bulk phases have surfaces and that these surfaces can and do have properties which are different from the bulk

119

phases. The neglect of the surface in thermodynamic calculations is well justified in most cases. Most solid materials have an atomic density of about lo2’ atoms/cm3. Consider a one cubic centimeter block of metal, the number of atoms on the surface of such a cube can be estimated from this bulk atomic density to be about atoms or lo-’ of the total number. Since for typical materials this is a very small fraction, the surface can be ignored in the calculations. The deposition of a thin epitaxial film on an existing substrate, however, is quite a different case. A thin film of 0.1 pm in thickness has an areal density of about lo1’ atoms/cm2. The atoms making up the interface or top surface then comprise 1% of the total number of atoms. In many cases, this 1% of the total number of atoms could possibly be neglected in our considerations. However, in the early stages of growth all the atoms are on or near a surface. The surface energetics can then dominate the film growth over the bulk phase effects. In addition, for structures in which interfaces play a major role, such as MOSFET devices, the interface is composed of the near surface regions of two different materials. The surface regions of these devices often dominate their physical and electronic properties. The atoms in a surface layer are in a completely different environment than the atoms in the bulk of the solid. They have fewer nearest neighbors, the distribution of neighbors is anisotropic and the properties on an atomic scale are different (Le., chemical bonding, positions, and so on). Since these detailed atomistic characteristics determine the thermodynamics of the macroscopic system, it is useful to talk about the surface as a distinct phase from the bulk. Internal surfaces or interfaces can be similarly considered as a distinct phase since the composition changes repid-

120

3 Epitaxial Growth

ly over a few atomic distances. The thermodynamic properties of the system can be considered to be the sum of the bulk and surface contributions, or in the latter case, an interfacial contribution. The most familiar of the characteristic energies associated with a surface is the surface tension. Surface tension, y, is defined as the reversible work involved in the formation of a unit area of new surface at a constant temperature, volume and number of atoms (Adamson, 1990): y- -

as A + O ,

posed of the bulk contributions and the surface contribution (Adamson, 1990): G=G~+G~

(3-2)

The surface contribution GS is defined in the same terms as the bulk free energy G B

G i = H i + TSi

(3-3)

where H iand S i are the enthalpy and entropy of the particular phase and T is the temperature. The surface tension can be expressed as

(3-1)

(3-4)

where d W is the amount of work associated with the increment in area dA. In order to increase the area of the interface or surface, work must be done on the system, hence the sign of this energy term. The work done in forming a new surface is associated with the breaking of bonds, increasing or decreasing the distance between neighbors, and/or rearranging atoms. While the concept of surface tension is usually associated with a liquid, it has a similar physical definition in the case of a solid. The surface tension is used to describe both the work done in creating a new surface, such as cleaving a crystal or nucleating a new solid phase, or increasing the surface area, as in the formation of new internal surfaces or a reconstruction or rearrangement of the surface atoms. A grain boundary is an example of an internal boundary which may be formed by cold working of a material. The surface tension is related to the more familiar energies encountered in thermodynamics. The Helmholtz free energy, entropy, enthalpy and Gibbs free energy can all generally be defined in terms of the surface tension. For example, the total Gibbs free energy of a system can be com-

The other relationships of bulk thermodynamics can be used in the definition of other surface-related quantities. In particular, the surface entropy can be given as

(3-5) or (3-6) The surface energy, E', and enthalpy, H S , are often very close in value, ESrH S , allowing the surface energy to be expressed as

E ~ Z H ~ = G ~ + T S ~

(3-7)

or A.!

(3-8) This concept of surface tension and surface energy of a solid will be useful in determining the underlying causes for surface rearrangement and the nucleation and growth behavior in epitaxial growth. The surface energy is almost always positive, indicating that surfaces are not energetically favored entities. A solid is al-

121

3 . 2 The Epitaxial Process: General Features

ways reluctant to form a new surface since it costs energy. Solids at high temperatures in equilibrium with their vapor or liquid phase will form a surface shape which minimizes this energy expenditure. Solids will therefore minimize their surface energy by altering their shape. The surface energy will be a function, in a crystalline solid, of the orientation of the solid. The surface energy can be estimated by looking at the number of broken bonds which had to be created when the surface was formed. The crystallographic planes of a crystal can and do possess different numbers of bonds. The surfaces with greater number of bonds broken in the formation of the surface will generally result in the higher surface energy. Such high energy surfaces are energetically unfavorable to form and expand. A crystallite at thermodynamic equilibrium will develop well-defined crystallographic facets or planar surface features. The wellknown shape of naturally occurring crystals often reflect these thermodynamic influences. The tendency to form facets on the surfaces is not only manifested at a macroscopic scale but also at the microscopic or atomic scale. The more stable crystallographic faces will be formed at the expense of surfaces with higher free energy. For example, thermal faceting will take place in the case of the (100) surface of Ag at high temperatures. Near the melting point of Ag, the (100) crystal surface will decompose into microscopic facets with a (1 11) orientatios. Most epitaxial growth takes place on a single crystal substrate which has a well defined, overall orientation. Most wafers are oriented to a specific low-index crystallographic direction, e.g., (100) or (11l), within a certain accuracy. If a wafer has a surface which is exactly a crystallographic plane, it is referred to as a singular surface. The wafer surface can have additional

structure aside from the above mentioned faceting. The detailed surface structure is characterized by three separate but related features: terraces, kinks and ledges. Often, the wafer will be specified to have a polished (100) surface which is intentionally misoriented at an angle towards another major crystal direction, as schematically shown in Fig. 3-3. Such surfaces are often referred to as vicinal surfaces. This intentional or unintentional off-orientation of the wafer increases the structure on the wafer surface. The terraces, ledges and kinks (TLK) on a such a surface are schematically shown in Fig. 3-3. The TLK description can be used to attempt to calculate the surface energy of a crystal by separately considering the contributions to the energies associated with the particular defects which make up the surface. In this context, the surface can be thought of as being made up of singular or atomically flat surfaces (terraces), plus steps (ledges) from one terrace to another, and kinks in those steps. This view extends the bond breaking model used in describing the surface energy. The formation of ledges and kinks are a consequence of entropic effects at temperatures greater than

Kink Site

Terrace

/ ;

Figure3-3. The surface of a substrate which is not perfectly oriented to coincide with an exact crystallographic plane consists of surface structures such as ledges, terraces and kinks in the terrace edges. These basis surface structures can influence the growth of the film.

122

3 Epitaxial Growth

a temperature of absolute zero. At 0 K, a wafer surface which has an orientation close to a major crystal axis, will consist only of terraces and ledges as shown in Fig. 3-4a. A surface which has a general orientation, i.e., not a singular or vicinal surface, will also have ledges consisting of sections interrupted by a jog or kink, i.e., a step in the line as shown in Fig. 3-4b. A vicinal surface is the most commonly used surface in epitaxial growth. The surface energy of a vicinal surface can be described through the aid of Fig. 3-5 which illustrates a wafer surface of a (010) orientation miscut by an angle 8 towards the [loo] direction. We will assume that 6 is small, i.e. 8 1 4 ” . The surface, shown in Fig. 3-5, will consist of monatomic steps of height s, with a density tan (I 8 /)is. The terrace will , have an average width i.where (3-9) At 0 K, the surface energy can be written as &i1)

E S ( 8 ) = E S = ( 0 )cos(@+ -sin(@

(3-10)

terrace

Figure 3-4. a ) At both 0 K and thermodynamic equilibrium, a substrate miscut towards a principal crystallographic plane will have only terraces terminated in ledges. b) A substrate of arbitrary miscut will possess kinks in addition to terraces and ledges.

Figure 3-5. A simple semiconductor surface will consist of terraces separated by monatomic steps (s). Under certain conditions, multi-step ledges are formed.

where E S ( 0 )is the energy per unit area of a singular terrace, d’) is the ledge energy per unit length of a ledge and E’(@ is the energy of the actual vicinal surface. It should be noted that the total terrace area is less than the total surface area, cos = (terrace area)/(surface area), where the ‘total surface area’ would be the area of a plane at the vicinal angle 8. As 8 increases, the amount of singular surface, relative to the total surface area, decreases. The last term in the expression is the ledge energy contribution to the surface energy. This is simply the ledge energy per unit length, ~(l), times the ledge density,

(e)

The inclusion of kinks into the calculation of the surface energy involves the addition of a term consisting of the energy per kink site, d2),and the kink density, Q. The kink density will depend, at 0 K, on the specific orientation of the surface. The surface energy then becomes (3-12) &(1) E S ( 6 ) = E S(0) cos(8)+ - sin(@+@E(’) S

3.2 The Epitaxial Process: General Features

Based on the number of possible broken bonds, an atom on a terrace will have the least number of broken bonds and will have the higher number of bonds to adjacent surface atoms. Atoms on ledges will have a higher number of broken bonds than the terrace while the kink sites have the fewest bonds to the surface. The surface energy of a particular feature will increase with the number of broken bonds. The kink sites will have the highest per atom energy followed by the ledge sites and finally the terrace sites. The surface structure, at equilibrium, will be determined by the minimum of this surface energy, at 0 K. It should be noted that the number of kinks, ledges and the terrace width are not independent variables but are constrained by the geometry of the surface, substrate orientation and vicinality. At higher temperatures, such as those used in the growth or deposition of epitaxial materials, the surface will have a more complex structure since entropy can play a role. As indicated in Eq. (3-3), the surface free energy contains both the surface energy (enthalpy) and the surface entropy. The increase in temperature allows the entropy term to gain in significance. Part of the surface energy will be associated with the configuration of atoms on the surface. As the temperature is increased, there is a driving force to increase the amount of disorder on the surface through the generation of atom vacancies, surface ledges and kinks. The addition of the these high energy structures increases surface energy but this increase is offset by the increase in the surface entropy. These energy considerations can lead to complicated surface structures. Such surface structures can be seen using surface sensitive techniques, such as the scanning tunneling microscope (STM) or electron diffraction. A STM micrograph of a Si surface is shown in Fig. 3-6.

123

Figure 3-6. A scanning tunneling micrograph (STM) of a clean (100) Si surface reveals the TLK structure characteristics of most surfaces.

The presence of such surface structures are readily seen in this picture, the flat terrace being bounded by alternating rough and smoother ledges. The alternating structure is attributed to the last aspect of surface structure important to the epitaxial growth of materials, surface reconstruction. So far, we have discussed the surface structure in terms of features residing on the surface of a truncated crystal. A truncated crystal is conceptualized as a surface formed by cleaving the crystal along a specific crystallographic plane. The bonds broken in this process are left ‘dangling’ from the surface. These dangling bonds are very energetic sites on the surface, readily forming new bonds with adatoms. The truncated crystal does provide an idealized view of the surface structure on an atomic scale. The very energetic dangling bonds left on the surface, in this construction, would however prefer to be part of a covalent bond if possible. This covalent bond could be formed through an interaction within an adsorbed species. In

124

3 EDitaxial Growth

the absence of adsorbed reactive species, the dangling bonds on the surface will often reform, bonding to adjacent atoms on the surface. This reformation process results in a new surface arrangement of atoms. This rearrangement away from the truncated crystal arrangement is referred to as surface reconstruction. Surface reconstruction on a semiconductor surface possesses both a short range and long range structure. The nature of the structure will depend on the temperature and surface chemical composition, as in the case of compound semiconductors. The reconstruction of a surface allows the surface energy to be decreased through the reformation of the broken bonds. Since the bonds are not at the angles and length found in the bulk, the energy expended in the creation of the surface is not fully recovered through the reconstruction process and hence the energy of the surface is still positive. The reconstructed surface of semiconductors will possess an altered chemical reactivity and therefore affects the process of epitaxial growth. The best studied surfaces, which are also used in epitaxial growth, are the (100) surfaces of Si and GaAs. In both of these cases the atomic level structure is dominated by the pairing of adjacent surface atoms, forming surface dimers. The dimers themselves can be arranged in a variety of configurations. The surface reconstruction of an epitaxial surface is most readily examined by electron diffraction techniques that can be easily incorporated into high vacuum growth apparatus, and by STM or AFM. The electron diffraction techniques average the surface structure over large dimensions while the STM images the atomic arrangement over a relatively small area. Both techniques can yield information on the details of the surface structure. The Si (100) surface is often characterized by

Figure 3-7. An atomic resolution image of the Si surface reveals that the terrace is composed of Si-dimer rows which alter their orientation with each successive layer.

rows of Si dimers running along the surface, as shown schematically in Fig. 3-7. The diamond structure of Si leads to an alteration of the Si dimer direction on successive planes of the Si crystal. This leads to dimer rows which rotate by 90" on each successive atom plane. This geometrical constraint has many implications for the transport of atoms on the surface and the attachment of new atoms to the growing surface. As seen in the STM micrograph of Fig. 3-7, the dimer rows end at step or ledge edges. If the ledge is parallel to the dimer row direction, a smooth ledge edge results. Ledges consisting of ends of dimer rows tend to be jagged and rough. The structure of these ledge edges is related to the detailed transport phenomena on the surface.

3.2.2 Surface Transport and Incorporation Film growth is the result of interaction between surface transport, structure and chemistry. The adsorbed species on the

3.2 The Epitaxial Process: General Features

growth front is often mobile and moves in order to find a favorable site for further decomposition, if necessary, and incorporation. The favorable sites on the surface are often the ledge edges and kinks described above which present a more reactive site. The initial deposition of an adatomcontaining species is typically thought of as occurring randomly over the surface. This picture is most correct for the physical deposition techniques which take place under ultra-high vacuum (UHV) conditions using elemental sources. The arrival of material to the growth front during CVD is quite different. In this case, adatom-bearing molecules can interact many times with the surface before final attachment to the surface. During these many interactions, the molecules can sample many different types of surface sites, Le., kinks, vacancies, ledge edges, and so on. The final site of incorporation will have the appropriate geometry and chemistry allowing for the chemisorption of material on the surface. The reconstruction and the larger scale surface features therefore play a central role at the atomistic level in the epitaxial growth process. The growth species, once adsorbed on the surface, can often move over the surface through the process of thermal surface diffusion. Surface diffusion will occur at any temperature above absolute zero. Since surface diffusion is a kinetic process, it will be extremely sluggish at very low temperatures and increase exponentially with temperature. Like any other diffusional processes, surface diffusion follows Fick’s laws. The flux of a species across the surface will be proportional to its gradient in chemical potential.or, for dilute systems, its concentration grradient (Borg and Dienes, 1990) (3-1 3)

125

where J is the flux across a surface, D, is the surface diffusion coefficient, and Cs is the local concentration of the diffusing species. The diffusion coefficient is determined by the same factor used in describing an atomistic picture of bulk diffusion. Temperature is the dominant factor in the diffusion Coefficient which depends on an activation energy, Q: D, = D o

.L-Q/(~B~)

(3-14)

If the activation energy is low, large diffusion rates can be observed. In general, activation energies for surface diffusion are smaller than that of the bulk. If diffusion entails the local breaking of bonds, a surface bonded atom most likely has fewer bonds to the substrate than a bulk atom has to neighboring bulk atoms. Hence, surface diffusion processes are typically more rapid. The diffusion coefficient also depends on a variety of factors which can influence both the pre-exponential term, D o , and the activation energy. The activation energy is comprised of the energy required for the atom to migrate from one low energy site, breaking its local bonds, to another low energy site. This contribution is referred to as the free energy of migration, Gmigr.The second contribution is related to the density of available sites for the atom to move into during the diffusion process. In many cases, the number of available sites is a strong function of temperature. The number of surface vacancies, ledges and kinks can all be a function of temperature through an activated process, characterized by an energy of formation, Gform.The concentration of vacancies, for example, typically follows an activated behavior. The activation energy is then the sum of both contributions, Q=Gmigr Gform.The pre-exponential term of the diffusion coefficient contains the frequency of jump attempts and geometrical configu-

126

3 Epitaxial Growth

ration (Borg and Dienes, 1990; Skewmon, 1989). The diffusion coefficient, along with the surface and interfacial energies, will determine the structure of the growing surface on an atomic and microscopic level.

3.2.3 Growth Behaviors The growth behavior in epitaxial systems is determined by the surface transport and the surface energetics of the materials system of interest. The above discussion focused on the surface transport required once the atoms are deposited. The atomic level motion and the energetics of the growth front will dictate the physical arrangement of these deposited atoms. The simple models of epitaxial growth predict different growth structures, derived from the chemical nature of the deposited atom, as well as the substrate serving as the template for the atomic arrangement of these species. In this case, there are generally two classes of epitaxial behavior based on whether the deposited atoms build a layer of the same structure and chemical composition as the substrate (hom*oepitaxial growth) or the growing layer is different in chemical composition, and perhaps physical structure, from the substrate (heteroepitaxial growth). Since epitaxial growth of a semiconductor requires that the deposited atoms assume an orientation which is directly related to the underlying substrate, there will, in both cases, be a known geometric relationship between the deposited layer and the underlying crystalline substrate. There are two dominant forms of growth behavior seen in hom*oepitaxial growth. These growth modes are related to the transport and incorporation kinetics of the adsorbed atom on the growth surface. Since there is no difference in the physical and chemical properties during hom*oepi-

taxy, this growth can proceed in a wellcontrolled manner. The growth or addition of atoms to the surface can proceed in two different growth modes or behavior: step-flow growth or layer-by-layer growth. These two-dimensional growth modes are often collectively referred to as Frank-Van der Merwe growth. (Three-dimensional growth can also occur, which results in a rough, uncontrolled interface.) In the stepflow mode, atoms deposited on the growth front diffuse to naturally occurring step edges. Since these step edges and step kinks, shown in Fig. 3-3, provide several atoms for the migrating atom to attach to, diffusing atoms will naturally bind there and be incorporated into the growing film. At high growth temperatures, the atoms have sufficient mobility to migrate across the surface before encountering other adatoms. The epitaxial growth then proceeds with the step-flowing across the growth front, leaving a very smooth atomically flat surface with a terrace-like structure. The characteristic terrace structure of step-flow growth, interrupted by monatomic steps, is seen in Fig. 3-7 for Si atoms on a Si surface. A similar terrace structure is found on GaAs during epitaxial growth by chemical vapor deposition as shown in Fig. 3-8 (Nayak and Kuech). This figure was obtained using an atomic force microscope. This particular epitaxial layer was grown at a high temperature, 650 "C, and a modest growth rate of 0.05 pm/min. At this growth rate, there is about one monolayer being grown every second. In this case, the steps are spaced about 0.1 pm apart. The miscut of this GaAs surface is 2" towards the (1 10) direction. This vicinal surface should have a terrace width of x7 nm if the steps are monatomic in height. The large terrace width indicates that the steps observed in Fig. 3-8 consist of more than a

3.2 The Epitaxial Process: General Features

Figure 3-8. A GaAs growth surface, formed by metalorganic vapor phase epitaxy (MOVPE), is also composed of the TLK structure. The GaAs surface presented here in an atomic force micrograph (AFM) has multi-atomic steps which are 3 to 4 atoms in height (Nayak and Kuech).

single atomic step. This phenomenon is referred to as step-bunching and is often seen in many epitaxial systems. The origin of the step-bunching phenomenon is complex and can be affected by the detailed chemistry of the attachment of atoms to the step edge, the diffusional process on the surface and any impurities on the growth surface. In step-flow growth, the transport of the atoms across the surface is rapid compared to the rate at which adsorbed adatoms would meet, bond together and nucleate a new layer of the growth surface. Since all the atoms are reaching a step, an estimate of the lower limit on the diffusion coefficient on the surface from the terrace spacing, A, can be made through (3-15) where Ds is the surface diffusion coefficient, t is the time for one monolayer growth, and

127

i / 2 is the average distance an atomic would have to move on the surface before reaching a step edge. For the GaAs image shown in Fig. 3-8, this simple formula leads m’js. to a value of about D s x 6 x The self-diffusion coefficient for Ga self-diffusion in GaAs at similar temperatures is much lower, values of Dbulk=IO-’’ m’/s being reported. Such a large difference between the surface and bulk diffusion coefficients is typical of values found in the semiconductor materials systems and reflects the lower number of bonds and the higher number of diffusion sites available to the adsorbed atoms on a surface. The step-flow growth described above does not always occur under the epitaxial growth conditions encountered in many growth techniques. The step-flow mode of growth only occurs when the diffusing atoms have sufficient time and mobility to reach a step edge and be incorporated into the crystal before encountering a sufficient number of other adatoms that can lead to the nucleation of a new atomic layer on an existing terrace. Both a high flux of atoms to the growth front and a low growth temperature, leading to a slow surface diffusiion of adatoms across the growing crystal, can lead to the shift from a step-flow growth behavior to the other dominant growth behavior referred to as layer-bylayer growth. In layer-by-layer growth, adatoms will encounter other adatoms on the growth front. Some of these atoms will bind together and result in the formation of a new layer of the crystal. The surface structure present in layer-by-layer growth can often have growth occurring over several layers at once as depicted in Fig. 3-9c, b. This multilayer growth can lead to a rough surface with many atomic levels. This rough growth can become part of the internal structure of the epitaxial materials. hom*oepitaxial growth is often

128

3 Epitaxial Growth

Figure 3-9. There are three principal growth modes commonly identified in thin film formation: a) Frankvan der Merwe or layer-by-layer growth, b) StranskiKrastanov growth (finite layer plus island growth) and c) Volmer-Weber or island growth.

used to create very sharp transitions in doping and hence electrical characteristics within the material. A smooth growth surface results in very sharp and planar internal interfaces. The use of conditions which result in a layer-by-layer growth mode will result, however, in a ragged transition region between two carrier types. Most epitaxial growth therefore is performed under growth conditions which yield step-flow growth behavior. The growth of a smooth internal interface becomes a more important issue when both the chemical composition and electrical characteristics change at the growth front as in the more complicated and yet more interesting case of heteroepitaxial growth. In this case, the deposited atoms

are different in chemical composition from the substrate. The best known heteroepitaxial semiconductor systems are Al,Ga, -,As grown on GaAs and SixGe,-x on Si. Heteroepitaxial growth has several distinct advantages over hom*oepitaxy as well as several complicating features. The major advantage is the use of bandgap engineering - the construction of layers with different bandgaps to achieve specific optical or electronic properties. There are several considerations which complicate the development of a heteroepitaxial growth technique. The primary considerations are the thermal expansion coefficients and lattice parameters of the two materials and the strength of the chemical bonding across the heterointerface. These three issues are not independent variables but they all contribute to the formation of the thin film structures. The chemical bonding between the growing overlayer and the underlying substrate can determine the growth behavior leading to large scale morphological features. Three fundamental growth behaviors have been identified in heteroepitaxy associated with initial nucleation and growth of the film. They are characterized by the surface energies associated with the interfaces between the epitaxial materials and the substrate. These three modes, Frank-van der Merwe, Stranski-Krastanov, and VolmerWeber growth, can be observed in several growth systems. Frank-van der Merwe growth is the single-layer growth mode discussed in reference to hom*oepitaxial growth. In terms of surface energies, the heteroepitaxial layer is considered to ‘wet’ the substrate leading to good uniform surface coverage. The formation of the heterointerface results in the destruction of the solid-vapor interfaces which would have been present had the materials chosen to not interact. A simple criterion for the ‘wet-

3.2 The Epitaxial Process: General Features

ting’ of the substrate is then YsA/sB

5 YsA/V + YsA/V

(3-16)

where is the interfacial energy between solid A and solid B and ySiiv is the surface energy of the solid vapor interface. The two solid-vapor interfaces were destroyed in the formation of the heterointerface. The formation of the interface is favored over the two separate interfaces. This type of behavior is found in systems which are chemically similar, e.g., GaAsAl,Ga, -,As, with similar lattice parameters. The ‘non-wetting’ of two materials hinders the formation of an initially single-layer growth mode. The epitaxial material does not bond to the substrate surface due to a difference in crystal structure, chemical reactivity or a very large difference in lattice parameter. Energetically, the inequality given in Eq. (3-16) does not hold and the two materials would prefer to form their own solid-vapor interfaces in preference to the solid-solid heterointerface: YsA/sS

’

YSA/V

(3-17)

The resulting initial growth behavior is a Volmer-Weber growth mode in which islands of the heteroepitaxial materials form on the surface of the substrate as shown schematically in Fig. 3-9. The material develops large growth islands whose density and shape are determined by the supersaturation of the growth ambient and the surface energetics of the growing islands. There are intermediate cases between these two growth mode extremes. The last major growth mode develops as a result of the interplay between the mechanical stresses which may develop in the thin film and the forces promoting adhesion between the epitaxial layer and the substrate. Lattice-matched heteroepitaxial semiconductor growth can proceed in a manner

129

quite similar to the hom*oepitaxial case, as described above, exhibiting a Frank-van der Merwe growth mode. Layer-by-layer and step-flow growth is observed in many systems in which the chemical bonding and lattice parameters are similar between the two materials. However there are many heteroepitaxial systems which have different bond strengths and lattice parameters with respect to the substrate. If the interfacial energy of the epitaxial layer and substrate favors a strong bonding or adhesion to the substrate, the initial stages of growth will generally be characterized by the deposition of thin planar films of epitaxial materials. The difference in lattice parameter will then lead to the development of internal stresses in the film due to the lattice mismatch between epitaxial layer and substrate. As the thin film strives to maintain perfect registry with the atoms in the substrate, the atomic positions in the epitaxial layer are shifted from their normal bulk values to conform to those of the atoms in the substrate. This shift in atomic position leads to a tetragonal distortion of the unit cell within the epitaxial layer and the development of an internal stress. Thin, highly perfect layers can therefore be grown in which the atoms in the thin layer are locked in perfect registry with the plane of the substrate surface despite the lattice mismatch. This process is referred to pseudomorphic growth. It is therefore possible to grow highly mismatched materials, without extended defects, to a limited or ‘critical’ thickness (Fitzgerald, 1991). The exact maximum thickness prior to the formation of extended defects which relieve the built-in stress, commonly referred to as the critical thickness, is specific to the particular materials combination. Many interesting materials structures can be invented and have been developed based on the use of pseudomorphic materials integrated in-

130

3 EDitaxial Growth

to a multilayer structure. The internal stress in the films can modify the electronic band structure which leads to the controlled formation of new optical and electrical properties which cannot be obtained in the nonstressed semiconductors. As the epitaxial layer grows, this internal stress continues to develop until the elastic energy stored in the film is sufficient to be released in the formation of defects. These defects occur typically in the form of dislocations. These dislocation can further multiply and propagate through the extent of the film releasing the internal stress and relaxing the atomic positions in the epitaxial layer to their bulk positions. Once the strain in the deposited film becomes too large, the film relaxes and three-dimensional islands form on the surface. The formation of the strain relieved structure, beyond the critical thickness, often leaves a structure in which there is a thin pseudomorphic layer remaining next to the substrate with the three-dimensional island growth of the defected and strained relieved materials residing above this layer. This growth mode, schematically shown in Fig. 3-9 b, is referred to as a Stranski-Krastanov growth mode. There are several common epitaxial growth modes which have been observed, as described above. The appearance of a particular growth mode has been rationalized in terms of the interfacial energies associated with the epitaxial layer-substrate interface and the stresses induced by the lattic mismatch. Other considerations can often dominate the appearance of a particular growth mode. The temperature and rate of growth, as well as other kinetic factors, can often give rise to growth behavior which would not be expected on the basis of purely energetic considerations. Lastly, the final microstructure and morphology of the epitaxial films will also be affected by

the initial perfection of the substrate and the difference in thermal expansion coefficients of the two materials. Defects in the substrate can propagate into the epitaxial layer. A dislocation intersecting the growth front will continue into the epitaxial layer since this structural information forms part of the epitaxial seed that is replicated into the growing film. Almost all epitaxial films are grown at temperatures which are substantially higher than room temperature. The difference in thermal expansion coefficients may also generate a great deal of strain in the film upon cooling from the growth temperature. This strain may also be released through the formation of dislocations and other extended defects.

3.3 Chemical Vapor Deposition: Technology and Issues Chemical vapor deposition or CVD is the deposition of thin films from the gas phase onto a substrate. As such, this process encompasses a wide variety of concerns which are not seen in other forms of crystal growth, such as those based on physical evaporation. Gas phase and surface chemistry, along with the thermal fluid environment from which the crystal is growing, must be controlled to a high degree in order to produce a high quality crystal that will become the device structure of interest. The basic CVD system consists of a flowing gas phase ambient which passes over a heated substrate. The mechanical aspects of the CVD system are conceptually divided into two separate components: the gas panel and the reactor. The gas panel mixes and schedules the gas phase reactants or nutrients into the reactor. The gas panel construction is designed so that accurately synthesized mixtures of reactants are injected at precisely the cor-

3.3 Chemical Vapor Deposition: Technology and Issues

Induction Coil

131

Silicon Wafers

Radiant Heaters

&ccocco,accc

Gas -nI

ccoccommm

Horizontal CVD Reactor

yL ,Exhaust Barrel CVD Reactor

control 0

Gas

xhaust

Horizontal LPCVD Reactor

Vertical CVD Reactor

Figure 3-10. Schematic of several reactor configurations commonly employed in chemical vapor deposition technology.

rect time to yield the desired structure. The valves and meters used in its construction are designed to exclude unintentional contaminants which would lead to unwanted impurities in the films. While the gas panel is of a common design in most CVD systems, the CVD reactors are quite varied depending on the growth chemistry and desired product. The reactor design is therefore materials specific. Examples of various reactors used in the epitaxial growth of semiconductors are shown in Fig. 3-10. The features important in most of these reactors centers on the uniform flow of nutrients over the growth surface of the wafer and the removal of the reaction by-products. The CVD growth of semiconductors is often conceptualized as consisting of several

steps, as schematically shown in Fig. 3-11 for the case of Si growth. Generally, the slowest of these steps will limit the observed growth rate. There are several principal factors which influence each of these primary conceptual steps in the CVD epitaxial process. Energy is directed into the reactor in order for the desired chemical reactions to occur. This energy comes typically in the form of heat through the placement of the reactor in a furnace or through the use of a locally heated substrate holder. In the latter case, the walls of the reactor and the gas stream can remain cool relative to the hot substrate. This latter configuration suppresses the gas phase decomposition of the nutrients prior to their arrival at the growth front. In all cases, there are common features to the CVD process

132

3 EDitaxial Growth

‘ w e l l m i x e d ’ g a s at a m b i e n t T _ _ Jnm

3.3.1 Reactors: Mass, Fluid, and Thermal Transport

pw A-

3.3.1.1 Fluid Behavior and Reactor Design

Transport to surface:

Surface Reaction:

Jsurllcp

Jgrovrh

= K , Psur‘‘cc Jgas

Jsurlsce

K . Pgrr

Figure 3-11. Si growth. like most semiconductor growth systems. can be conceptualized as consisting of several steps as shown here, involving gas phase and surface chemistry as well as surface transport leading to the incorporation of the deposited atom into the growing structure.

which bear on the growth of most epitaxial films. The specific nature of these elementary steps can influence the film composition, its electrical and optical properties, the uniformity of the thickness of the film and properties across the substrate and between substrates, the structure and abruptness of electrical and compositional interfaces, and finally the presence of defects in the film. The issues of uniformity and defects bear directly on the utility of the epitaxial films in later device processing. Defects, particularly morphological defects on the growth surface, make subsequent processing difficult, particularly the process of photolithography. The discussion of the epitaxial growth of semiconductors by CVD will therefore center on the principal influences of each of these primary steps in the microscopic model of the film growth.

The CVD reactor is typically a reaction chamber through which the reactant gases flow and in which the heated wafers are placed. There are several principal reactor geometries which are,used in the growth of compound and elemental semiconductors. The choice of a specific reactor depends on the growth chemistry and pressure regime used in the growth process. These operating conditions are in turn determined by the growth chemistry. The four reactors shown in Fig. 3-10 are those most commonly found in the manufacturing of epitaxial semiconductors. The horizontal, barrel and rotating disk reactors are all forms of ‘cold-wall’ reactors. These reactors operate at relatively high pressures, between 1 Torr and atmospheric pressure (760 Torr). The fourth reactor pictured in this figure is a low pressure ‘hot-wall’ reactor referred to as an LPCVD system. This reactor operates at pressures as low as 0.001 Torr or about atm. The mass and fluid transport in these systems can be quite different. The first three systems operate in the viscous fluid regime where the continuum mechanics description of the fluid behavior can be used. The LPCVD can be operated in the molecular flow regime. The specific flow regime of the CVD environment is characterized by the Knudsen number which is based on the ratio of the mean free path of the gas molecule, A, to the typical physical dimension of the reactor, L : K n = i / L . The mean free path of a gas molecule of diameter d, at a gas pressure of P, is given by (3-18)

3.3 Chemical Vapor Deposition: Technology and Issues

The Knudsen number is one of the many dimensionless numbers which can be used to describe general features of the fluid, thermal and mass transport. The mean free path of a gas molecule at room temperature is approximately given by A (cm)= O.OOS/P, where P is the pressure in Torr. At atmospheric pressure, ( 760 Torr) the mean free path is about 70 nm while at a low pressure of Torr the mean free path is 5 cm. The major flow regimes are then classified by the magnitude of the Knudsen number:

133

LAMINAR

TURBULENT FLOW

viscous flow transition flow molecular flow

Kn 4 1 Kn z 1 Kn 1

I .

Figure 3-12. Laminar flow profiles can be developed in the reactor chamber leading to a controlled and regular flow of gas over the growing substrate surface.

The viscous regime is characterized by low temperatures and high pressure. Most CVD systems which operate at moderate or near atmospheric pressures are therefore in the viscous flow regime. In this pressure regime, the fluid transport is described by the traditional fluid transport models which provide the equations governing the thermal, momentum and mass transport in the reactor. While the complete solution of the transport equations is generally dificult, several simplifications have arisen which provide a heuristic model of the growth environment. The design of CVD systems within this pressure regime typically focuses on the development of a laminar flow profile within the reactor. Laminar flow is characterized by the gas flowing smoothly across the surface, without turbulence, as shown in Fig. 3-12 for the case of a horizontal growth system. In the rotating disk reactor, a spinning disk is the substrate holder which acts as a centrifugal pump, resulting in a radial flow of gas across the surface. In the absence of laminar flow, turbulence or irregular mixing leads to a high degree of non-uniformity in the film growth since the gas flow and hence the flux of nutrients to the surface is

changing with time. Laminar flow is readily established in most systems within a short entrance length of the reactor. The full fluid mechanical treatment can be subsequently carried out for most of these reactors. Such modeling efforts, requiring the numerical solution of the coupled heat, mass, and momentum transport equations, can be solved with considerable effort. The results of these calculations provide a detailed picture of the transport of nutrients within the CVD reactor. The calculated flow patterns resulting from such a calculation for a horizontal system is presented in Fig. 3-13 (Vossen and Kern, 1991). A complex fluid flow behavior within the reactor can be seen in this figure. The complexity of these flow fields, which add to the nonuniformity of the growth, can often be suppressed by an appropriate choice of growth conditions. In particular, the reduction in the reactor pressure at a constant mass flow can eliminate many of these recirculation effects and lead to a laminar flow profile in the reactor. Once laminar flow is established, the resulting gas phase fluid transport across the growth front is often characterized by the use of boundary layer

134

3 Eoitaxial Growth

_--

Figure 3-13. Numerical solution of the basic equations governing the mass, fluid and heat transport in the reactor can be used to predict many of the complex flow patterns and phenomena in a CVD reactor. This figure illustrates the results of such a calculation for a horizontal reactor. (a) The predicted flow pattern from a symmetric and asymmetric inlet geometry. The latter leads to a complex fluid flow. (b) Recirculations in the flow field can result from geometric differences in the reactor shape [Vossen and Kern, 19911.

theory. Boundary layer theory is a simplified description of fluid flow based on specific assumptions. A boundary layer is a hypothetical gas phase region near the growth surface over which the gas velocity is zero. This stagnant region of gas allows for the easy solution of the diffusion equation for mass flow across this boundary layer. The extent of the boundary layer is dependent on the gas velocity and viscosity. It arises from the ‘no-slip’ condition at the reactor walls where the gas velocity is zero. In practice, the assumptions of the boundary layer theory are not strictly met for most reactors, yet this simplification can predict some of the general features of the growth process. The flux to the surface is found by postulating a growth reaction at the surface in series with the gas phase transport to the growth front as seen in Fig. 3-1 1. The diffusion of growth nutrients

across this boundary layer provide the growth front with the reactants for the film to develop and grow. .4t steady state, the flux through the gas phase and the reaction rate at the surface are equal. Several reviews and discussions of the modeling methods and considerations used in describing these reactors can be found in the references to this chapter (Hess and Jensen, 1989; Middleman and Yeckel, 1986; Ouazzani and Rosenberger 1990; Vossen and Kern, 1991). LPCVD reactors, as shown in Fig. 3-10, typically have a large number of wafers that are stacked close together within the heated region of the furnace. Models of these reactors consider the gas flow around the wafers as well as between the wafers. The calculation of the fluid flow in such systems is divided into two separate regimes where the gas flow in the annular region around the wafers is often treated as a viscous fluid flow and the mass transport radially between the wafers is considered to be diffusionally based. This model provides an accurate picture of the fluid and mass transport until the characteristic distances, such as the wafer spacing, become less than the mean free path in the gas. Reactors operating in the molecular flow regime, K n 6 1, are often used when the growth rate is limited by the surface reaction rate of a growth species. In this case, the simple models based on continuum fluid mechanics and diffusion are no longer accurate. The detailed motion of individual gas molecules, as they enter, transverse, react and leave the reactor must be considered. This detailed molecular description is addressed through numerical techniques which have been developed to build a macroscopic description of the growth process from the trajectories of individual molecules. These calculational methods, referred to as Monte Carlo techniques, are

3.3 Chemical Vapor Deposition: Technology and Issues

based on the statistical nature of molecular flow. Such numerical models require timeconsuming calculations, but can yield an accurate description of mass transport in the reactor. 3.3.1.2 Mass and Thermal Transport

The fluid behavior within the reactor provides a description of the overall mass motion in the system. In LPCVD growth there is a high mole fraction of the reactants in the gas phase, while, in the case of higher pressure growth processes, the reactants are diluted in a carrier gas. A carrier gas is typically an inert dilutent, such as He, N, , or H, , which is used to control the partial pressure of the reactants while maintaining an overall reactor pressure or flow. In the case of LPCVD systems, the mass transport is largely given by the fluid flow. The high pressure reactors possess a reactant mass transport due to both convection, through entrainment in the carrier gas flow and diffusion through the boundary layer. The gas phase diffusion coefficient for thermal and mass transport are similar in magnitude and their transport in these types of reactor are described by similar theoretical formalisms. The uniform growth of an epitaxial film requires that the flux of the reactants to the growth front be uniform over the wafer surface as well as among all the wafers in the reactor. This uniformity requirement places constraints on the mass transport in the reactor. The mass transport must be designed to provide this constant flux to the surface despite changes gas phase conditions in the reactor. The mass transport in high pressure reactors is complicated by the consumption of the nutrients as the gas flows over the heated growth surface. The growth rate, GR, of the film, measured in thickness per unit time, is equal to the flux of nutrients at

135

the growth surface (3-19) where D is the gas phase diffusion coefficient and c is the concentration of reactants in the gas phase at the growth front and no is the number density of atoms in the film. The gas phase diffusion of reactants near the surface is modified by the overall fluid flow and the gas phase concentration of reactants. The gas phase reactant concentration will vary over the surface of the wafer because of depletion of the reactants from the gas stream resulting from upstream deposition of the thin film. The design of the reactor can substantially reduce these depletion effects. Early modeling efforts treated this depletion of the gas phase of reactants through the formation of a diffusional boundary layer of thickness Jdiff,in analogy to the boundary layer formed as the laminar flow profile is generated in the fluid flow. This diffusional boundary layer will grow as the gas flows over the heated substrate and the gas phase near the growing wafer becomes depleted of nutrients (3-20) where v is the kinematic viscosity of the gas, V,, is the mean stream velocity of the gas, and x is the distance along the gas flow. The flux to the surface or GR can then be approximated by D

(3-21)

c being the gas phase concentration of the reactants in the bulk of the gas at a given position along the reactor. Since d d i f f is a function of position in the reactor, the growth rate will, in principle, vary along

136

3 Epitaxial Growth

the length of the reactor. In order to achieve uniform growth over large substrate areas in a horizontal reactor, the cross-sectional area of the reactor is often reduced in order to locally increase the V,, in the reactor. This increase in the gas velocity along the reactor can offset the drop in the growth rate due to gas phase depletion. Other approaches to increasing the uniformity have been the use of other alternative carrier gases to H, , which alter the gas phase viscosity, as well as the use of very high reactor flow velocities. The latter approach can lead to the growth of uniform films at the expense of low utilization of the growth reactants.

3.3.2 Gas Phase and Surface Chemistry The description of most chemical systems begins with an equilibrium thermodynamic analysis of the overall process. The term equilibrium implies that the system is unchanging in time which is clearly not the case for the process of crystal growth. The process of crystal growth is inherently not an equilibrium thermodynamic process since it entails a net deposition of material. As described above, the growth rate of a material can be affected by a variety of macroscopic transport phenomena. No matter what the transport limitations are in the system, there must be a thermodynamic driving force for the deposition of material. This driving force or supersaturation can be calculated by the application of conventional concepts of the law of mass action to the chemical reactions of importance for film growth. This driving force arises from the free energy change of the overall chemical reaction responsible for the net deposition of material. The application of thermodynamics can provide some useful and important information on this driving force. Thermodynamics can indi-

cate whether a reaction is energetically possible and, if it is possible, the expected maximum extent of that reaction. While thermodynamics can indicate the feasibility of a reaction, the actual occurrence and rate of the reaction will depend on the temperature and the specific species involved. Not all reactions will occur under the desired thermal conditions supplied in the reactor. In those cases, non-thermal energy sources are often used. External energy sources, such as ultra-violet (UV) radiation or an applied plasma, can provide SUEcient energy to initiate the growth reaction through the breakdown of the growth precursor. In most cases, the simplicity of implementation and uniformity of growth afforded by the simple heating of the substrate is favored over these other energy sources. The growth chemistry occurring within the reactor is generally divided between that occurring in the gas phase and on the surface. There has been a wide assortment of gas phase compounds used in the growth of semiconductors. Some of the more common reactants for silicon deposition are listed in Table 3-2. Many of these compounds will decompose or react in the gas phase at relatively low temperatures. Disilane, Si$,, will rapidly decompose in the gas phase at temperatures of 700°C. The reaction products will further react in the gas phase producing other species which eventually reach the surface. The gas phase decomposition of Si,H, eventually leads to a mixture of SiH,, Si,H,, and SiH, reaching the surface, as shown below. Disilane decomposition (unimolecular decomposition) Si,H,

* SiH,+SiH,

(1)

Silane formation (gas phase reaction) (2) SiH,+H, * SiH,

3.3 Chemical Vapor Deposition: Technology and Issues

137

Table 3-2. Thermodynamic and physical properties of Si-based growth sources. State at room temperature

Vapor pressure at 22°C (Torr)

Free energy of formation (kcal/mol)

SiCI, SiHC1,

liquid liquid

- 148.16

SiH,Cl, SiH,Cl SiH, Si,H,

gas gas gas gas

208 533 1200 (23 psig) 47 990 (928 psig)

Compound ~~

Disilane reformation (gas phase reaction) (3) SiH,+SiH, =- Si,H, In this case, the use of disilane leads primarily to the arrival of SiH, and Si,H, to the growth front since reactions (2) and (3) occur very rapidly in the gas phase at elevated temperatures in a H, carrier gas. Such a rapid reaction leads to a very low steady state concentration of SiH, in the gas phase. If the gas phase decomposition of Si,H, goes to completion, i.e., the formation of SiH,, disilane-based growth of Si would then result in a factor of two in growth rate over that found with SiH,. In this case, gas phase reactions result in the in situ generation of a growth precursor, SiH,, which reaches the surface. Not all gas phase reactions lead to benign or useful reaction products. Many compound semiconductors are grown through the metal-organic vapor phase epitaxy (MOVPE) process. A feature of this process is the use of volatile metal compounds, such as (C,H,),Ga and (CH,),In, typically in conjunction with group V hydrides, such as ASH, and PH, . The metal organic compounds, while being stable at room temperature, do undergo gas phase decomposition at temperatures low compared to typical substrate temperatures. These compounds decompose and react in the hot gas phase regions of the

-115.34 -43

+13.6

+ 30.4 reactor, as well as at the growth surface, leading to depletion or elimination of the growth reactant prior to its arrival to the growth surface. The decomposition of the metal organic compounds leads to nonvolatile by-products, containing the metal species, which are deposited on the reactor interior walls. This gas phase pre-reaction results in a reduction of the growth rate and an increase in growth rate non-uniformities along the wafer. Other types of deleterious gas phase reactions lead to the formation of undesired gas phase chemical species which are subsequently transported to the growth surface and result in defect formation. This is particularly true for particle-forming reactions. The gas phase reactions described above all depend on temperature and reactor pressure. In the case of the metal-organic compounds, the use of a ‘cold-wall’reactor allows the gas phase to remain cool prior to its arrival to the growth front. The gas phase reactions are therefore suppressed. Many reactions, such as the uni-molecular decomposition of Si,H, given in Eq. (I), rely on collisions with other gas phase molecules for their initial stages of decomposition. These gas phase decomposition reactions can be effectively suppressed through the use of low reactor pressures. The low reactor pressures reduces the probability of gas phase collisions and sub-

138

3 Epitaxial Growth

sequent decomposition. Low pressure reactors utilize this dependence on the reactor pressure to eliminate the gas phase decomposition of the growth reactants. In these cases, the gas phase chemistry no longer plays a great role in the growth chemistry. As a result, the direct reaction of the growth reactants with the growth front is the principal reaction in the overall growth chemistry. The thermodynamic and mass transport relationships can determine the necessary conditions for growth and the uniform arrival of the growth nutrients to the surface. Once at the surface, the decomposition and incorporation of the material will be dependent on the details of the surface structure and surface chemistry. The elementary steps in these surface processes start with the adsorption of a reactive species. The adsorption of these species depends on the availability of an adsorption site and the energy required or released upon adsorption for reactions. There are often many gas phase species competing for the same surface sites. The resulting surface composition, in terms of adsorbed species, will be the result of this competition, determined by the relative gas phase concentrations and the energetics of the adsorption process. The surface adsorption of reactive species can be described by several simple models. Most of these models are based on equilibrium thermodynamic considerations. In these models, the surface concentration of reacting species will result from a balance between the arriving species, Rgas,interacting with vacant surface sites, V, and those adsorbed species, R,, which may subsequently be available for desorption. adsorption: R,,,+V desorption:

R,+V

% R, Rga,+V

(4) (5)

where kad and k d , are the rate constants for the adsorption and desorption processes. The simplest of these models is the Langmuir adsorption isotherm. This model assumes thermodynamic equilibrium between the gas phase and surface adsorbed species, The constraints in the model include the restriction of only one type of surface site and a limit of one monolayer of adsorbed species. The fraction of available adsorption sites is given in terms of the reactant partial pressure in the gas phase. The fraction of available adsorption sites, 0, covered by given reactive species is given by (3-22) where P is the partial pressure of the reactive species, Rgas,over the growth surface, and c1 is typically written in Arrhenius form as (3-23)

Qad being an activation energy associated with the adsorption process, and a. a constant (Adamson, 1990). This simple equation allows for a description of the temperature dependence and the partial pressure dependence of the surface concentration of reacting species and can often, despite its simplicity, describe the features of many adsorption processes. At low partial pressures, the surface coverage is simply proportional to the gas phase concentration: 0 z a P. Correspondingly, at high pressures, the surface coverage becomes unity. Temperature affects the surface coverage through favoring high coverages at low temperatures where the desorption of species would be suppressed. The Langmuir adsorption isotherm can be modified to account for more than a single adsorbed species. If several species

3.3 Chemical Vapor Deposition: Technology and Issues

are competing for the same adsorption sites, the site coverage of each species will be affected by the presence of the other chemical entities on the surface. The site fraction of a particular adsorbed species is then given by

139

The growth rate expression, formed by combining these two expressions, will have a temperature dependence related to both the adsorption and decomposition processes, combined with the gas phase concentration of reactant at the growth front

(3-24)

krxn,O a0

P ~ X(-(Q;+Te,xn)) P

GR = where the sum is over all the species ( j ) available for adsorption. This is a common situation during growth. In the case of SiH,-based Si growth, SiH, , SiH,, and H all complete for the same sites on the surface. Adsorption is the first step leading to a surface reaction. Once adsorbed, the reactant undergoes further decomposition or reaction with an ultimate by-product being the incorporated atom. There are several simple types of surface reactions which may occur. In practice, these simple models may not adequately describe the detailed surface reaction kinetics, but they do serve to describe the overall phenomena. The reaction rate of adsorbed species will be dependent on its surface coverage, the concentration and nature of the nearest neighbors and the temperature. The gas phase chemistry is coupled into the surface or heterogeneous reactions to complete the model of the growth chemistry. The simplest model of the surface growth reactions is the direct decomposition of the reactant on the adsorbed site. In this case, the growth rate will be proportional to the surface coverage of the adsorbed reactant

(3-27) This relationship can lead to a complicated behavior dependent on growth temperature and reactant concentration. For many systems, the partial pressures and resulting surface coverages of reactant are low, leading to the reduced expression

where k,,, is a rate constant for the decomposition of the surface species. This rate constant is also assumed to follow an Arrhenius rate expression

This expression indicates that the growth rate will have a linear dependence on the gas phase reactant concentration and an exponential dependence on temperature. Such behavior is often seen in many CVD growth systems despite the actual presence of a more complicated growth chemistry than assumed in this simple model. More complicated surface reaction schemes have been proposed to describe the CVD growth behavior. Many surface species require the co-reaction of two adsorbed species on nearby sites for the completion of the growth reaction. In this case, the growth rate will be proportional to the surface coverage of both reacting species. Again, the surface coverage of each species could be described by the Langmuir model. The growth rate reaction will then be proportional to both reactant surface coverages. The constant of proportionality will be the reaction rate constant k,,,

(3-26)

(3-29)

GR cc 0 or GR=krX,0

(3-25)

140

3 Epitaxial Growth

This particular model is referred to as the Langmuir-Hinshelwood reaction law and has been used to describe the growth behavior of GaAs from (CH 3 ) ,GA and ASH3 . The temperature and pressure dependencies of this expression are quite complicated and have been used to explain the often observed complex behavior of the growth rate on reactor variables. The generalization to other growth situations can be derived through a combination of the adsorption law and the assumption of a specific chemical mechanism. Examples of the development of these rate relationships for common CVD epitaxial systems will be discussed later. The surface reactions involved in epitaxial growth are dependent on the detailed surface structure present at the growth temperature under the chosen growth conditions. These surface structures are, in turn, partly determined by the presence of adsorbed species. Steps, kinks, and terrace structures, as well as local reconstruction, can present a variety of different adsorption sites for the arriving chemical species. In particular, impurities can adsorb, in addition to the primary growth reactants, on the surface perturbing the growth chemistry and the growth morphology. The incorporation of impurities has been described using the same concepts as discussed for the growth reaction itself. The impurity source can undergo gas phase reactions, adsorb on the surface, and be incorporated into the growing film. Many impurity sources can only strongly adsorb at specific surface sites, e.g., steps on the surface. Small variations in substrate orientation, sometimes referred to as miscut, lead to large changes in the efficiency of impurity incorporation. Such detailed factors can complicate the growth behavior and final properties of the epitaxial film.

3.4 Liquid Phase Epitaxy (LPE) Technology Liquid phase epitaxy (LPE) was first demonstrated by Nelson (1963) and has been used to deposit a wide range of materials, including 111-V and 11-VI semiconductors, as well as magnetic garnet materials (Giess and Ghez, 1975). The flexible nature of LPE and the ability to produce high purity material has been used to produce the first demonstrations of many electronic and optical devices, including the first room temperature cw operation of a GaAs/Al,Ga -,As double heterostructure laser. The advantages of LPE include relatively simple and inexpensive equipment, high utilization efficiency of precursor material and the ability to produce high purit y and high optical efficiency material over a wide range of thicknesses. In addition, LPE is a near-equilibrium growth technique. The growth rate is strongly dependent on the substrate orientation, which leads to unique abilities to regrow and planarize patterned substrates. These advantages have made LPE a common deposition technique for a wide range of LEDs where low cost is a major issue as well as buried heterostructure and DFB lasers which take advantage of LPE’s regrowth capability. The weakness of LPE comes from its inability to controllably grow very thin layers of a specific composition required in heterostructure electronic devices such as superlattice or quantum well devices. The growth rate in LPE is generally higher than in MOVPE or MBE, which limits LPE’s ability to produce very thin layers. Absolute layer thickness control is also not as good as these other techniques, as a result of the manner by which the growth is initiated and terminated. Because LPE is a near-equilibrium technique, not all materi-

3.4 Liquid

als can be grown by this technique. Miscibility gaps occur for some compositions of ternary and quaternary materials which prevent their deposition by LPE due to phase separation during growth. Finally, surface morphology is typically not as good as in MOVPE or MBE, which again precludes its use for the growth of certain device structures. Thus, for more sophisticated devices which include quantum wells, superlattices or etched gratings, MBE and MOVPE are most commonly the growth techniques of choice. LPE growth occurs by precipitation of the desired material out of a supersaturated solution onto a substrate. In contrast to MOVPE and MBE, LPE takes place very near to equilibrium in a column-111-rich environment. The solvent element is typically the column I11 constituent of the compound to be deposited (Ga or In); in some cases other low melting point metals such as Sn, Bi or Pb are used as the solvent. The thermodynamic driving force for LPE growth is produced by cooling the system below the liquidus temperature. In the

0 Ga

0.5 x - b

1 As

Figure 3-14. The Ga-As phase diagram can be used in the development of the LPE growth process of GaAs.

Phase Epitaxy (LPE) Technology

141

phase diagram for GaAs, shown in Fig. 3-14 (Casey and Panish, 1973), only a liquid exists above the convex line. Melt growth (i.e., Czochralski) is performed at the melting point of the stoichiometric solid (1238"C for GaAs) while LPE is performed at much lower temperatures. LPE growth of GaAs takes place by cooling a solution of Ga, containing a small amount of As at a temperature, TI, to its liquidus temperature, T,, at that composition, for example point B in Fig. 3-14. Upon further cooling to temperature, T,, at point C, the solution becomes supersaturated and GaAs begins to precipitate or grow onto the substrate. When suficient GaAs has precipitated out, such that the liquid is no longer supersaturated, growth stops at point D. During this period, the liquid composition changes from B to D. Since most of the 111-V binary compounds are line compounds (i.e., no measurable hom*ogeneity range), only stoichiometric GaAs is deposited. In ternary and quaternary compounds, this is not necessarily true since the composition of the deposited film depends on the supersaturation and liquid composition. As a result, not all alloy compositions can be grown at an arbitrary temperature. Many ternary and quaternary alloys possess a miscibility gap. A miscibility gap in the phase diagram implies that two solid phases or two solid compositions will simultaneously grow out of the liquid solution depending, of course, on the specific temperature and liquid compositions. Three principal variants of the LPE technique have been reported in the literature: tipping, dipping and sliding. Only the latter variant slider-based LPE, has seen widespread use. Tipping was the technique first used for LPE. In the tipping technique, the melt and substrate are placed at opposite ends of a crucible. Growth begins

142

3 Epitaxial Growth

by tipping the crucible so that the melt flows over the substrate. Growth is terminated by returning the crucible to its original position, thus removing the melt from the substrate. This method is limited to the growth of a single layer. The dipping technique permits the growth of multiple epitaxial layers on the substrate. In the dipping technique, the substrate is dipped into the melt to initiate growth, and removed from the melt to terminate growth. The substrate is moved to an additional dipping station and the growth procedure is repeated, accomplishing the growth of an additional layer in a multilayer structure. This technique has been used for multiple layer growths and for some commercial devices, however, like the tipping technique, thickness uniformity is only moderate. Device requirements of multiple layer structures, with thin layers of different compositions, have led to the dominance of the sliding method. The slider method is the most widely used for LPE because it permits straight-

forward growth of multiple layer structures with acceptable thickness uniformity. A schematic view of the slider system is shown in Fig. 3-15 and consists of a tray which holds the substrate and a slider which has multiple bins for different melts (Kuphal, 1991). Each melt is associated with the growth of a different layer and therefore requires a different melt composition. For example, p-n junctions are made by having one melt contain a p-type dopant and the next melt an n-type dopant. Heterostructures can be produced by preparation and use of ternary or quaternary melts. The slider fits over the substrate holder tray and growth is initiated by sliding a bin containing the desired melt over the substrate. The components of the LPE system are made of graphite. The melts do not generally wet the graphite, which permits termination of growth by wiping the melt off from the substrate when the slider is moved. This assembly is housed in a quartz tube which is purged with high purity hydrogen. A movable multi-zone fur-

Solution Bins

I Slider Assembly

Figure 3-15. Schematic view of the commonly used horizontal slider-type LPE system.

3.4 Liquid Phase Epitaxy (LPE) Technology

nace typically surrounds the quartz tube. Often a heat pipe is placed within the furnace to promote flat temperature zones. The slider is positioned using a quartz rod; this can be done manually or through a stepper motor controlled by a computer. Graphite covers are typically placed on top of the melts to prevent evaporation and contamination of the liquid melt. The melts that make up the LPE system can either be single- or two-phase. A single-phase melt is a liquid that is supersaturated at a specific temperature. The supersaturation must be small enough to prevent spontaneous nucleation of the solid phase in the melt. A two phase solution consists of a melt which contains a solid source. The graphite cover may be replaced by a substrate of the type being grown, assuring uniform saturation of the melt. The major advantage of the twophase method is to simplify control over the growth process. For example, in LPE the growth rate is determined by the exposure time and the degree of super saturation. In the two-phase method, the floating substrate melt cap acts as a source or sink of material to ensure saturation of the melt during the initial heating state. In addition to ensuring saturation, the cover also prevents source evaporation and helps control the geometry of the melt. Since there are now two substrates, when the system is cooled, growth takes place on both substrates. Depending on the thickness of the melt, this can result in a desirable decrease in the growth rate on the intentional substrate. It should be noted that this technique is most advantageous for the growth of binary compounds since substrates with arbitrary ternary and quaternary compositions are not available. The slider technique has been developed through many years of research and development experience. Slider LPE production-scale systems

143

exist which are computer controlled and can handle multiple round substrates, up to 50 mm in diameter (Shea et al., 1993). There are a number of practical problems in the LPE-slider technique. For example, enhanced edge growth on the substrate is a potential problem for LPE. Enhanced edge growth occurs for several reasons, such as an orientation-dependent growth rate, thermal convection and nonone-dimensional diffusion of the solute in the melt. If the grown layer thickness at the edge of the substrates becomes larger than the space between the substrate holder and the melt slider, graphite and the grown material will be scrapped off by the slider and cause scratches and other defects on the growth surface. This space cannot, however, be made too large or some of the melt will be carried over and contaminate the adjacent melt. The substrate-slider spacing is typically between 20 and 100 pm, which puts limits on maximum layer thickness as well as tolerances on substrate thickness. Enhanced edge growth can be minimized by reducing thermal convection in the melt through the use of small cooling rates or isothermal (step) growth and through the use of thin melts with lids which reduce two-dimensional diffusion. It can also be eliminated by making the melt contact area smaller than the substrate. 3.4.1 LPE Growth Procedures The growth procedures in the LPE-slider technology are centered on the preparation of the melts and the time-temperature program of the subsequent growth sequence. Figure 3-16 illustrates a representative temperature cycle for LPE growth (Kuphal, 1991). The system is first heated to a temperature which is above the saturation temperature T,. This step produces a hom*ogeneous melt. The temperature is

144

3 Epitaxial Growth

Time

Figure 3-16. Representative temperature cycle for LPE growth.

then lowered and the melt brought in contact with the substrate. Two common methods for lowering the temperature are shown, ‘equilibrium’ and step cooling. In ‘equilibrium’ cooling, the system is slowly cooled during the growth step from T, to an end temperature, T E .In step cooling, the system is cooled to the supersaturation temperature TA prior to making contact with the substrate, and subsequent epitaxial growth proceeds at this at a fixed temperature. The substrate can also be heated to above the saturation temperature in contact with an undersaturated melt in order to perform an in situ etch of the substrate surface. This etching step can aid in removing saw or polishing damage as well as creating a more uniform density of nucleation sites. The disadvantage of this melt-back procedure is that can adversely affect surface morphology through nonuniform etching. As previously stated, LPE is a close-toequilibrium growth process. If growth went completely to equilibrium, the amount of material deposited would just equal the amount of solid precipitated from the supersaturated melt to re-establish the solid-melt equilibrium at that temperature. This situation does not normally occur because diffusion in the melt is not

rapid enough to achieve equilibrium conditions throughout the melt volume. The growth rate is typically limited by diffusion of the supersaturated species through the melt to the substrate surface. A simple diffusion model can be developed in which the melt is assumed to be semi-infinite in height and isothermal with no convection cells. Growth is assumed to proceed by deposition only on the substrate and the growth rate is determined by diffusion of the solute (the low concentration component of the melt). In the case of GaAs growth, this would be diffusion of As in the G a melt to the GaAs substrate. The thickness of the epitaxial layer, d, that would be grown during time t is given for uniform cooling by

where R is the cooling rate, C i sis the concentration of the solute (As) in the solid, m is the slope of the liquidus curve which is assumed to be constant over the small temperature change associated with growth, D is the diffusivity and tis the growth time. For the step cooling case, the epitaxial layer thickness is given by (3-31) where AT is the temperature step (Casey and Panish, 1978). Growth rates for noninfinite melt heights as well as for ternary and quaternary materials have also been derived (Kuphal, 1991). Typical growth rates for LPE are around 1000A/min. While a variety of techniques have been developed to lower the growth rate and provide short exposure times to the melt, LPE cannot compete with MOVPE or MBE in the formation of extremely thin layers.

3.4 Liquid Phase Epitaxy (LPE) Technology

145

Figure 3-17. Planarization of a 4 pm deep groove by LPE growth of Al,Ga, - .As/GaAs/Al,Ga -,As layers [Kuphal, 19801.

One of the main characteristics of LPE is that it is a simple method to produce material with high purity and high optical efficiency. These positive material properties are derived directly from the growth method. LPE is performed under group 111-rich conditions, which results in a low density of group I11 vacancies. These vacancies have been attributed to non-radiative recombination centers which limit optical efficiency, carrier lifetime and diffusion length (Jordan et al., 1974; Ettenberg et al., 1976).High purity growth is aided by the fact that the melt tends to retain impurities by virtue of their small distribution coefficients. Pre-baking the Ga melt has also been shown to be very effective in reducing unintentional impurities and producing high purity GaAs (Amano et al., 1993).The impurity concentrations of S, Si and C in the melt have been reduced by Ga pre-baking. Oxygen is another deleterious impurity which forms a non-radiative deep level in a number of 111-V materials. If a small amount of A1 is incorporated in the melt, any oxygen present will preferentially form A1,0,, which will remain in the melt

and prevent oxygen incorporation in the crystal (Stringfellow, 1981). The growth rate realized in LPE is orientation-dependent, which can lead to enhanced edge growth as discussed above. This orientation dependent growth rate can also be utilized to great advantage in regrowth on patterned substrates. The main use for this is to produce buried heterostructure and distributed feedback or DFB lasers. Figure 3-17 illustrates LPE growth over a 4 pm deep groove (Kuphal, 1991). The initially grooved surface has been fully planarized by the LPE growth of a series of AlGaAs/GaAs/AlGaAs layers. The large difference in growth rates on the (001) and (111) faces, especially between InP and the InGaAsP quaternary compounds, has even permitted the growth, in one step, of buried heterostructure lasers on pre-patterned substrates. It is almost impossible to produce these kinds of structures using any of the other common epitaxial growth techniques. The difficulty in achieving a smooth planar surface morphology over large areas is a major problem in LPE. As a near-equi-

146

3 Epitaxial Growth

librium process, the surface mobility is large and subsequently the lateral growth rates are high. The surface morphology becomes, therefore, very sensitive to the substrate orientation, the nature and number of defects on the substrate and the conditions used for initial nucleation of the growth. The most common LPE morphological feature is a terrace or facet. If the substrate misorientation is large, extended terraces will form which make device fabrication difficult. Small misorientations, < O S ” , produce shorter terraces which have long treads, in the order of 100pm, with short risers in the order of several tens of nanometers. Using specific orientations, these terraces can be made large enough that devices such as lasers can be made completely on the terrace. It has been reported that extremely fine control of the growth temperature and substrate misorientation can be used to produce LPE layers without terraces (Rode et al., 1977). Heterostructure growth by LPE is complicated by the necessity of controlling the composition and diffusion of each species in the melt to achieve the desired composition. In some cases an effect called “lattice pulling” or “lattice latching” occurs which actually perturbs the solid composition of the growing layer to match the lattice constant of the substrate. The minimization of the total energy of the system, consisting of the strain energy combined with the thermodynamic driving force, leads to this shift from the predicted values. Lattice pulling actually makes it easier to produce latticematched heterostructures. This effect does not occur in MOVPE or MBE. Conversely, this effect makes it difficult to grow strained-layer structures, which require the ability to produce layers with specific lattice mismatches.

3.5 Molecular Beam Epitaxy (MBE) Technology Molecular beam epitaxy (MBE) is an ultra-high vacuum evaporation technique which is most commonly used for the deposition of single crystal semiconductors. It has been successfully used for the deposition of 111-V and 11-VI compound semiconductors as well as Si, Ge and related alloys. MBE has also been applied to the single crystal growth of a wide variety of metals and oxides. Like conventional thermal evaporative methods, it consists of a vacuum chamber with internal sources containing the materials to be evaporated. MBE systems are designed for extremely low pressures as well as very low outgassing rates. MBE is carried out under ultra-high vacuum (UHV) conditions. The UHV environment is required to maintain the purity of the growing film. In MBE, the growth rate is small, typically on the order of 1 pm/h. To achieve this growth rate, the source molecules must attach to the surface at about a rate of one monolayer of atoms per second. If all the atoms hitting the surface are incorporated, this impingement rate is equivalent to a vapor pressure of about IOv6 Torr. The residual gases in the vacuum chamber also impinge on the surface, react, and incorporate into the growing surface. The impurity content of the film is dependent, therefore, on the partial pressures of such unintentional impurit y containing gases in the chamber. The total background gas pressure in the chamber must be less than IO-’’ Torr to insure that the relative rate of arrival of impurities to growth nutrients is very low and the purity of the films is maintained at a high level. This high purity environment results in a number of unique characteristics. Among these features are the growth of high purity

3.5 Molecular Beam Epitaxy (MBE) Technology

material at temperatures lower than typically used in CVD, extremely fine control over the growth rate, and the ability to produce very abrupt interfaces, both for intentional dopants and major constituents. In addition, the high vacuum environment permits the use of in situ analytical tools, such as reflection high energy electron diffraction (RHEED) and Auger electron spectroscopy, which aid in monitoring the growth process. A principle advantage of MBE is its ability to utilize relatively low growth temperatures and slow growth rates. Lower growth temperatures result in reduced impurity incorporation from outgassing of hot system components, as well as reduced diffusion or redistribution of impurities and layer components within the device structure during growth. Slow growth rates ease control of film thickness and interface structure. Typical MBE growth temperatures and growth rates for GaAs are in the order of 600°C and 1 pm/h. The low growth temperature is made possible by the slow deposition rate. As discussed in Sec. 3-2, the slow growth rate gives impinging atoms sufficient time to diffuse across the substrate surface and to incorporate at their appropriate lattice sites. If the impinging flux rate becomes too high, the atoms will not have enough time to reach the proper sites and island growth will result. Island growth is undesirable because it can produce non-abrupt interfaces, loss of epitaxial relationship with the substrate and generation of a variety of defects. Defect generation can also result from a local non-stoichiometry, such as G a droplet formation, due to a local flux imbalance. The UHV environment of MBE determines the mode of mass transport in the growth chamber. Because of the low pressure, a large mean free path exists for the evaporated materials. The source materials

147

travel directly from the source to the substrate without scattering, forming a flux beam onto the sample. The beam nature of the flux allows the use of mechanical shutters to effectively interrupt this beam of evaporated species. The flux of nutrients at the growth front can therefore be very quickly and abruptly turned off or on. This fast switching of the sources, coupled with the slow growth rate, generates interfaces which approach atomic abruptness and layers that can approach single atomic layer dimension in thickness. As discussed above, since growth occurs at low temperatures, interdiffusion is often negligible between the layers during the growth process. A general schematic view of a MBE growth chamber is shown in Fig. 3-18. This chamber has three main parts: the vacuum system, the sources and the substrate holder. The vacuum system consists of the chambers, pumps, in situ monitoring equipment and transfer tools to move the substrates in and out of the system. The in situ monitoring tools include flux monitors on the sources and RHEED. RHEED is used during surface preparation prior to growth as well as for in situ calibration of growth rates. The growth sources, typically in elemental form are evaporated from effusion cells onto a single crystal substrate to form an epitaxial single crystal thin film. The flux of the impinging species at the substrate is controlled by the temperature of the individual effusion cells and the mechanical shutter position. The substrate is held in a heater stage, which is generally rotated to improve flux uniformity onto the growth surface. The MBE system is designed to achieve and sustain very low pressures. Base pressures approach Torr, while pressures during growth are about l o p 6Torr. A multi-stage load lock is used for efficient loading and unloading while minimizing

148

3 Epitaxial Growth

Growth chamber wall

Figure 3-18. Scheme of a typical MBE growth chamber.

RHEED screen

the possibility of introducing air into the growth chamber. As shown in Fig. 3-19, a system usually consists of a load-lock, a buffer chamber and the growth chamber. The vacuum chamber is typically made of stainless steel, and employs metal-sealed

fittings and valves for low leak and outgassing rates. In addition to achieving low pressures, the system must be able to generate appreciable fluxes of desired species with very little undesired impurities. All components of the MBE system must be

Growth chamber

Heater qtation Buffer chamber

Substrates load here

Figure 3-19. The main components of an MBE system include load lock, buffer and growth chambers.

3.5 Molecular Beam Epitaxy (MBE) Technology

designed to withstand baking at x 200 "C to enhance desorption of water vapor and oxygen from the internal chamber walls. A 'bake' of the growth chamber is undertaken when the internal surfaces of the system have been exposed to air during the occasional opening of the chamber for maintenance. Air exposure leads to adsorbed water which can be more effectively pumped from the chamber by heating or 'baking' of the chamber walls. The substrates are introduced into the system through the load lock. The load lock utilizes several stages of pumps to quickly achieve a relatively low pressure to lo-' Torr). These might include an adsorption pump followed by a cryogenic or ion pump. Load locks typically also permit low temperature (few hundred degrees) bake-out to desorb a large percentage of adsorbed water vapor from the substrate and holder. The substrate on which the film is to be deposited is attached to a carrier which can be transferred throughout the system. The substrate is attached to the holder using either an indium solder, or more commonly for whole wafers, a set of clips that greatly simplify loading and unloading. Smaller systems load one wafer at a time. Larger, production oriented systems utilize a trolley system to permit the loading or unloading of many substrates. Such wafer handling systems increase the throughput as well as minimize the number of exposures of the system to air. After the load lock is pumped out the substrates are transferred to the buffer chamber. The buffer chamber is the next higher stage of vacuum, typically pumped using an ion pump. The buffer chamber accommodates a higher temperature bakeout stage ( x500 "C) to further remove adsorbed impurities. It may also include some diagnostic equipment such as Auger

149

or RHEED analysis. After further pumping and baking in the buffer chamber, the substrate is introduced into the main growth chamber. This is done using a transfer tool which allows the substrate to be moved from one chamber to another without breaking vacuum. The growth chamber has a large cryogenic or ion pump in order to maintain the required vacuum level and partial pressures of residual gases during growth. These pumps are supplemented with large cryo-panels in the growth chamber which contain liquid nitrogen. The cold surfaces of the cryo-panels condense volatile gas phase impurities and greatly increase the pumping speed for species such as H,O and 0,. Water and other oxygen-containing species have an adverse effect on semiconductor properties, especially in Al-containing compounds. Cryo-panels are typically designed to surround the entire growth area, the source flange and the substrate holder. Excess growth species, such as As in the growth of GaAs, also condense on these panels, and thus are not completely pumped by the main pumping system. The source flange and effusion furnaces are also surrounded by cryo-panels which reduces cross-contamination and leakage of source material when the shutters are closed. The entire pump system ensures a very small partial pressure of unintentional species (H,O, O,, CO and CO,) in the growth chamber, with the result that very high purity materials can be deposited. The substrate, in its holder, is mounted on a heater stage in the growth chamber, It is typically heated by radiation from a filament source. The temperature is measured using a thermocouple behind the substrate as well as a pyrometer which controls the surface of the substrate. Typically an ion gauge is positioned opposite the substrate holder. This ion gauge can be rotated into

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3 Epitaxial Growth

the flux beam to measure the 'pressure' of the flux of each growth nutrient from the sources directly at the substrate position. One of the advantages of MBE over CVD is the availability of in situ surface analysis techniques mentioned above that may be used before and during growth. The most commonly used technique is RHEED. The two major uses of RHEED, within the MBE growth chamber, are (1) to establish the correct surface conditions prior to growth and (2) to perform in situ growth rate determination. The RHEED system, shown schematically in Fig. 3-18, consists of an electron gun producing an electron beam with energies in the range of 5-50 keV and a phosphor screen. The electron beam is incident on the substrate at a very shallow angle ( z1-2"). The electron beam forms a two-dimensional diffraction pattern after reflection from the surface atoms of the growing layer. This diffraction pattern contains information about the overall structure and atomic arrangement of atoms on the surface. The structure of the reconstructed surface can be deduced by examination of the diffraction pattern on the phosphor screen. The choice of the appropriate surface reconstruction during growth can influence the growth mode and uniformity as discussed in Sec. 3-2. The evaporation sources are contained in effusion cells which can very accurately and reproducibly maintain a specified temperature. This control is required because the flux from these cells is mainly determined by the cell temperature. These cells are often called Knudsen or k-cells because they originally approximated the geometrical and equilibrium conditions used in Knudsen's work on molecular effusion (Knudsen, 1909). In an ideal k-cell, the vapor pressure in the cell is assumed to be at equilibrium with the solid or liquid source and only a very small amount of the vapor

species escapes through an aperture in the cell. The aperture is small enough that the equilibrium condition is maintained with the cell. In this case, the flux of atoms J (atoms cm-'s-') which impinge on the substrate, a distance, 1, from the cell aperture, is given by J=

PAN x i 2 (2 x M R T ) ~ ' ~

(3-32)

where P is the pressure in the cell, A is the aperture area, N is Avogardro's number, M is the molecular weight, R is the gas constant and T (K) is the cell temperature. The tight temperature control required for the effusion cells arises from the strong temperature dependence of the vapor pressure of the source materials (3-33) The combination of Eqs. (3-32) and (3-33) leads to a dependence of the flux on temperature given by J cc

T - 1'2 ~ X [ P Qevap/(kB 771

(3-34)

The heat of vaporization for most metals, Qevap,such as Ga is approximately 3-4 eV/ atom. In the case of Ga at 950 "C, the vapor pressure is x 2 x Torr. Using typical values of A=0.78 cm2 and 1 = 20 cm, the Ga flux is x1.5 x 10j4 atoms cm-* s-'. This corresponds to about 0.24 unit cells of GaAs per second or a growth rate of 0.48 pm/h. A temperature variation of 1 "C for a Ga k-cell operated under these conditions would lead to a = 2% change in flux. For many structures this variation must be minimized, constraining the source heater to have a temperature stability of greater than 0.2 "C at these elevated temperatures. In actual systems, effusion cells differ greatly from an ideal Knudsen cell. These differences come about from the necessity of achieving a higher growth rate and improved uniformity over large areas. High

3.5 Molecular Beam Epitaxy (MBE) Technology

purity refractory materials such as Ta and pyrolytic boron nitride (PBN) are used in the k-cell to prevent contamination of the source and chamber. Much effort has gone into crucible design, the goal of which is to provide a large and controlled flux with a minimum heat load. In all cases, the k-cells are surrounded by the cryo-panel to minimize heating of the chamber by radiation from the glowing heater and sources. As an example, the cell apertures are much larger than in an ideal Knudsen cell. This is done to achieve acceptably high growth rates without excessively heating the k-cell. The evaporation of many low vapor pressure elements, such as Si, may require other forms of heating which allow greater temperatures to be achieved. Electron beam heating, where a small, high current, high energy electron beam is focused onto the source, is a common alternative. The k-cells are held in a source flange which properly orients each cell with respect to the substrate. A short cell-to-substrate distance and large cell aperture are desirable in order to provide a uniform flux and acceptable growth rate over a large substrate area. Gas source or metal-organic MBE (MOMBE) is a variant of MBE, which employs gaseous sources in addition to, as well as replacing, the typical solid sources. The addition of a gas injector allows the use of a wide variety of gaseous and liquid sources such as ASH,, PH,, trimethyl gallium, and so on. Alternate precursors may permit new growth modes and dopant species, as well as easing the control of certain growth species. An example of the latter is the growth of mixed 111-V arsenide/phosphide materials. Growth of these materials using solid P is very difiicult because of the high vapor pressure of P, resulting in high vacuum capability problems, and difficulty in controlling the As/P ratio in the solid. Replacing elemental sources of As and P

151

with ASH, and PH, has greatly improved the ability to grow these materials. Gas source systems have much higher gas loads and thus require high speed pumps such as cryo, turbo-molecular or diffusion pumping systems. Gas introduction is often performed through a high temperature ‘cracker’ cell. The purpose of the cracker cell is to decompose or crack apart the precursor before it impinges on the substrate. Both thermal and plasma cracking have been used successfully. This partial decomposition of the growth sources allows for, at times, lower growth temperatures and higher source utilization. An example of the utility of this approach is in the MBE growth of 11-VI compounds. 11-VI compounds have traditionaIIy been very difficult to dope p-type. Nitrogen is a suitable dopant element in many 11-VI semiconductors, however N, is very unreactive. An ECR plasma cracking cell for N, , generating atomic nitrogen, has resulted in greatly increased p-type doping efficiency and directly led to the demonstration of 11-VI lasers. MBE systems have become increasingly sophisticated in response to the need for increased control, reproducibility and throughput. Computer control of the entire system, including effusion cell temperatures, substrate heater, shutters and the entire pumping system is common. The necessity of producing graded composition and dopant profiles has led to control programs which can produce arbitrary temperature profiles for effusion cells and the substrate heater. The latest developments include the incorporation of direct monitoring and feedback from in situ measurements, such as ellipsometry or reflection electron diffraction, to control the growth process. MBE permits relatively quick realization of specific device structures. MBE is

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3 EDitaxial Growth

very effective for research projects as well as development and production where a large throughput is not required. Disadvantages of MBE include its high expense and relatively limited ability to grow on a large number of substrates simultaneously. Thus production of low cost devices, such as LEDs, or large area devices, such as solar cells, is better performed using other growth techniques such as CVD.

3.6 Specific Epitaxial Systems: Materials and Growth Issues The epitaxial growth of the common semiconductors has been accomplished by many techniques. The following section will focus on four individual systems currently being used in the semiconductor industry. The materials systems are chosen to highlight a particular growth technique. Silicon chemical vapor deposition is perhaps the most important semiconductor growth system. The analogous system for the growth of compound semiconductors is the metal-organic vapor phase epitaxy system which is discussed in the context of InP-based growth. InP is used in many opto-electronic devices. Liquid phase epitaxy has been replaced in many applications by the techniques of MOVPE and MBE. However, it remains a technologically important process in the growth of many high efficiency light-emitting structures in the Al,Ga, - .As/GaAs system. Finally molecular beam epitaxy is discussed in reference to the growth of GaAs.

3.6.1 Silicon Chemical Vapor Deposition Silicon epitaxy is used in many of the steps in the formation of integrated circuits. The particular form of Si epitaxy depends on the application of the materials

within a device context. Most Si epitaxy has been carried out in atmospheric pressure multi-wafer growth systems. These systems are capable of handling several wafers of large diameter ( 26” diameter). A major use of Si epitaxy is the formation of thick layers of controlled electrical properties on Si wafers at the beginning of the complementary MOSFET (CMOS) technology. The advent of advanced heterostructures in Si technology has been driven by new advances in the CVD growth technology. The growth of Si,Ge, -x\Si based material structures containing very thin layers of Si,Ge, - x grown on Si substrates has lead to an increase in performance of many traditional Si-based devices such as the bipolar transistor. The development of the ultra-high vacuum CVD of Si, referred to as UHV-CVD, has lead to the growth of Si structures at very low growth temperatures which minimizes interdiffusion between the grown layers. The reduced redistribution of impurities and materials preserves the grown-in heterointerfaces and impurity distributions allowing for the development of thin layer structures with abrupt interfaces. These two applications, thick Si layers and heterojunction formation, require different reactor designs and operating conditions, due to a difference in the underlying growth chemistry important to each process. 3.6.1.1 Silicon Chemical Vapor Deposition: Surface and Reactor Considerations

The growth of Si on large Si wafers is a processing technique used primarily at the beginning of the formation of integrated circuits. The reactors used in Si epitaxy are typically either barrel, single wafer, or the multi-wafer hot wall LPCVD tube reactors. The growth conditions employed in each of these systems is different. For each

3.6 Specific Epitaxial Systems: Materials and Growth Issues

of these reactors, the growth procedures have been optimized to yield a uniform, controlled film. The barrel reactor can hold typically 20-40 wafers on the susceptor. The wafers and graphite wafer holder are generally heated by RF induction or by banks of high intensity infrared lamps. The reactors typically run near ambient pressure using a chorine-based growth chemistry, such as SiCl, or SiCl,H,. These reactors can deposit at relatively high rates of xO.1 pm/min, when operated at high growth temperatures. The high growth temperatures, necessary for high growth rates, can lead to the interdiffusion or redistribution of impurities within the growing layers, often making abrupt doping junctions very dificult to achieve. The large thermal mass of these systems can lead to extended processing times at high temperatures. There are several considerations which have lead to the development of single wafer growth systems. The continued increase in wafer diameter has made many of the multi-wafer reactors impractically large. Simple scaling of the reactor size, based on wafer dimensions, has not been possible. In addition, many modern devices have a need for thinner device layers and minimized dopant redistribution. These device constraints only permit short times at high temperature to keep diffusion within acceptable limits. The use of a single wafer reactor allows rapid heating of the substrate through the use of infrared lamps. These systems are referred to as single wafer rapid thermal processing (RTP) based systems. While encountering many technological difficulties, such as uniform radiative heating and cooling of the wafer, these RTP systems can be easily integrated into an automated processing line since only a single wafer must be handled at a given time. In contrast, a barrel reactor

153

often requires operator-assisted loading and unloading of the wafers, leading to increased risk of breakage, contamination, and lost time. The newest form of reactor is the ultrahigh vacuum CVD or UHV-CVD system. This horizontal tube, multi-wafer system is a conventional LPCVD reactor which has been designed to operate at very low pressures. In addition, the reactor is constructed using similar technology to MBE systems to maintain a very low pressure, 5 lo-' Torr, while not in use. Wafer loads of 10-35 wafers or more can be used in a single growth run insuring a high wafer throughput. Wafers are loaded through a vacuum load lock which eliminates exposure of the internal surfaces of the reactor to air during loading and unloading. While insuring a high degree of cleanliness, the UHV-CVD system can produce high quality epitaxial films at temperatures lower than the other growth reactors through the use of lower growth rates. Growth in the UHV-CVD system takes place at a pressure of several micrometers ( % Torr). A hydride-based chemistry is used in this system: SiH, and GeH,. The growth temperatures employed in the UHV-CVD system are typically very low when compared to the growth of structures by the near atmospheric pressure growth reactors. Epitaxial growth of Si has been demonstrated at temperatures of 450-650 "C and at temperatures greater than 750°C. The intermediate growth temperature range (650-750 "C) typically leads to polycrystalline growth. The use of a particular system is dependent on a wide variety of concerns: device application, growth rate and thermal processing considerations, among others. There are common features of Si-CVD which come into play in the design of the operating conditions of the system. The limits to

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3 Epitaxial Growth

the range of operating conditions within the CVD reactor, for a given growth chemistry, are primarily dependent on the residual impurities within the growth system. These impurities, the most important being hydrocarbons and the oxygen-bearing compounds, such as H,O, lead to contamination of the growth front due to the high reactivity of the Si surface. The adsorption and incorporation of carbon and oxygen leads to a variety of deleterious effects, including the introduction of electrically active defects which can reduce device performance or yield a device inoperable. The adsorption of oxygen and carbon on the growth front additionally leads to morphological defects. Localized regions of oxidized Si prevent epitaxial growth from occurring often leading to no-growth regions. At lower oxygen coverages on the surface, the incorporated impurity can disrupt the transfer of the crystallographic information leading to the development of stacking faults and other defects. The tendency for Si to oxidize is very strong. The Si-0 or Si-C bonds readily form in preference to the Si-Si bond, with bond strengths of 191.1, 107.9, and 78.1 kcal/mol, respectively. In the case of oxygen, this strong bond indicates that the amount of H,O in the growth environment must be very small to prevent oxygen incorporation. The equilibrium amount of oxygen tolerated in the growth environment can be calculated through the use of equilibrium thermodynamics. Water and Si react to form SiO, according to the reaction Si+ZH,O o SiO,+ZH, (6) where the equilibrium coefficient is given by

In this expression, is the partial pressure in the system of a particular reactant and

AG,,, is the free energy of reaction. A similar calculation can be carried out for a variety of metal species as shown in Fig. 3-20 (Kuech et al., 1987). This figure indicates that at a growth temperature of 800°C, a H,O-to-H, ratio in the growth environment less than l o p 8is required. Within an atmospheric pressure reactor, this ratio indicates that a H,O concentration of less than 10 ppb is required in the inlet gas stream. The purification of the source gases is not complete enough to insure such high levels of gas purity. Water contamination in the reactor can also arise from adsorbed water on the components introduced into the reactor with the wafers, such as the wafer holders. This internal source of water can prevent the reactor gas phase composition from achieving such low levels of water content.

500

600

700

aoo

900

Temperature ?C)

Figure 3-20. The H,O-to-H, ratio determined by thermodynamic equilibrium considerations can be used to provide guidelines on the required purity of a growth system. Values of the H,O-to-H, above a given line can lead to the formation of an oxide.

3.6 Specific Epitaxial Systems: Materials and Growth Issues

The above argument is based on equilibrium considerations. At very low pressures and temperatures, these thermodynamic considerations do not adequately describe the growth environment due to kinetic limitations in achieving equilibrium. In such a case, the adsorption and incorporation of oxygen is limited by the kinetics of oxide formation and oxygen desorption from the growth front. Silicon can form other oxidebased compounds at high temperatures which also play a role in determining the surface concentration of adsorbed oxygen. In particular, the equilibrium between SiO, and 0, within the reactor can be shifted to favor an oxygen-free surface at very low pressures. SiO, and SiO, the high temperature monoxide, compete in the formation versus the removal of surface oxygen. These reactions reach a steady state with 0, and H,O in the reactor SiO, (solid)

SiO(g)+t O,(g) (7)

versus Si(solid)+2H20 +. Si0,+2H2 and Si(solid)+O,

SiO,

(8) (9)

A low partial pressure of H,O and 0, in the reactor favors the formation of the volatile SiO. There is a limiting partial pressure at a given temperature of these reactants, below which the surface remains oxide-free. The Si surface then remains free of O-based contaminants allowing epitaxial growth at a low growth temperature. Figure 3-21 indicates this limiting partial pressure of H,O for the growth in the absence of a H, carrier gas due to the evaporation of S i 0 from the growth front (Ghidini and Smith, 1984).At a growth temperature of 650°C, a partial pressure of H,O less than Torr is required. In the case of a CVD system operating at atmospheric

155

pressure, this partial pressure indicates the inlet gases must have a H,O concentration less than about 1 ppb. Even if the inlet gases were purified to such a level, the residual adsorbed H,O on the mechanical parts introduced into the reactor could provide this partial pressure. There have been APCVD systems which have successfully grown Si at reactor temperature less than 800 "C. These systems have been designed with load locks to minimize introduction of gases from the ambient from entering the reactor and very careful purification of gases at the point of use. There are several ways to reduce the impact of the oxide formation on the epitaxial growth of Si. The two primary techniques are the choice of growth chemistry and the use of a low reactor pressure. Si sources containing chlorine have been used to provide a chemical pathway to remove oxygen from the growth front. SiO, can be etched in aqueous solution by HF at room temperature. At high temperatures, other halogen containing compounds can effectively etch the Si surface. During the initial heating of the wafer, HC1 is often introduced into the reactor to etch the Si surface. Silicon, and to a lesser degree SiO,, are etched at high temperatures, such as IOOO'C, through the formation of SiCl, Si+4HC1

SiC1,+2H2

SiO2+4HCl o SiC1,+2H2O

(10)

(11)

These etching reactions can remove the initial, chemically prepared, surface of the Si wafer. The chemically prepared surface typically has, in addition to an oxide layer, adsorbed carbon, and other impurities. This in situ or within-the-reactor etch process removes these surface impurities leading to the preparation of a fresh, atomically clean surface for epitaxial growth. These high temperature etching procedures do

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3 Epitaxial Growth

lead to the redistribution of impurities, as would any high temperature process. In addition, the gas phase etching of Si sometimes preferentially occurs at defects within the Si layer. The HC1 etching process can decorate, through the preferential etching of material, the defect sites and result in a rough morphology of the growing surface. The use of chlorinated silanes during growth, i.e., SiCl,H,-,, allows any oxide which forms to be eliminated through a similar etching reaction. Reductions in the reactor pressure can also affect the range of epitaxial growth temperatures available. If the removal of oxygen from the Si growth front is limited by the formation and desorption of SiO, the reduction of the total reactor pressure insures that the partial pressures of H,O in the reactor is well below the limit required for surface oxide formation. A high purity gas flowing into a reactor at 0.01 Torr total pressure, for example, will have 100 ppb or less contaminants in it. The gas flow into the reactor will lead to a partial pressure of

10.8

impurities of z lo-' Torr. This results in a very low impingement and incorporation of impurities into the growing film. The equilibrium between SiO, and 0, within the reactor can be shifted to favor an oxygen-free surface, reducing SiO, through rapid desorption of SiO. According to Fig. 3-21, a reactor running at the pressure of 0.01 Torr and a typical level of carrier gas purity could possess an oxide-free surface for temperatures less than 600 "C. Much lower growth temperatures are achievable, in practice, using a UHV-CVD system. The advantage of an LPCVD system therefore stems from both the lessening of the mass transport limitations in the reactor as well as the production of epitaxial materials at a lower growth temperature.

3.6.1.2 Silicon Chemical Vapor Deposition: Growth Chemistry The growth chemistry used in the formation of epitaxial silicon has centered on

Oxidized Si Surface

_L \

109 6.0e-4

7.0e-4

8.0e-4

9.0e-4

inverse Temperature ( K ' )

1.Oe-3

1.1e-3

Figure 3-21. The evaporation of S i 0 from the growth front can lead to a clean Si surface. The balance between the oxide formation and oxide elimination represented in this figure can also determine guidelines for the purity requirements of a growth system with respect to oxygen and water.

3 . 6 Specific Epitaxial Systems: Materials and Growth Issues

157

100

10-1

10-2

't0 ,

the silanes, Si,H,,+ and chlorosilanes, SiCl,H,-, . The chlorosilanes have been generally used in higher pressure growth systems. The reduction of the oxygen incorporation during growth appears to be a key-advantage of these chlorinated growth sources. The chlorosilanes are very stable molecules with a range of free energies of formation as given in Table 3-2. The higher stability of the heavily chlorinated silanes increases the growth temperature required for deposition in the APCVD reactors. Figure 3-22 shows a comparison of growth rates for epitaxial Si grown using four Si precursors: SiCl,, SiH,Cl,, SiH,Cl, and SiH, (Bollen, 1978). The more highly chlorinated silanes lead to a reduced growth rate of Si under the same conditions. There are several other common features to the CVD of Si from this series of precursors. In each case, two temperature regimes of growth are noted in the figure. At low temperatures, the growth rate is strongly temperature dependent. This growth temperature dependence is attributed to the direct surface reaction of the Si precursor with the growth surface as being the rate-limiting step of the growth reaction. The greater stability of the Si source molecule results in a lower reactivity on the growth front with

Figure 3-22. A comparison of growth rates for epitaxial Si grown using four Si precursors, SiCl,, SiH,Cl,, SiH,Cl, and SiH,, indicates that the growth rate of Si from highly chlorinated sources is a function of the number of halogens on the source molecule.

a lower resulting growth rate. The specific surface reaction step responsible for the change in growth rate has not been determined. The suggested mechanisms for the limiting reaction step has been the desorption of hydrogen from the growth front or the surface decomposition of the chlorosilane. The desorption of hydrogen would make available additional surface sites for the adsorption of the Si-containing reactant. The surface coverage of hydrogen will be a function of the growth ambient and the wafer temperature. Higher growth temperatures lead to a reduced coverage of hydrogen on the surface leading to a potentially higher growth rate. An increased stability of the growth source can also lead to a reduced surface reactivity. Stable growth sources can desorb from the surface before they undergo a surface decomposition reaction. This desorption then eliminates the Si nutrient from the surface, again leading to a reduced growth rate. In practice, it is difficult to discern a particular mechanism and the actual growth chemistry is undoubtedly more complex than these simple suggestions imply. The other growth regime shown in Fig. 3-22, exhibits a weak or nearly temperature-independent growth regime. This

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3 Epitaxial Growth

weak temperature dependence is indicative of a mass transport limited growth behavior. In this case, the surface reactions are very fast and the gas phase concentration of the nutrient close to the surface is near zero. The surface reaction consumes all the available reactants as they reach the surface. The rate limiting step to the incorporation of Si into the growth front is then the transport of the growth reactant in the gas phase to the growth front. The growth rate would then have a temperature dependence characteristic of the gas phase diffusional transport. This diffusional transport has a power-law like dependence as discussed in Sec. 3-2. The transition between the surface reaction limited and the mass transport limited growth regimes occurs at increasingly high temperatures as the stability of the growth precursors increases. The choice of growth precursors therefore depends strongly on the required growth rates, the allowable thermal budget for the device being fabricated, and the background impurity levels in the inlet gas stream. The growth chemistry employed in the has been UHV-CVD of Si and Si,Ge, -, largely based on the hydrides of Si and Ge: SiH, and GeH,. The growth temperature range of UHV-CVD is determined by the kinetics of hydrogen adsorption. The wafer preparation, immediately prior to its introduction into the reactor, often includes a final oxide removal from the chemically prepared surface through the etching of the surface in an H F / H 2 0 solution. This HF/ H 2 0 oxide removal step can leave the surface H-terminated. The H-terminated surface has all available adsorption surface sites populated. The H-termination leaves the surface very inert since the oxygen and H 2 0 in the room ambient cannot adsorb and subsequently react to form a surface oxide. This treatment has a limited lifetime

since even at room temperature some hydrogen will eventually be displaced by oxygen. This pre-growth treatment introduces an oxide-free but hydrogen-terminated surface into the reactor. The wafer does not require additional etching provided the hydrogen passivation remains intact until growth. As the growth temperature is increased the hydrogen will desorb until at very high growth temperatures, greater than 750"C, there is little or no hydrogen adsorbed on the surface at steady state. The epitaxial growth of Si in UHV-CVD can take place under two very different growth temperature regimes. Epitaxial growth has been carried out at low temperatures, from SiH,, over the range 5 650 "C and at higher tem450°C 5 Tgrowth 2 750°C. This bistable peratures of Trow,,, growth temperature regime is directly related to the hydrogen-termination of the surface and the need to preserve an oxidefree surface during growth. At the low temperatures, the extrapolation of the data given in Fig. 3-20 indicates that the H 2 0 partial pressure in the reactor must be below IO-', Torr in order to maintain a clean surface. The inlet gases cannot be purified to the levels required to produce such an environment. Two factors within the UHV-CVD system assist in preventing the formation of the surface oxide and in maintaining a low H 2 0 content growth environment. The internal surfaces of the UHV-CVD reactor becomes coated with Si in the process of the Si growth. This internal surface coating of poly-crystalline Si provides a large reactive surface area for the reaction and removal from the gas stream of any oxygen containing species prior to its arrival on the wafer surface. The removal of impurities from the gas stream within the reactor is referred to as in situ gettering. The second factor which impedes the formation of

3.6 Specific Epitaxial Systems: Materials and Growth Issues

the oxide layer on the Si surface is the hydrogen passivation. Just as the hydrogen prevents surface oxidation in the environment external to the reactor, the hydrogen on the Si wafer prevents some of these oxidants in the growth environment from reacting with the growth surface through the lack of reactive adsorption sites. High growth temperatures enhance the removal of hydrogen from the growth front. However at the low temperatures, the surface of the growing film is replenished with hydrogen which is produced from the growth reaction. On such a surface, the reaction sequence would have the SiH, decomposing initially through the sequential elimination of hydrogen to the surface

SiH,(g) + 2 Sisurf=. SiH (ad) (1 2) + SiH, (ad)+ Si (solid)

SiH,(ad)+Sisurf=. SiH,(ad)+SiH(ad) (13) 2SiH,(ad)

SiH(ad)+H,(gas) (14)

2SiH(ad) =. Si(solid)+H,(gas) (15) where Sisurfis a Si surface site and the subscript ad refers to an adsorbed species. While this is a proposed mechanism, the primary implication of these reactions is that the hydrogen can be replenished to the surface provided a sufficient SiH, overpressure is maintained. In practice, a SiH, over-pressure is always provided over the wafer as it heats up in the reactor. This SiH, over-pressure insures that a SiH, molecule is available for adsorption onto the surface when a site becomes available due to hydrogen desorption. In the UHV-CVD process, the rate limiting step to Si epitaxial growth is the desorption of the hydrogen from the surface allowing for the subsequent adsorption and decomposition of the SiH, source. Since mass transport limitations are absent in this growth technique, the overall reaction

159

scheme is quite simple, based on the rate of desorption of H, from the growth surface, allowing additional SiH, to adsorb, and subsequent hydrogen removal from the SiH, to the growth surface. The epitaxial relationship is maintained through the lateral diffusion of the deposited Si atoms over the surface after SiH, decomposition on an appropriate Si surface site. The growth of the semiconductor alloy Si,Ge, - x utilizes the co-introduction of SiH, and GeH, into the reactor. The growth of the alloy system is complicated by the effect of Ge addition to the hydrogen desorption process. The Ge-H bond is much weaker than the Si-H bond (20 versus 38 kcal/mol). The presence of Ge on the growth surface, when growing Si,Ge, - x , leads to the enhanced desorption rate of hydrogen from the surface. Hydrogen attached to surface Ge is easily desorbed, again opening new adsorption sites. The SiH, and GeH, compete for these new surface adsorption sites. The GeH, is more efficient at adsorption and decomposition, leading to an enhancement of the Ge/Si ratio in the films over the gas phase ratio, shown in Fig. 3-23 (Meyerson et al., 1988). The rapid desorption of hydrogen from the Ge sites also leads to a non-linear growth rate with Ge composition in the solid as seen in Fig. 3-24 (Meyerson et al., 1988). If the ability to adsorb on the growth front were the same for both these sources, a constant growth rate would result. The chemical modification of the surface kinetics leads to an overall increased growth rate of the alloy system over Si with a comSi,Ge, -, plex growth behavior resulting from this surface chemistry. 3.6.1.3 Heterojunction Formation

The utility of the epitaxial growth of Si is not limited to the growth of epitaxial layers

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3 Epitaxial Growth

e e

Percent Ge in the Gas Phase

Figure 3-23. GeH, is more efficient than SiH, at adsorption and decomposition, leading to an enhancement of the Ge/Si ratio in the films over the gas phase ratio.

Figure 3-24. The rapid desorption of hydrogen from the Ge sites also leads to a nonlinear growth rate dependence on Ge composition in the solid.

with controlled electrical properties, as in a pn junction. The growth of the alloy semiconductor, Si,Ge,-., on Si allows for the development of many advanced device concepts which utilize the controlled compositional control across a heteroepitaxial interface as the composition is altered during growth. The change in composition must often be very abrupt, over a few nanometers, in order to effectively utilize the change in electronic structure in a device. The abruptness of the interface is directly related to the change in composition of the gas phase ambient out of which the film is growing. In the UHV-CVD growth system, the gas residence time in the reactor is very small. The residence time is defined as the volume of the reactor divided by the volumetric flow rate into the reactor. The UHVCVD systems have residence times of less than a tenth of a second under most growth conditions. The growth rate is very low in these systems, typically only a few nm/min. The short residence time insures that the

growth ambient can change within a fraction of a monolayer of growth. The resulting junctions are abrupt to about a single monolayer within the crystal. The final structure will, of course, be modified through thermal inter-diffusion. The residence time of gases in the APCVD system is not as low as in UHVCVD. This is because APCVD systems typically have larger volumes and lower volumetric flow rates. An additional complicating factor is recirculation within the gas phase environment of the reactor. If the gases within the reactor are susceptible to thermal convection, the convective rolls formed in the reactor act as a reservoir for the unused reactants and reaction by-products. While the simple calculation of the residence time may indicate that there is no difficulty in achieving abrupt junctions, these hydrodynamic effects can lead to the slow grading of the composition and a resulting poor heterointerface.

3.6 Specific Epitaxial Systems: Materials and Growth Issues

3.6.1.4 Impurity Incorporation

The controlled placement of impurities within the growing layer is required to define the electrical properties of the epitaxial thin layers comprising the device structure. The introduction of impurities during epitaxial CVD growth requires appropriate gas phase sources. In general, Si-CVD utilizes the hydrides of the impurity. The most common of these sources for Si doping are ASH,, PH,, and BZH6, These are conventient sources for Si doping since they are all gases at room temperature and can be easily handled. These gases, like SiH, and GeH,, are toxic and, in many cases, pyrophoric. The intentional incorporation of impurities requires their controlled introduction into the reactor. The rate of impurity incorporation depends on the nature of the dopant source, growth temperature and the growth surface. The dopant source is introduced into the reactor in a highly diluted form so that the ratio of dopant to growth source, e.g., PH,/SiH,, is very low. The solid concentration of the dopant will be very low, typically within the range of cm-,. The addition of these low levels of impurities can also alter the growth reaction itself due to surface interactions. The addition of PH, or ASH, during the growth of Si from SiH, leads to a dramatic decrease in the growth rate of the film (Farrow, 1974). These hydrides adsorb strongly on the Si surface and subsequently decompose slowly compared to SiH,. The strong impurity adsorption, combined with the low decomposition rates, leads to the accumulation of PH, on the Si surface. Many of the available surface sites are no longer available for SiH, adsorption and hence the growth rate drops significantly. The group I11 hydride, B2H6, can result in a very different reaction. Boron is the most

161

common acceptor in Si and Ge. In contrast to the case of ASH, and PH,, B,H, addition to the gas phase leads to an enhancement of the Si growth rate from SiH,. This effect is presently not well-understood. The presence of a p-type layer near at the growth front is believed to facilitate the desorption of H from the surface leading to the opening of new adsorption sites for the SiH,. As described above, the rate limiting step to the Si growth in many cases is the hydrogen desorption from the growth front. These chemical modifications to the growth front, through the addition of impurities, can alter the overall growth chemistry, despite their low inlet concentrations. The final impurity distribution in CVD systems will be affected by the same residence time considerations, considered above, as well as these additional chemical complications. The impurity profile generated during the growth of the multi-layer structures will be further modified by any thermal processing which will cause solidstate diffusion of the impurities. 3.6.2 GaAs MBE

GaAs is among the best characterized materials grown by MBE. While there are many variations for MBE growth of GaAs, by far the most common MBE technique utilizes elemental sources of Ga and As. These elements are held in effusion cells at temperatures required to achieve the necessary flux for growth. Ga cell temperatures of around 1000°C are required in order to produce an appreciable flux to the surface. The higher vapor pressure of As results in an As cell temperature of around 300-400 "C. Typical substrate growth temperatures are 600-700°C. The growth of GaAs under these conditions can be modeled using the following simplified assumptions: 1) the sticking coefficient of the

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3 Epitaxial Growth

group111 element (Ga) is unity; 2) only enough group V component (As) is incorporated to achieve stoichiometric GaAs; and 3) GaAs growth is almost always performed under As-rich conditions and the growth rate is controlled by the group I11 Ga incident flux. GaAs (and most compound semiconductors) do not evaporate congruently. In the case of GaAs, non-congruent evaporation implies that above z 650 “C, As evaporates preferentially from the crystal in the form of As,. At even higher temperatures, Ga will also begin to evaporate. Since these temperatures are within the typical growth temperature range, the substrate must be heated and cooled under an ‘over-pressure’ of As to avoid dissociation. The ‘over-pressure’ is provided by a flux of As species, typically As, or As,, onto the growth front. Since solid elemental As is most commonly used as the arsenic precursor, the predominant sublimed species is As,. In some systems this is further cracked at temperatures of x 900 “C to produce As,. When As, is the predominant species, the generally accepted growth model is that two chemisorbed As, species react with each other to produce GaAs and As, which is then desorbed. A simplified overall reaction is as follows: 4Ga+2As4

4GaAs+As,

(16)

When the As flux is greater than the Ga flux, there is a high probability that most adjacent sites will be populated with As, species. In this case, the growth rate will be limited by the flux of Ga to the surface, reacting with the adsorbed As,. However, if the As flux is similar to the Ga flux, the rate limiting step is determined by the probability of two As, species meeting and reacting. The model for GaAs growth from Ga and As, is less complex. The As, species is chemisorbed on the surface, in this

case, and reacts with surface- adsorbed G a to form GaAs. It is commonly stated that As, has a sticking coefficient close to 1 whereas As, has a maximum sticking coefficient of 0.5. It has been suggested that As, should then be a better, more efficient source of As for the growth of these compounds. ASH, is a less common As source in MBE. There are several attractions to the use of ASH,. Since ASH, is a gas, ASH, is supplied from a tank outside of the system, and the system does not have to be opened to replenish the As source as is necessary when reloading elemental As into an effusion cell. Another advantage of ASH, is that the flux can be accurately controlled using mass flow controllers which have a much faster time response than thermal effusion cells. Finally, ASH, may be dissociated using a high temperature cracker, leading to the possibility of choosing the incident As species. Disadvantages of ASH, include the added complexity of the pumping system and the large safety infrastructure required for the use of this toxic and hazardous gas. The elemental Ga metal used as a growth source is typically evaporated from an effusion furnace. These effusion sources do have complications. Ga or Ga-related oxide impurities from the cell may be ejected onto the substrate. This effect has been referred to as ‘Ga spitting’. The Ga droplets or oxides deposited have been related to pit and hillock type defects in the grown layer. Reduction of the density of these defects has been accomplished by careful attention to detail in preparing the Ga furnace to eliminate all impurities as well as modified effusion furnaces which have a hotter lip to prevent condensation of Ga at the end of the furnace. GaAs growth is usually performed on a GaAs substrate. These are typically

163

3.6 Specific Epitaxial Systems: Materials and Growth Issues

cleaned ex situ using a combination of solvents and acids. Recently so called “epiready” substrates have become available that eliminate the necessity of ex situ cleaning. After introduction to the system and outgassing in the buffer chamber, the substrates are heated prior to growth to desorb the native oxide. This is done in an As flux and the desorption temperature is ~ 6 0 0 ° CThe . RHEED system is used to determine when the oxide has been desorbed. As mentioned previously, GaAs growth is almost always performed in an As-rich ambient. Since the Ga sticking coefficient is about 1, if growth takes place in a Ga-rich ambient, the morphology degrades and eventually the growth becomes non-epitaxial. In the (001) orientation, GaAs consists of alternating layers of Ga and As. Depending on the As and Ga fluxes, an As- or Ga-stabilized surface can be obtained. However, the Ga-stabilized surface is difficult to maintain without morphology degradation. The surface reconstruction is determined using RHEED. The Asstabilized surface has a c(2 x 8) structure while the Ga-stabilized surface has a centered c(8 x 2) structure. Standard pregrowth treatment would consist of heating the substrate in an As flux, desorbing the oxide and obtaining an As-stabilized surface. The surface reconstruction during growth is determined by the As/Ga or V/III ratio. This is a very important parameter, affecting not only the structural but electrical and optical properties of the grown films. Typically growth is carried out with an As/Ga ratio about 1-2; i.e., a ratio that just results in an As-stabilized surface. While the As and Ga fluxes can be estimated from the beam equivalent pressures (BEPs), it is common to determine the desired conditions by examination of the

RHEED pattern and the properties of the grown films. High As/Ga ratios have been shown to result in increased densities of deep levels (Stall et al., 1980), and electron traps (Neave et al., 1980).This relationship is especially strong at low growth temperatures. Typical growth temperatures for GaAs are in the range of 600-650°C. While epitaxial films can be grown at much lower temperatures, the density of electrically and optically active defects strongly increases below about 600 “C. The growth temperature is also determined by the type of device being grown. Electrical devices are usually grown at lower temperatures than optical devices. The lower temperatures result in less impurity incorporation from hot system parts. Optical devices are grown at higher temperatures. The main reason for this is that the luminescence efficiency greatly increases with increasing growth temperature. Figure 3-25 (Cho, 1985a) shows a plot of PL

GaAs ACTIVE LAYERS d

0.15 - 0.2prn

450

500

550

600

650

SUBSTRATE TEMPERATURE

(‘c)

Figure 3-25. The photoluminescence intensity obtained from the GaAs active region in a double heterostructure or DH laser increases strongly with growth temperature. The arrows indicate the order in which the samples were grown.

164

3 Epitaxial Growth

intensity from GaAs active layers in a double heterostructure (DH) laser as a function of growth temperature. It is clear that the radiative efficiency strongly increases at higher growth temperatures. The high growth temperatures result in a reduction in the incorporation of oxygen, which acts as a deep level and a non-radiative recombination site. This increase in luminescence efficiency with increasing temperature is even stronger for A1,Ga -,As, where growth temperatures above 700°C are routinely used. However, high temperature growth is complicated by desorption of Ga from Al,Ga, -,As. At high tetmperatures, G a evaporates off the growing surface, resulting in a higher mole fraction of AlAs in the layer as well as a thinner layer. These effects are accounted for empirically and “calibrated out” in high temperature growth. A major advantage of MBE is the ability to determine the growth rate in situ using RHEED. This is done by observing the intensity oscillations in the specularly reflected RHEED spot from the As-stabilized (2 x 4) pattern. The intensity of this spot oscillates with a period that corresponds to one monolayer (Ga + As layer, z 2.83 A) of growth. The oscillations begin as soon as the Ga shutter is opened and stop when it is closed. The growth rate can then be determined by calculation of the period of the oscillations. This technique can also be applied to the growth of AlAs. The cause of the intensity oscillations is believed to be due to the growth mode, which results in a variation in the “smoothness’’ of the surface on a monolayer scale, (Neave et al., 1983). Figure 3-26 shows schematically a model for this type of growth model (Cho, 1985a). At the beginning of growth the surface is smooth and the electron beam is strongly reflected from the surface. Nucleation then begins to oc-

Figure 3-26. Growth of GaAs showing surface variations resulting in RHEED oscillations. 8 = O represents the initial or smooth surface. Fractional 0 values represent partial coverage of one monolayer.

cur at random locations across the surface. When the surface coverage 8 is about 50%, the surface has the most “roughness”, i.e., half the surface is one monolayer above the original surface, but in a random fashion. The reflectivity of this rough surface is at a relative minimum. As growth proceeds, the surface coverage increases and eventually a smooth surface is again achieved. Here,

3.6 Specific Epitaxial Systems: Materials and Growth Issues

like at the beginning, the reflectivity is at a relative maximum. If growth were to proceed in this mode, the reflections would be observed indefinitely.In most cases, the oscillations decrease in amplitude. This has been attributed to nucleation of a second layer on a lower layer that has not yet achieved 100% coverage. Unintentionally doped GaAs grown by MBE is typically p-type with carrier concentrations in the 1014 cm-3 range. Carbon has been identified as the dominant residual acceptor by PL and temperaturedependent Hall measurements. While not completely identified, the major suspected sources for C in the MBE system are residual hydrocarbon gases such as CO or CO, . Other residual impurities in unintentionally doped GaAs include silicon, manganese (from hot stainless steel), sulfur (from the As source), and oxygen (residual 0, and H2O). A great deal of effort has gone into increasing the purity of undoped GaAs. First, the growth chamber and sources must be of the highest purity. The growth chamber and all components must be thoroughly baked to desorb as much water as possible. Sources also must be outgassed at temperatures above where they will be used. Liquid nitrogen cryoshrouds (shown in Fig. 3-18) greatly reduce the residual partial pressure in the system, especially of H,O. Finally, for the highest purity, only the required cells should be kept hot and all ion gauges and ionization sources should be turned off to prevent decomposition of any residual gases. Modern MBE systems are designed to address most of these issues. However, the highest mobilities are only achieved through detailed and dedicated efforts - the highest 2DEG (twodimensional electron gas) mobility in GaAs/Al,Ga, -,As was achieved in a specialized dedicated system with high pump

165

speed cryo-pumps and an 8 week bake prior to growth (Pfeiffer et al., 1989). Many elements have been used for intentional doping of GaAs by MBE. Donors include silicon, tin, germanium and carbon. Acceptors include beryllium, magnesium, manganese, carbon, zinc and cadmium. Figure 3-27 (Cho, 1985b) shows the doping concentration of a number of donors and acceptors in GaAs as a function of effusion cell temperature. This figure indicates the wide range of carrier concentrations achievable for both donors and acceptors in GaAs. Silicon is typically the donor dopant of choice because of its well-behaved characteristics and small ionization energy ( x 5.8 meV below EJ. Silicon incorporation varies inversely with the growth rate and is relatively insensitive to the growth temperature. The highest electrical carrier concentrations grown with silicon are about IO1’ ~ m - ~ . . Tin has a similar ionization energy and maximum carrier concentration as silicon. However, tin incorporation is quite sensitive to the growth temperature and it tends to accumulate at the growing surface. However, tin has much less of a tendency to occupy both Ga and As sites (amphoteric nature) and no SnAs-related recombination peaks have been observed in the luminescence spectrum of tin-doped GaAs. For this reason, tin is often the preferred dopant for lasers. Germanium is not widely used, but is of interest because of its strong amphoteric nature (Kunzel et al., 1980; Heckingbottom and Davies, 1980). Depending on the As/Ga ratio and the substrate temperature, Ge can be an acceptor or donor. p-n junctions have been demonstrated using only Ge by changing from As- to Ga-stabilized growth conditions (Cho and Hayashi, 1971).

166

3 Epitaxial Growth TEMPERATURE ('C)

-a a

0 t I

J J w

5 W

a 0

0.700.75 0.80 0.85 0.90 0.95 1.0

1.05 1.10

Beryllium is the most common p-type dopant. Be forms a relatively shallow acceptor ( x 19 meV above E,,) and has wellbehaved incorporation characteristics. In ~ ) addition, very high (lo2' ~ m - carrier concentrations can be achieved. The major disadvantages of Be are its toxic and carcinogenic nature, the fact that it is very reactive with oxygen species and the inability to obtain Be in a purity comparable with other elemental sources. Magnesium is only incorporated eficiently at temperatures below about 500°C. It could be preferable for low temperature growth because it is less toxic than Be. Zn and Cd have vapor pressures too large to make them useful for MBE doping. Manganese produces a relatively deep acceptor ( ~ 9 meV 0 above E"), but has a number of complications in the growth such as surface accumulation and strong dependencies on growth conditions that make it almost impossible to use.

1.15 1.20 1.25

Figure 3-27. The doping concentration of several donor and acceptor elements in GaAs is a strong function of effusion cell temperature due to the exponential dependence of the elemental vapor pressure on the temperature (assuming unity sticking coefficient at the growth surface).

3.6.3 Growth of AlGaAs by LPE The actual practice of LPE can best be described in the context of the formation of a particular materials system. A wide variety of Al,Ga,-,As-based LED and laser devices have been grown by LPE. In this section we will discuss the growth and doping of AlGaAs by LPE. As discussed above, the starting point for LPE growth is the phase diagram. Figure 3-28 (Cassey and Panish, 1978) shows the phase diagram for the ternary compound Al,Ga, -,As. This diagram focuses on the liquidus and solidus lines; the details of the diagram near the As end are not shown here. The shaded area represents the ternary liquidus compositions that can be in equilibrium with the solid. The hatched area represents the solidus compositions. The binary solids GaAs and AlAs are fixed at the midpoints of the sides of the triangles between Ga and As and A1 and As. Figure 3-29 (Stringfel-

3.6 Specific Epitaxial Systems: Materials and Growth Issues

Figure 3-28. Liquidus and solidus phase diagram for A1,Ga1-,As which is used in the LPE growth of this material.

GaAs

AlAs

Figure 3-29. Pseudobinary section of the phase diagram, shown in Fig. 3-28, which indicates the solid composition in equilibrium with the liquid melt at a given temperature.

low, 1982) shows a section of this diagram cut parallel to the temperature axis and is sometimes called the pseudobinary section. This can be used to determine the composition of the solid that is in equilibrium with a given composition liquid at a specific temperature. This figure also shows that the composition in the solid is significantly higher than that in the liquid. This is demonstrated in more detail in Figs. 3-30 and 3-31 (Casey and Panish, 1978). Fig-

167

ure 3-30 shows the liquidus isotherms in the Al/Ga/As system while Fig. 3-31 depicts the solidus compositions in the solid as a function of the liquidus composition. These figures exhibit in more detail that the AlAs mole fraction in the solid is significantly larger than the A1 percentage in the liquid, and this ratio increases with decreasing growth temperature. The large difference between the mole fractions of A1 in the liquid and the solid leads to difficulties in composition control. Small errors in the amount of A1 in the melt will have a large impact on the AlAs mole fraction in the growing solid. Furthermore, the small amount of A1 in the melt can be rapidly depleted, which will lead to further compositional grading within the layer. Finally, any solution carry-over from an A1 containing melt to a non-A1 containing melt will cause significant unintentional A1 incorporation. As stated above, the phase diagram is the starting point for determining the growth parameters. As an example, we will determine the melt composition for the growth of Al,~,,Ga,,,,As at a growth temperature of 900°C. It should be noted that the solid composition and the growth temperature are all that are theoretically required, along with the phase diagram, to determine the melt composition. The atomic fraction of A1 in the melt X,, is determined to be 3 x l o p 3using Fig. 3-31. Figure 3-30 indicates that the atomic fraction of As in the liquid X,, is 5 x lo-' with x,,=I- XA,-XA, = 9.47 x lo-'. The atomic fractions of the melt constituents are then converted to weights using the formula

N, xi=3

crv,

j= 1

(3-36)

168

3 EDitaxial Growth L

.-da

Figure 3-30. Liquidus isotherms in the Al/Ga/As system as a function of temperature. O.OO0

0.002

0.004

0.006

0.008

0.010

0.012

0.016

0.014

A1 Atom Fraction in Liquid, X AI

0.9

0.8 e,

0.7

0.6

0.5

0.4 0.3

0.2

0.1 0.0 5

10-3

10-2

10-1

Figure 3-31. Solidus composition in the solid Al,Ga, -.As as a function of the liquidus composition.

AI Atom Fraction in the Liquid

determined using (3-38)

is the weight and M i is the atomic where W. weight of each component, the number of moles being K.= v . / M i . The Ga component makes up the bulk of the melt and hence determines the capacity of the system. In this example we use l o g of Ga which is NGa = 0.143. The respective number of moles of the other constituents are

and (3-39) We find from these equations that NA,=7.57 X and NA,=4.54X w4. The weights of As and A1 are determined,

3.6 Specific Epitaxial Systems: Materials and Growth Issues

using the molecular weights, to be WAS = MA,NA,=74.9

= 5.67 x

x 7.57 x lo-’

to-’ g

WA, = MAINA, = 27.0

= 1.23 x lo-’ g

(3-40) x 4.54 x

(3-41)

W,,=lOg Using this method, the composition of the melt can be determined to produce a specific solid composition of Al,Ga, -,As. It should be noted that as the A1 mole fraction X in the solid is increased, the mole fraction of As in the melt is decreased. Since the growth rate is limited by diffusion of As to the substrate, for a given supersaturation, the growth rate will decrease as the A1 mole fraction X in the solid is increased. This effect can become quite significant, a decrease of a factor of five in growth rate has been observed when X is increased from 0 to 0.8 (Wu and Su, 1989). Preparations for growth begin by loading the Ga into the boat. The system is then pumped and purged. The Ga melt is then outgassed to reduce its impurity concentration. Outgassing is performed for 1020 h in purified hydrogen at a temperature equal to or greater than the growth temperature. After outgassing, A1 and As are added. If the two-phase method is used, then GaAs would be added to the melt in the form of a substrate. As long as there is more than 5.67 x lo-’ g of As in GaAs (for the growth example given above), the solution will automatically come to equilibrium. Addition of these elements can be done by opening up the system, or in situ, using specially designed reactors, to prevent exposure to air and water vapor. The melt is then heated to slightly above the growth temperature for several hours allowing the melt to come to a state of equilibrium. Growth can then proceed using either ‘equilibrium’ or step cooling. Typical

169

growth temperatures for (A1,Ga)As are in the range of 80O0C, while typical cooling temperatures are in the range of several tenths to one degree per minute. Growth of AlGaAs is complicated compared to GaAs because A1 will oxidize if there is any oxygen present and form Al’O,. This forms a stable skin which floats to the top of the melt. However some Al,O, will be present at the substrate-melt interface; this interferes with the growth causing defects in the grown layer. The formation of Al,O, is reduced by removing all sources of oxygen. Careful preparation, outgassing of source materials, the use of purified hydrogen as carrier gas and techniques for in situ loading of A1 into the Ga melt have all been developed in order to produce high quality (A1,Ga)As. Special boat designs have been developed to separate the oxide floating on the top from the rest of the melt prior to growth (Lu et al., 1992). Unintentionally doped (A1,Ga)Asgrown by LPE is n-type. The impurities responsible for the n-type conduction are sulfur and silicon. Typical carrier concentrations for Al,Ga,-,As are in the low 10I6cm-3 range for OcxcO.35 (Wu and Su, 1989). There are other complicating factors associated with the heteroepitaxial growth of Al,Ga, -,As. Since Al,Ga, -,As is not typically grown on another Al,Ga, -,As layer of the same composition, it is important to understand the effect of growth on different compositions. It has been observed that in the growth of GaAs/Al,Ga, -,As quantum wells, the interface between the bottom Al,Ga, -,As barrier and the GaAs well can be made quite abrupt, whereas the interface between the GaAs well and the top Al,Ga, -,As barrier is much less abrupt (Chen et al., 1989). The reason for this is that the chemical potential for Al,Ga, -,As is lower than that of GaAs, in other words,

170

3 Epitaxial Growth

the effective saturation is less, and Ga etch melt-back will occur. Etching instead of growth initially takes place, therefore, when the Al-Ga-As melt is brought into contact with the GaAs well. In severe cases, the GaAs well can be locally etched away completely. This effect can be mitigated by using a different melt that has a higher supersaturation. The higher supersaturation effectively prevents melt-back, since a higher driving force for deposition is present, and results in an improved interface at the GaAs-to-Al,Ga, -,As junction. The last issue in LPE is the intentional incorporation of impurities. A wide range of elements have been investigated for donor and acceptor impurities in LPE grown A1,Ga -.As. Group I1 elements, such as Zn and Cd, are acceptors, while S,Se and Te are donors. Group IV elements Si,Ge and Sn are amphoteric. These elements can be incorporated on either the column I11 or column V sub-lattice resulting in either donor or acceptor behavior, respectively. The site dependence of the incorporation of these elements depends on the growth conditions, such as growth temperature and liquidus composition, as well as stoichiometry of the solid.

3.6.4 InP Metal Organic Vapor Phase Epitaxy (MOVPE) The growth of 111-V semiconductors is the most widespread application of the MOVPE technique. There are many features of the MOVPE growth process which are common to most of these materials systems. This section will look at the growth of InP as an example of this technique. The growth temperature dependence, influence of reactor chemistry, and the reactor pressure effects discussed in reference to InP growth will also be found in the growth of GaAs, A1,Ga -,As, and other technologi-

cally important materials. This section will present both the chemistry of InP growth and some of the growth related behavior connected with doping and other issues. The growth of InP and related compounds has progressed from research scale to production over the last decade, mainly driven by applications for light emitters in the 1.3-1.55 pm range for optical fibers. InP and related InGaAsP alloys have direct bandgaps and thus emit light very effciently. The presence of lattice-matched ternary and quaternary alloys and the ability of InP to produce high quality regrown layers has resulted in a very large number of laser structures, including buried heterostructures and ridge waveguides. Electronic applications include devices such as heterojunction bipolar transistor and modulation doped FETs. All of these devices utilize InP substrates and epi-layers in conjunction with ternary and quaternary layers of (In,Ga,Al)(As,P)to form the heterostructures. Two technologically important lattice-matched ternary compounds are In,~,,Ga,,,,As with a bandgap of 0.75 eV and Ino.52Alo,48As with a bandgap of 1.46 eV. Quaternary compounds utilizing InGaAsP, InGaAlP, etc., can provide lattice matched layers over a wide range of bandgaps. InGaAlP alloys have recently been used to produce extremely efficient light emitters in the yellow-orange color range. Trimethyl indium (TMI) and triethyl indium (TEI) are the main In precursors, while phosphine (PH,) is the major phosphorus source. Both 'TEI and TMI are stored in a bubbler, however, TEI is a liquid while TMI is a solid. The vapor pressure of TMI is also about 10 times higher than that of TEI. Much of the early MOVPE work on InP utilized TEI. InP grown using TEI and PH3 appeared to be more reproducible than TMI-based growth.

3.6 Specific Epitaxial Systems: Materials and Growth Issues

The delivery of a reactant from a bubbler containing a liquid is much more reproducible and stable than that from a solid. One problem with the use of TEI for the growth of InP results from its room temperature reaction with PH, creating an involatile adduct, removing reactant from the inlet gas stream and thus leading to poor growth uniformity. While lower reactor pressures suppress adduct formation, TMI has generally supplanted TEI for the growth of indium and phosphorous containing compounds. An advantage of TMI is its higher vapor pressure, which reduces the problem of condensation in the gas delivery lines. Tertiarybutylphosphine (TBP) has recently been developed as an alternate P source. TBP is much less hazardous than PH, since it is a liquid with a much lower vapor pressure than the compressed gas, PH,. TMI decomposes at temperatures in the range of 300-400 "C. The decomposition temperature is somewhat dependent on the ambient. In H, and D,, the pyrolysis reaction was found to be a hom*ogeneous gas phase reaction. The decomposition of TMI in D, results in the formation of CH,D and C,H, (Buchan et al., 1988).The carrier gas is found to participate in the decomposition process as seen in the formation of CH, from CH, and H, . The TMI decomposition process is however modified by

v 0 0

the presence of PH,. TEI has been less studied than TMI. A major feature of TEI is that its gas phase pyrolysis temperature is lower than TMI. Phosphine decomposes at substantially higher temperatures than TMI. In Fig. 3-32 (Buchan et al., 1987), curve (a) indicates of the PH,, by itself, in D, is that ~ 5 0 % decomposed at about 520 "C. However, the decomposition is strongly catalyzed by the presence of an InP surface, as shown in curves (b)-(d) obtained with increasing amounts of TMI added to the ambient. Several interesting features are seen in this figure. The pyrolysis temperature of PH, is greatly reduced by the addition of TMI. Additionally, the pyrolysis temperature of TMI is also lowered by about 50°C from that observed for TMI alone. Finally, the shape of the TMI+PH, reaction curves show that part of the PH, decomposes at a low temperature with the remainder still decomposing at the higher temperature, indicating that PH, can react with the TMI at very low temperatures. In contrast to the decomposition of TMI alone, TMI with PH, produces only CH, and no CH,D when decomposed in a D, ambient. The gas phase decomposition mechanism is therefore different for the TMI/PH, mixture than for the individual precursors alone. The proposed model for decomposition of this mixture postulates

15%/0%/85% 15 / 0 . 3 2 / 8 4 7 1.5/0.36/98.1 0.5 / 0 . 2 4 / 9 9 . 3

v -

200 250 300 350 460 4 5 0 500 550 600 650 700

Temperature

("CI

171

Figure 3-32. PH, pyrolysis as a function of temperature for PH, alone, and with increasing concentrations of TMI. The ratios of PH, :TMI are 41,4, and 2.

172

3 Epitaxial Growth

that the TMI and PH, react to form a gas phase complex or adduct which then decomposes through elimination of CH,. This reaction, in which only CH, is produced, does not require the participation of the carrier gas, D, (H,). The methane elimination process may occur in both the gas phase as well as on the substrate, generalizing the results from purely gas phase decomposition studies. TBP has been investigated as an alternative source to PH,. The two major reasons for desiring an alternate source are the relatively high decomposition temperature of PH, and its high hazard and toxicity levels. PH, is supplied as a gas in high pressure cylinders and has a threshold limit value (TLV) of 300 ppb. The high pressure storage of PH, gives rise to the potential hazard associated with PH,. TBP is supplied as a liquid with a vapor pressure of 266 Torr at 25 "C. Thus, although the TLV is similar to that of PH,, TBPs much lower vapor pressure greatly reduces the hazards involved in storage and use. Advances in the purification of TBP have permitted the growth of InP with purities rivaling those produced using PH,. InP is usually grown on (001) oriented InP substrates with a mis-cut of 3-5" towards a (011) direction. InP wafers are similar to GaAs substrates in their chemical and structural properties and are relatively fragile when compared to silicon. The use of vicinal substrates result in better morphology compared to exactly on-axis or no-miscut wafers. InP substrates are typically cleaned for growth using a polishing chemical etch. The purpose of this etch is to remove a thin surface region that contains residual polishing damage. The etch is usually composed of DI water, sulfuric acid and hydrogen peroxide. After rinsing in DI water and drying in clean N,, the substrate is loaded into the reactor.

As with GaAs, the group V element, P, is more volatile than the group 111 element, In, and thus InP substrates must be heated in an over-pressure of P to prevent the surface decomposition of the substrate prior to epitaxial growth. In MOVPE growth, PH, is added to the H, carrier gas at temperatures of 2 350 "C. This step also serves to desorb native oxides that have formed during the cleaning steps. If an As containing layer is to be grown on the InP substrate, an InP buffer layer may be grown first. An alternative to the PH,-based heatup process is to heat the InP substrate in ASH,. This will also prevent decomposition of the substrate and desorb surface oxides through the formation of a thin InAs surface layer. The growth of InP using TMI and PH, is typically performed using a H, carrier gas. Growth is performed in an over-pressure of the group V element P, with the growth rate controlled by the partial pressure of the column I11 element In. In practice, the growth rate of InP is found to be directly proportional to the flow of H, through the TMI bubbler and is independent of the PH, flow due to the large excess of group V source in the reactor. At atmospheric pressure, the growth rate is independent of the growth temperature from x550-7OO"C. Below z 550"C, the growth rate decreases, which is a result of a reduction in the decomposition rate of the precursors. Growth at atmospheric pressures uses relatively modest V/III ratios (30-50) compared to low pressure growth where the V/III ratio for good morphology and materials properties is in the range of several hundred. The photoluminescence response (PL intensity and peak FWHM) of undoped InP is also improved at high V/III ratios (Eguchi et al., 1988). A practical issue related to the use of TMI is stability of the flux of TMI from the

3.6 Specific Epitaxial Systems: Materials and Growth Issues

bubbler over time. As the TMI is depleted, it is believed to recrystallize (remember that TMI is a solid) and thus its surface area changes with time. The resulting TMI flux per unit of carrier gas through the bubbler tends to decrease over time as the bubbler is used. This often necessitates frequent calibration growths to be able to achieve desired compositions and growth rates. Several methods have been used to reduce this effect, including running the bubbler backwards, depositing the TMI on support material in the bubbler to increase the exposed solid surface area and running the bubbler at reduced pressures. Undoped InP is typically n-type asgrown. A great deal of work has been done to grow high purity InP layers by MOVPE. The major source of impurities in the InP is associated with the TMI source. Using highly purified TMI, mobilities as high as 264 000 cm2 V- s- have been achieved (Thrush et al., 1987). In these high purity layers, the main impurities are C, Si and S . At very high purity levels, the source of these impurities may not be the In and P precursors. In these cases, the actual impurity concentrations depend on the specific reactor and its materials of construction. For example, unintentional silicon incorporation may result from reduction of heated quartzware with the gas phase transport of Si into the growing layer (Briggs and Butler, 1987).The electron mobility is also a function of growth conditions. This growth procedure dependence is related to the particular source of the impurities. The highest mobility is achieved using lower growth temperatures and higher growth rates. These conditions minimize heating of the reactor components (one source of impurity precursors) as well as their concentration (large growth rate) in the grown solid. Since lower growth temperatures result in inefficient decompo-

' '

173

sition of PH, , very high V/III ratios ( > 150) are required to maintain acceptable morphology. The photoluminescence (PL) response of high purity InP is dominated by two peaks, one exciton related and the other acceptor related. The exciton peak dominates the spectrum as the growth temperature is increased. The acceptor peak has been associated with both carbon and zinc; however in higher purity material it is most likely carbon whose source is from the metal-organic In source TMI. Typically, higher growth temperatures also yield higher PL efficiencies of the exciton related peak. For example, increasing the growth temperature from 600 to 650°C results in a decrease in the FWHM of the band edge PL peak as well as an almost total elimination of the PL peak attributed to carbon (Chen et al., 1986). Intentional impurity introduction can also be accomplished in MOVPE growth. A wide variety of dopants have been investigated for InP, to produce n- and p-type material as well as semi-insulating (SI) InP. Donor impurities include silicon, sulfur, selenium, tin (Veuhoff et al., 1992) and tellurium (Clawson et al., 1987), while cadmium (Blaauw et al., 1987), magnesium and zinc have been investigated as acceptors. Iron and chromium have been reported to form SI InP. N-type doping is typically performed using silicon or sulfur. Si and S have different advantages which must be evaluated with respect to the requirements of the final device. Si has a lower diffusion coefficient and is able to produce somewhat more abrupt doping interfaces. However, S is able to produce higher free carrier concentrations and the mobility for equivalent dopant concentrations is typically higher using S. Thus, in the growth of modulation doped heterostructure devices, where abrupt doping and compositional

174

3 Epitaxial Growth

interfaces are of prime importance, silicon is the donor of choice. Where high doping and conductivities are required (for example, in lasers) S is the dopant of choice. Both silane and disilane have been used as precursors for silicon doping. The doping behavior of silane in InP is very similar to that in GaAs. The incorporation is proportional to the mole fraction of silane in the reactor, the reactor pressure and the growth temperature and inversely proportional to the growth rate. Quite high carrier concentrations using SiH, ( x 2 x 1019cm- 3, have been achieved; lower temperatures are found to produce the best morphology at these high carrier concentrations (Clawson and Hanson, 1994). Disilane also acts similarly in InP doping as in GaAs. The main advantage of disilane over silane is the lower pyrolysis temperature and consequent insensitivity to growth temperature. Silicon incorporation from disilane also increases with increasing PH, mole fraction (Rose et al., 1989). H,S is the precursor for S doping. Using H,S, the free carrier concentration is exponentially proportional to the mole fraction of H,S in the reactor. The incorporation of S decreases with decreasing reactor pressure (Moerman et al., 1991) and is also exponentially proportional to 1/T. P-type doping of InP has a more complicated growth behavior than n-type doping. The acceptor diffusion coefficients are typically concentration dependent, and dopant activation is affected by the reactor ambient during cool-down. The most common p-type dopants for InP are Zn and Mg. Zn doping is performed using diethyl zinc (DEZ). At atmospheric pressures, Zn incorporation from DEZ has a similar growth dependence to that of S using H,S. The Zn doping process is, however, much less efficient. Like H,S the incorporation of Zn is exponentially proportional to the

flow of H, through the DEZ bubbler and exponentially proportional to 1/T. At low pressures, the incorporation of Zn from DEZ is linear with the mole fraction of DEZ introduced into the reactor (Veuhoff et al., 1991). The temperature dependence of both of these elements is explained by their high vapor pressures. While a portion of the adsorbed Zn is incorporated into the growing crystal, a fraction of the surface adsorbed Zn evaporates and diffuses into the reactor ambient. This behavior leads to a dependence of dopant incorporation on growth rate. At high temperatures the dopant incorporation increases with growth rate. If the desorption of Zn is kinetically limited, the higher growth rates will trap more of the dopant into the growing layer. Similar to H,S, the incorporation of Zn decreases with decreasing reactor pressure. Lower reactor pressures lead to an enhanced mass transport of Zn from the growth front resulting in a reduced Zn incorporation rate. Mg, Cd and Be (Cole et al., 1991) have also been investigated as p-type dopants in InP. The incorporation of Mg, at low reactor pressures, is superlinear with mole fraction of bis-methyl cyclopentadienyl magnesium in the reactor and thus harder to control than DEZ. Maximum carrier concentrations achievable for both Zn and Mg are about 2 x lo1* ~ m - ~ . An interesting facet of acceptor doping in InP is the observation the acceptor activation is dependent on the gas ambient present in the reactor during cool-down. The acceptor impurities can become passivated with hydrogen during cool-down. The acceptors are still physically incorporated in the crystal, but they are not electrically active due to the co-introduction of hydrogen. Passivation is strongest for cooling in ambients which can produce atomic hydrogen at the growth front. Such hydrogen passivation arises from the surface-

3.8 References

catalyzed decomposition of the group V sources. Since ASH, is more readily decomposed than PH,, this passivation effect is strongest for cooling in ASH,, less for PH, and even less for cooling in H,. This effect is not observed for n-type InP. Semi-insulating InP has also been grown by MOVPE using iron (Franke et al., 1990) and chromium (Harlow et al., 1994). Resistivities of lo8 R cm have been achieved through the incorporation of both of these elements. Both Fe and Cr by themselves act as deep acceptors allowing for the compensation of n-type materials (Wolf et al., 1993).

3.7 Acknowledgement The authors would like to acknowledge the help of Prof. Max Lagally, Department of Materials Science and Engineering, University of Wisconsin, Madison, in the preparation of this chapter. He also provided the scanning tunneling micrographs.

3.8 References Adamson, A. W (1990), Physical Chemistry of Surfaces, 5th ed. New York: Wiley. Amano, T., Kond, S . , Nagai, H., Maruyama, S . (1993), Jpn. J. Appl. Phys. 32, 3692. Blaauw, C., Emmerstorfer, B., Springthorpe, A. J. (1987), J. Cryst. Growth 84, 431. Bollen, L. J. M. (1978), Acta Electron. 21, 185. Borg, R. J., Dienes, G. J. (1990), Introduction to Solid State Diffusion. San Diego, CA: Academic Press. Briggs, A. T. R., Butler, B. R. (1987), J. Cryst. Growth 85, 535. Buchan, N. I., Larsen, C. A,, Stringfellow, G. B. (1987), Appl. Phys. Lett. 51, 1024. Buchan, N. I., Larsen, C. A,, Stringfellow, G. B. (1988), J. Cryst. Growth 92, 591. Casey, H. C., Jr., Panish, M. B. (1978), Heterostructure Lasers, Part B. New York: Academic Press. Chen, C. H., Kitamura, M., Cohen, R. M., Stringfellow, G. B. (1986) Appl. Phys. Lett. 49, 963. Chen, J. A., Lee, J. H., Lee, S . C., Lin, H. H. (1989), J. Appl. Phys. 65, 4006.

175

Cho, A. Y. (1985a), in: The Technology andphysics of Molecular Beam Epitaxy: Parker, E. H. (Ed.). New York: Plenum Press. Cho, A. Y. (1985 b), in: The Technology and Physics of Molecular Beam Epitaxy: Parker, E. H. (Ed.). New York: Plenum Press, p. 6. Cho, A. Y., Hayashi, I. (1971),J. Appl. Phys. 42,4422. Clawson, A. R., Hanson, C. M. (1994), in: Proc. 6th Int. Conf. on InP and Related Materials, March 27-31, Santa Barbara, CA. Piscataway, NJ: IEEE, p. 114. Clawson, A. R., Vu, T. T., Elder, D. I. (1987), J. Cryst. Growth 83, 211. Cole, S . , Davis, L., Duncan, W. J., Marsh, E. M., Moss, R. H., Rothwell, W. J. M., Skevington, P. J., Spiller, G. D. T. (1991), J. Cryst. Growth 107, 254. Eguchi, K., Ohba, Y., Kushibe, M., Funamizu, M., Nakanishi, T. (1988), J. Cryst. Growrh 93, 88. Ettenberg, M., Olsen, G. H., Nuese, C. H. (1976), Appl. Phys. Lett. 29, 141. Farrow, R. F. C. (1974), J. Electrochem. SOC.121,899. Fitzgerald, E. A. (1991), Mater. Sci. Rep. 7, 87. Franke, D., Harde, P., Wolfram, P., Grotet, N. (1990), J. Cryst. Growth 100, 309. Ghidini, G., Smith, E W. (1984), J. Electrochem. SOC. f3f, 2924. Giess, E. A., Ghez, R. (1975), in: Epitaxial Growth, Part A : Matthews, J. W. (Ed.). New York: Academic Press. Harlow, M. J., Duncan, W. J., Lealman, I. E , Spurdens, P. C. (1994), in: Proc. 6th Int. Conf. on InP and Rel. Mater., March 27-31, Santa Barbara, CA. Piscataway, NJ: IEEE, p. 64. Heckingbottom, R., Davies, G. J. (1980), J. Cryst. Growth 50, 644. Hess, D., Jensen, K. E (1989), Microelectronics Processing, Adv. Chem., Vol. 221. Washington, DC: American Chemical Society. Jordan, A. S . , von Neida, A. R., Caruso, R., Kim, C. (1974), J. Electrochem. SOC.121, 153. Knudsen, M. (1909), Ann. Phys. (Leipzig) 4, 999. Kuech, T. E, Wolford, D. J., Veuhoff, E., Deline, V., Mooney, P. M., Potemski, R., Bradley, J. A. (1987), J. Appl. Phys. 62, 632. Kunzel, H., Fischer, A., Ploog, K. (1980), Appl. Phys. 22, 23. Kuphal, E. (1980), Appl. Phys. A 52, 380. Lu, Y. C., Bauser, E., Queisser, H. J. (1992), J. Cryst. Growth 121, 566. Meyerson, B. S . , Uram, K. J., LeGoues, E K. (1988), Appl. Phys. lett. 53, 2555. Middleman, S . , Yeckel, A. J. (1986), J. Electrochem. Sac. 133, 1951. Moerman, I., Coudenys, G., Demeester, P., Crawley, J. (1991), in: Proc. 3rd Int. Conf. on InP and Rel. Mater., April 8-11, Cardiff, U.K. Piscataway, NJ: IEEE, p. 412. Nayak, S . , Kuech, T. F., unpublished. Neave, J. H., Blood, P., Joyce, B. A. (1980), Appl. Phys. Lett. 36, 311.

176

3 Epitaxial Growth

Neave, J. H., Joyce, B. A., Dobson, P. J., Norton, N. (1983), Appl. Phys. A 3i, 1. Nelson, H. (1963), RCA Rev. 24, 603. I Cryst. . Growth Ouazzani, J., Rosenburger, E (1990), . 100, 545. Pfeiffer, L., West, K. W., Stormer, H. L., Baldwin, K. W. (1989), Appl. Phys. Lett. 55, 1888. Rode, D. L., Wagner, R. W., Schumaker, N. E. (1977), Appl. Phys. Lett. 30, 75. Rose, B., Kazmierski, C., Robein, D., Gao, Y (1989), J. Cryst. Growth 94, 762. Shea, J. B., You, B. T., Kao, J. Y., Deng, J. R., Chang, Y. S., Chen, T. P. (1993), J. Cryst. Growth 128, 533. Shewmon, P. (1989), Diffusion in Solids, 2nd ed. Warrendale, PA: TMS. Stall, R. A,, Wood, C. E. C., Kirchner, P. D., Eastman, L. E (1980), Electron. Leti. 16, 171. Stringfellow, G. B. (1981), J. Cryst. Growth 55, 42. Stringfellow, G. B. (1982), Rep. Prog. Phys. 45, 469. Thrush, E. J.. Cureton, C. G., Trigg, J. M., Stagg, J. P., Butler, B. R. (1987), Chemtronics 2, 62. Veuhoff, E., Baumeister, H., Reiger, J. Gorgel, M.. Treichler, R. (1991), in: Proc. 3rd Int. ConJ on InP and Rel. Mater., April 8-11, Cardiff, U.K. Piscataway, NJ: IEEE, p. 72. Veuhoff. E., Rieger, J., Baumeister, H., Treichler, R. (1992), in: 4th Int. ConJ on InP and Related Materials, April 21-24, Newport, CA, p. 44.

Vossen, J. L., Kern, W. (1991), Thin Film Processing II. San Diego, CA: Academic Press. Wolf, T., Zinke, T., Krost, A,, Bimberg, D. (1993), in: Sth Int. Conf. on InP and Related Materials, April 19-22, Paris, France, p. 707. Wu, M. C., Su, Y K. (1989), J. Cryst. Growih 96, 52.

General Reading Grovenor, C. R. (1989), Microelectronic Materials. Bristol, U.K.: Adam Hilger. Hess, D., Jensen, K. F. (1989), Microelectronics Processing. Washington, DC: American Chemical Society. Hurle, D. T. J. (Ed.) (1995), Handbook of Crystal Growth, Vol. 3. Amsterdam: Elsevier. Lee, H. (1990), Fundamentals of Microelectronics Processing. New York: McGraw-Hill. Massel, L. I., Gland, R. (3970), Handbook of Thin Film Technology. New York: McGraw-Hill. Muraka, S. P., Peckerar, M. C. (1989), Electronic Materials: Science and Technology. San Diego, CA: Academic. Vossen, J. L., Kern, W. (1991), Thin Film Processes II. San Diego, CA: Academic.

4 Photolithography Rainer Leuschner Infineon Technology. Memory Products. Erlangen. Germany

Georg Pawlowski Clariant Japan K . K., BU Electronic Materials. Shizuoka. Japan

List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 179 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 4.2 Exposure Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 4.2.1 Image Formation and Resolution . . . . . . . . . . . . . . . . . . . . . . . 184 186 4.2.2 Contact and Proximity Printing . . . . . . . . . . . . . . . . . . . . . . . . 186 4.2.2.1 Optical Mask Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2.2 X-Ray Stepper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 4.2.3 Projection Printing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.2.3.1 Near UV Projection Systems . . . . . . . . . . . . . . . . . . . . . . . . . 189 4.2.3.2 Deep UV Projection Systems . . . . . . . . . . . . . . . . . . . . . . . . . 190 4.2.3.3 Nonconventional UV Lithography . . . . . . . . . . . . . . . . . . . . . . 191 4.2.4 Post-Optical Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 4.3 Photoresist Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 4.3.1 Quality Control and Resist Deposition . . . . . . . . . . . . . . . . . . . . 195 4.3.1.1 Purity and Storage Stability . . . . . . . . . . . . . . . . . . . . . . . . . 195 4.3.1.2 Resist Coating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 4.3.2 Resist Exposure and Development . . . . . . . . . . . . . . . . . . . . . . 197 4.3.2.1 Characteristic Curve and Standing Wave Effects . . . . . . . . . . . . . . . 197 4.3.2.2 Process Latitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 4.3.2.3 Dissolution Rate and Development Methods . . . . . . . . . . . . . . . . . 199 4.3.3 Pattern Inspection and Resist Profile Simulation . . . . . . . . . . . . . . . 201 4.3.4 Etching, Resist Stripping and Planarization Concepts . . . . . . . . . . . . 201 4.4 Photoresists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 4.4.1 Principles of Photoresist Chemistry . . . . . . . . . . . . . . . . . . . . . 203 4.4.2 Negative-Tone Resists . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 4.4.2.1 Photocrosslinking via Azides . . . . . . . . . . . . . . . . . . . . . . . . . 204 4.4.2.2 Free-Radical-Initiated Polymerization . . . . . . . . . . . . . . . . . . . . 205 4.4.2.3 Acid-Catalyzed Crosslinking . . . . . . . . . . . . . . . . . . . . . . . . . 206 4.4.3 Positive-Tone Resists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 4.4.3.1 Dissolution Inhibition/Dissolution Promotion . . . . . . . . . . . . . . . . 214 4.4.3.2 Acid-Catalyzed Deblocking . . . . . . . . . . . . . . . . . . . . . . . . . 221 4.4.3.3 Polymer Degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

178

4.4.4 4.5 4.5.1 4.5.1.1 4.5.1.2 4.5.2 4.5.2.1 4.5.2.2 4.5.3 4.5.3.1 4.5.3.2 4.5.4 4.5.4.1 4.5.4.2 4.6 4.7

4 Photolithography

Solvents for Photoresists and Main Resist Suppliers . . . . . . . . . . . . . 233 Special Photoresist Techniques . . . . . . . . . . . . . . . . . . . . . . . 234 Nonconventional Diazo Resist Processes . . . . . . . . . . . . . . . . . . . 234 Resist Profile Modification and Image Reversal . . . . . . . . . . . . . . . 234 Bilayer Systems for Contrast Enhancement . . . . . . . . . . . . . . . . . 236 Suppression of Reflections and Standing Wave Effects . . . . . . . . . . . 237 Dyed Resists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Antireflective Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 240 Silicon-Containing Multilayer Resists . . . . . . . . . . . . . . . . . . . . 241 Negative-Tone Silicon Bilayer Resists . . . . . . . . . . . . . . . . . . . . Positive-Tone Silicon Bilayer Resists . . . . . . . . . . . . . . . . . . . . 242 Top Surface Imaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Gas Phase Silylation Systems . . . . . . . . . . . . . . . . . . . . . . . . 245 Liquid Phase Silylation Systems . . . . . . . . . . . . . . . . . . . . . . . 246 Trends in Photolithography . . . . . . . . . . . . . . . . . . . . . . . . . 252 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

List of Symbols and Abbreviations

List of Symbols and Abbreviations CD DR DOF D;, Do, Ea FT G k l , k2

n NA 0. N. r R

S TG

critical dimension dissolution rate depth of focus dose to clear activation energy film thickness of resist proximity gap constants refractive index numerical aperture Ohnishi number ring parameter reflectivity swing ratio glass transition temperature

resist absorptivity resist contrast extinction coefficient angle wavelength

AAS ABC AFM AHR ALC APSQ ARC ARCH ASIC BARC BCB BDMADS CA CAR CARL CEL CMP coo CQUEST DESIRE DNQ

atomic absorption spectroscopy (azidobenza1)cyclohexanones atomic force microscope acid-hardening resist acid labile compound acetylated phenylsilsesquioxane antireflective coating advanced resist chemical amplified application specific integrated circuit bottom antireflective coating benzocyclobutane bis(dimethy1amino)dimethylsilane chemical amplification chemical amplified resist chemical amplification of resist lines contrast enhancement layer chemical-mechanical polishing cost of ownership Canon quadrupole efficient stepper technology diffusion enhanced silylating resist diazo-naphthoquinone

Y E

179

180

DPI DR DRAM DUV EBL ECR EVE excimer FFP FIB-CVD FLEX HAE HELIOS heptaMDS HMCTS HMDS HMMM HX IBL IC ICA ICP-MS ICP-OES IPL KTFR LAE LIGA LSI MAE MCM MEMS MIE MIF MLR MOSFET MSNR MTF NBSE NTRS NUV 0,-RIE OPC OPTIMA OSPR PAC

4 Photolithography

diphenyl iodinium dissolution rates dynamic random access memory deep ultraviolet (300- 100 nm) electron beam lithography electron cyclotron resonance ethylvinylether excited dimer film-forming polymer focused ion beam chemical vapor deposition focus latitude enhancement exposure high activation energy high energy lithography illumination by Oxford’s synchroton heptamethyldisilazane hexamethylc yclotrisilazane hexamethy ldisilazane hexamethoxymethyl melamine hydrogen halogen ion beam lithography integrated circuit indene carboxylic acid inductively coupled plasma mass spectroscopy inductively coupled plasma optical emission spectroscopy ion projection lithography Kodak’s thin film resist low activation energy Lithographie, Galvanoumformung, Abformung large scale integration medium activation energy multichip modulus microelectronic mechanical system magneton enhanced ion etcher metal-ion-free mu1t i -layer resist metal-oxide-silicon field effect transistor methacrylated silicon-based negative resist modulation transfer function nitrobenzyl sulfonate ester National Technology Roadmap for Semiconductors near-ul traviolet oxygen reactive ion etching optical proximity correction outline pattern transfer imaging organosilicon positive resist photoactive compound

List of Symbols and Abbreviations

PAG PBOCMOST PBOCST PBOST PCM PCVD PEB PHS PI PMGI PMIPK PMMA PROMOTE PSMT PTMS RBS RIE SABRE SAFE SAHR SCALPEL SEM SHRINC SIA SIMS SLR SNR SRAM SUCCESS TARC t-BOC TFT/LCD THP TMAH TMMGU TMSDEA TPS TSI ULSI

VHSI XL XRL

photoacid generator poly -(t-butoxycarbonyl-methoxystyrene) poly-(t-butoxycarbonyl-oxystyrene) poly -(t-butoxy styrene) portable conformable mask plasma chemical vapor deposition post exposure bake polyhydroxystyrene photo initiator poly(methy1 glutarimide) poly(methy1 isoprophenyl ketone) poly(methylmethacry1ate) profile modification technique phase shifting mask technology pyrogallol trismethyl sulfonate Rutherford backscattering spectroscopy reactive ion etching silicon added bilayer resist scanning tunneling microscope aligned field emission silylated acid hardening resist scattering with angular limitation projection electron beam lithography scanning electron microscope super high resolution illuminating control Semiconductor Industry Association secondary ion mass spectrometry single layer resist silicon-based negative resist static random access memory sulfonium compound containing expellable sophisticated side groups top antireflective coating tertiary butyloxycarbonyl thin film transistor/liquid-crystal display tetrah y dropyran tetrameth y lammoniumhydroxide tetramethoxy methyl glycoluril trimethylsily ldiethy lamine triphenyl sulfonium top surface imaging ultra large scale integration ultraviolet very high speed integration crosslinker X-ray lithography

181

182

4 Photolithography

4.1 Introduction The definition of the numerous electrical functions assembled on integrated circuits (ICs) is usually accomplished with the aid of an illumination-based imaging technique called photolithography. Photolithography provides a method to transform a complex master image with radiation into thousands of three-dimensional replicas of a photoresist film coated onto a substrate with utmost accuracy, speed and cost efficiency. The real or digitized master image is provided by either a mask or a serial writing technique. Being stroked by the radiation, the exposed photoresist areas change their solubility or polarity properties. The material’s chemistry selection and its processing conditions determine the tonality of the relief image: If the reproduction corresponds to the original, it is termed a positive; if it is reversed. it is a negative reproduction. The discrimination between image and nonimage areas is accomplished by selective removal of either the exposed (positive) or unexposed (negative) resist through a development method (Fig. 4- l ) , resulting in the desired three-dimensional relief image. The remaining photoresist portions protect the underlying substrate from the attack of processing chemicals, e.g., etching agents, and allow the whole device to be subjected to the undifferentiated action of these. Photolithography has become an inevitable element in the manufacturing sequence of microelectronic circuits and other devices, such as multi-chip modules (MCMs) (La11 and Bhagath, 1993), micromechanical devices (Rogner et al., 1992), thin film recording heads for magnetic disks (Bond, 1993), color filters (Kudo et al., 1996a, b), or thin film transistorAiquid-crystal displays (TFT/LCD) (Howard, 1992; Bardsley, 1998). Many of these products are integral parts of the hardware platform mandatory

for an effective handling of the growing information density worldwide. The base material for the production of an integrated circuit consists of an intensively cleaned, highly polished disk, called a wafer, with a diameter up to 300 mm (Brunkhorst and Sloat, 1998; Bullis and O’Mara, 1993), which has been sliced from a large monocrystalline silicon rod of extreme purity. Each wafer provides hundreds of small separate chips, containing millions of electrical elements, such as capacitors, diodes, and transistors on a field size of 1 to 2 cm2. During its metamorphosis from apolished silicon plate to disk carrying ICs, the wafer is subjected to many different operations. Certain key steps are used repeatedly in IC fabrication, among which lithography plays a dominant role to delineate the patterns of conducting and insulating areas (Einspruch, 1985).

Figure 4-1. Formation of positive and negative tone pattern.

4 . 1 Introduction

Initially, the wafer is thermally oxidized at 1000°C. During this step a thin layer of silicon dioxide grows on the silicon substrate. This SO,-layer will protect selected areas of the substrate from penetration by dopant ions. The wafer is spin-coated with a solution of the photoresist, which solidifies to a uniform 0.5 to 2 mm thick film after the solvent is evaporated on a hot-plate at elevated temperature. The coated wafer is then imagewise irradiated and the soluble resist portions are removed by a development procedure. Next, the SO,-layer, which is imagewise protected by the resist, is etched away where it is uncovered to open the desired portions of the silicon surface. At this point, the resist is removed (stripped) to avoid device contamination with resist impurities. The wafer is now ready for a further key processing step: ion implantation, which gives the silicon its electrical properties. High-energy ions of dopant elements (boron, phosphorus) are fired at the wafer and penetrate the open areas of the silicon surface. The substrate surface is reoxidized,

183

and the wafer is again coated with a photoresist to allow further processing, e.g. insulation, or metallization steps. In a final lithographic step, contacts and connections for pins used to plug the chip into a printed circuit board are defined. At present, up to 24 lithographic and more than 250 separate processing steps are employed for the manufacture of electronic devices, resulting in a production time of one month for a single chip (Bullis and O’Mara, 1993). A simplified IC manufacturing procedure is given in Fig. 4-2. An ongoing challenge in IC production is to further shrink the lateral device geometry, with the aim of building even more complex circuits, e.g. dynamic random access memory (DRAM) devices with higher storage capacity. This demand for higher resolution is the driving force for steady improvement of the photolithographic process (Gargini et al., 1998). Figure 4-3 illustrates the developments of storage capacity and required feature size for memory devices (left), and summarizes the applied or required technologies and photoresist characteristics to produce the devices (right).

Figure 4-2. Planar technology: simplified production steps in MOSFET manufacture.

184

4 Photolithography

Technology: UV-broadband contact & proximity printer Chemistry: Azido I isoprene resists Tonality: Negative, single layer Pros: High sensitivity, good adhesion, low cost Cons: Swelling, resolution > 2.0 pm

1 256 kBit DRAM

Technology: g-line 8 i-line (436 & 365 nm) stepper Chemistry: DNQ I novolak resists Tonality: Positive, single layer Pros: High resolution, wide process laditudes Cons: Low sensitivity invariable chromophore

16 MBit DRAM

Technology: DUV (248 & 193 nm) exumer stepper & scanner (*beam, x-ray systems, IPL 7) Chemistry: Chemically amplified resists Tonality Positivelnegative, single (multi) layer Pros: High resolution, high sensitivity, adjustment to any wavelength Cons: Process sensitivity, high investment costs

16 GB1 DRAM

1970

1980 1990 2000 2010 Availability for production [year]

Figure 4-3. Development of storage capacity and minimum feature size of memory devices (left) and technologies utable for memory debice production

4.2 Exposure Tools 4.2.1 Image Formation and Resolution

ICs are usually patterned with near UV radiation sources, e.g. mercuryhare gas discharge lamps. To achieve optimum resolution. the emitted light is filtered and corrected by filter and lens systems to yield narrow-banded radiation. Contact, proximity or projection exposure tools (Fig. 4-4) have found commercial use, each having certain advantages, and handicaps over the other (Soane and Martynenko, 1989).The history of the different lithographic exposure tools is outlined by Bruning (1997). In an optical lithographical system, light passes through the transparent areas of the mask. In the photoresist, the basic phenomenon to be seen is Fresnel diffraction. Figure 4-5 compares the aerial images of the above-described exposure methods. Con-

tact printing readily approaches a perfect pattern transfer. But, with growing distance between mask and wafer (proximity printing), interference patterns occur, ending in an aerial image with a smooth distribution of the light intensity with its peak in the centre of the slit and tails beyond the area defined by the mask. When adjacent slits are projected, the situation becomes more complex, as a series of undulating maxima and minima are observed, with maxima smaller than 100% and minima greater than 0% transmission. The minimal printable linewidth CD (critical dimension) is given by the wavelength A, the proximity gap G and the resist film thickness FT [Thompson et al., 1983; Eq. (4-1)]: CD = 312 VA(G + FTl2j

(4-1)

In projection printing the special frequencies of the diffraction pattern are collected

4.2 Exposure Tools

185

by the objective lens, which rebuilds the areal image of the mask in the wafer plane. For an ideal lens, the image quality is only restricted by the diffracted light that it does not pass through the lens due to the limited size of the numerical aperture (NA). The NA of a lens system in air is defined in Eq. (4-2), with 8 denoting the maximum angle of the diffracted light that can enter the lens (Mack, 1993a):

NA = sin (8/2)

Figure 4-4. MasWdie arrangement in (a) contact, (b) proximity and (c) projection printing.

(4-2)

A rough estimation of the limits of projection printing can be given by the Rayleigh [Eq. (4-3)]. The resolution (= critical dimension, CD) is a function of the radiation wavelength A,the NA and an empirically determined constant k~ which is governed by the type of photoresist, substrate, and the 9

Relative intensity

100

Figure 4-5. Comparison of aerial images obtained by contact, proximity and projection printing. (Reproduced after Soane, 1989.)

186

4 Photolithography

process environment (Lin, 1990). Under laboratory conditions, k l is assumed to be 20.5, whereas under production conditions, k , typically has a value of > 0.8 to > 1.2 depending on the reflectivity of the substrate.

C D = kl AJNA '

(4-3)

At a fixed wavelength, a larger NA allows the reproduction of smaller patterns. As seen from inspection of Eq. (4-4), the penalty for obtaining higher resolution by increasing the NA is a smaller depth-of-focus (DOF). The empirical constant k , in Eq. (4-4) also depends on the type of materials used.

DOF = k2 . AJ(NA)'

0.2

0.3

0.4

0.5

0.6

0.7

Numericol operture

'200 /

---

I _ T -I-----

----

I000

436 n m 365nm 248 nm

(4-4) t

Values for k , are in the range of 0.4 to 0.9 under laboratory and production conditions. Studies by Dammel et al. (1990) and Boettiger et al. (1994) revealed that Eq. (4-4) is only roughly valid in the sub-half-micron range, and larger focus budgets than predicted may be observed in reality. From Eq. (4-3) it is obvious that a decrease of A, also will result in improved resolution capability, which thus may be obtained by either using NUV radiation with a high N A system, or by deep UV radiation with a smaller N A . A shorter wavelength A, should yield a better focus budget at a defined resolution but with shrinking feature size it cannot totally compensate the corresponding DOF reduction as shown in Fig. 4-6 (Arden, 1990). The DOF problem is a major physical limitation for single layer resists i n optical submicron lithography, as a minimum resist thickness of >0.35 pm is necessary to ensure both coverage of the topography and sufficient etch resistance. The considerations mentioned above are basedon the assumption that the light strikes the mask only from one direction (coherent illumination). In reality, it comes from a

CI 3

600

400 200

*/ 5

+/4

+/-I

D r p t n of focus [ p m ]

Figure 4-6. The impact of re

range of angles rather than just one (partial coherence). The impact on the resolution is expressed by the modulation transfer function (MTF), which describes the image contrast as a function of the spatial frequency (Thompson et al., 1983 and Mack, 1993 A).

4.2.2 Contact and Proximity Printing 4.2.2.1 Optical Mask Aligner

With respect to the equipment, 1:l contact printing is the simplest method. It is widely used for the production of devices with low resolution requirements (> 5 pm). A mask consisting of a glass or quartz substrate carrying an array of thin chrome pat-

4.2 ExDosure Tools

terns as absorber, is brought into intimate contact with the resist. This allows the simultaneous formation of many dies within one exposure, is cheap, and offers optimal pattern reproduction. Repeated contacts between mask and film may give rise to severe scratches, or sticking of resist pieces on the mask. Damaged mask patterns are then reproduced in the resist, which require additional time for reworking and mask cleaning, and diminish the yield. In shadow proximity exposure, the mask is separated by a gap of about 40 p m from the wafer plane. This avoids contamination and damage problems, but causes degradation of resolution due to diffraction effects (compare Eq. (4- 1>>. Optical mask aligners are usually equipped with mercury/xenon discharge lamps providing high output around: 400 nm, 3 10 nm and 250 nm (Fig. 4-7). In contact printing, broad band illumination is preferred, because standing wave effects are less pronounced when polychromatic light is used. Contact printing can be advantageously used to pattern very thick resist layers (< 200 pm) with high aspect ratios

KrF

248

XeCl ArF 193

t 1

200

300

400

500

Wavelength [nrn]

Figure 4-7. Comparison of emission spectra and energies provided by a mercury lamp and excimer lasers. (Courtesy of W. Spiess. Reproduced with permission.)

187

because the resist thickness is not limited by the depth-of-focus of any optical projection system (Loechel et al., 1994). Specially designed mask aligners allow for front and rear alignment (Cromer, 1993), which is needed for micromechanical applications, where the silicon substrate is etched through. 4.2.2.2 X-Ray Stepper

The resolution limits of optical systems using short wavelength radiation and improved resists together with optical tricks (Chu et al., 1991) are expected to be around 0.10-0.13 p m mainly due to the inadequate depth-of-focus budgets. Surface imaging schemes may give rise to further reductions of the device geometry at the price of increased process complexity. Ultra large scale integration (ULSI) patterns smaller than 0.13 pm without any depth-of-focus problem may be achieved using X-ray radiation (Peters and Frankel, 1989). The basic concept of X-ray lithography (XRL) is proximity printing. The improvement of the aerial image using X-ray beams compared with 200 nm radiation is quite obvious with respect to Eq. (4-1). Laser-based plasma sources (Chaker et al., 1991) emit “soft” X-rays of a wavelength (0.8-2.2 nm), which is short enough to give images not deteriorated by diffraction (Guo and Cerrina, 1991). Their medium brilliance (< 10 mW/cm2) requires highly sensitive resists (<50 mJ/cm2), and their resolution capability (-0.2 pm) is controlled by the penumbral blur (Frackoviak et al., 1993). Such data are also achieved by deep ultra violet (DUV) lithography, and it is doubtful, whether this approach will see a breakthrough into large volume production. In contrast, bright (compact) synchrotron storage rings with a power of > 100 mW/cm2 are candidates to become production tools in the future for sub 0.2 p m

188

4 Photolithography

lithography (Yanof et al., 1992; Simon et al., 1998), due to their high resolution capability (>70 nm; Ogawa et al., 1993) combined with high throughput. Other unique and important advantages of XRL are its insensitivity to dust particles and substrate topography (Yoshioka, 1990), as neither reflection nor backscattering effects occur, resulting in excellent linewidth control over topography as demonstrated in Fig. 4-8. Although these features make XRL superior to any other irradiation technique presently known, several problems exist, which have hampered its introduction into high-end IC production for more than a decade. The large size of, and high capital investments for, synchrotron sources as well as their complex ancillary system are severe drawbacks in the competition with other technologies, but acost per bit analysis demonstrates that synchrotron XRL might be the cheapest method of manufacturing ULSI-

devices (Roltsch, 1991). Various functional circuits (e.g., SRAM with critical dimensions of 0.35 pm) have been manufactured using XRL (Technology News, 1993). The suitability of XRL for the fabrication of three-dimensional microelements for integrated optics, sensors, and microgears by the LIGA process (German: Lithographie, Galvanoformung, Abformung) will only be mentioned here (Rogner et al., 1992; Ehrfeld et al., 1998). The first ‘commercialized’ compact synchrotron with superconducting magnets is the high energy lithography illumination by Oxford’s synchrotron (HELIOS) from Oxford Instruments (Kempson et al. 1991). Several state-of-the-art descriptions of synchrotron sources used in lithography have been given recently (Maldonado, 1991; Schmidtet al., 1991; Yoshihara, 1992; Cerrina, 1992; Smith, 1995). The usable wavelength range of X-rays (0.5-4 nm) is determined by the absorption properties of the mask and of the resist.

Figure 4-8. SEM photograph of AZR PN 114 (left: 0.4 mm lines & spaces; right 0.175 mm lines. Dose: 9 mJ/cm2. development: 60 sec. 0. 135 N AZTkfMIF 3 12) over metal topography exposed with X-ray radiation provided by a laser plasma source. (Courtesy of Hampshire Instruments, Ltd. Reproduced with permission.)

4.2 Exposure Tools

These photons are neither reflected nor refracted by any material known today and have to be used as they are produced by the source. As no optical system can be applied, neither projection nor reduction techniques, only 1 : 1 shadow printing with proximity gaps of -40 p m can be employed (Guo et al., 1991). High quality X-ray masks consist of a thin, X-ray transparent membrane ( 1 4 pm), which makes them very sensitive to distortions due to absorber stress (Acosta, 1991; Chaker et al., 1991). Their defect-free production and repair are difficult tasks (Koek et al., 1993). These problems have not been satisfactorily solved over the last ten years. Recently, progress has been reported (Wasiket al., 1998). High overlay accuracy (< 70 nm) has been demonstrated (Tsuyuzaki et al., 1994; Aoyama et al., 1997).

4.2.3 Projection Printing 4.2.3.1 Near UV Projection Systems

Current IC lithography is clearly dominated by projection printing methods. In the early 1980s, 1 : 1 full-field scanning optical projection cameras were the workhorses of IC lithography (Thompson et al, 1983). These machines operate with a special, low numerical aperture (NA) ring-field mirror lens. Their benefits were high throughput, and the property to allow exposure over a range of wavelengths. But their resolution capability did not meet the aggravating IC design rules. The increase of the NA of the mirror lens gave way to cameras with higher resolving power at the penalty of smaller exposure fields, resulting in the step-and-scan camera concept. Although these new cameras allow the NA to be doubled (> 0.3), they could not compete with the step-and-repeat reduction cameras (stepper), which currently dominate advanced IC production.

189

Modern steppers use monochromatic radiation (e.g. 436 nm or 365 nm, g- or i-line of the mercury emission spectrum, respectively; Fig. 4-7), a complex system of lenses with an NA>0.5 and allow diminution of the mask image by a factor of 5x or lox. As the field dimensions of the imaging system are of limited size, only a small part of the wafer, i.e. a single chip, is exposed during one irradiation step (Fig. 4-9). This lowers the production throughput, but yields highly reproducible patterns, as the same mask is used for each distinct unit. Beside resolution and DOF (Yamanaka et al., 1993), the image field size is another important issue, as it decreases with increasing NA due to difficulties in manufacturing adequate optics of large size (Noelscher et al., 1990). Several IC companies switched from g- to i-line lithography to manufacture the 4 MBit DRAM chips with critical dimensions (CD)of 0.8 pm, and now use this technology for the production of 16 MBit DRAMS or other devices with 0.5 pm design rules (Greeneich and Katz, 1990).

Mirror Light source Filter

Condenser

Reduction lens

I +

x-y stage

Figure 4-9. Schematic drawing of a step and repeat camera.

190

4 Photolithography

These products require a DOF budget of 1.5 pm due to topography, limited wafer flatness and focus error of the stepper (Peters, 1991). The first version of the 64 MB DRAM with CDs of 0.4-0.35 mm has been produced with i-line, but the shrunk versions (0.35 to 0.3 pm) required a switch to DUV lithography for certain critical levels. 4.2.3.2 Deep UV Projection Systems

As the production of small feature sizes is one major challenge i n ULSI lithography, it became inevitable to investigate DUV radiation for providing higher resolution together with an increased DOF budget (Mack, 1993 a). However, previously used lens glass has to be replaced by quartz with high DUV transmission. Mercury-xenon lamps have a high radiation output in the near UV range, but a very low one in the 200 to 300 nm region, which excludes the use of narrow band pass filters to avoid chromatic aberrations and demands mirror projection optics. Two commercial DUV mirror projection systems operate with servicefriendly and inexpensive high pressure mercury-xenon lamps. As their brilliance is poor, resists ofhigh sensitivity ( < 5 mJ/cm') are mandatory. However, antireflective coatings may be omitted i n the case of broadband illumination (Kuyel et al., 199 I ) . The Ultratech stepper operates at a wavelength of 24953 nm, while the SVG Micrascan machine (step-and-scan concept) provides exposure illumination over a 240 to 255 nm bandwidth (Buckley and Karatzas, 1989). A different approach to DUV illumination systems is based on excimer lasers (excited dimer), which are very powerful pulsed gas lasers, in which excited diatomic noble gadhalogen molecules formed by a high voltage electric discharge, e.g. XeCl (308 nm). and especially KrF (248.5 nm) or

ArF (193 nm), emit the laser radiation during their transition to the repulsive ground state (Fig. 4-7; Jain, 1990). By injection locking, their emission is extremely narrow banded ( < 2 pm) and therefore no attention has to be given to chromatic aberration (Preil et al., 1991). Experimental resolutions of 0.15 pm have been reported using this technology (Hartney et al., 1992) and adequate alignment systems with an overlay accuracy ~ 0 . pm 1 have been designed (Fig. 4-10; Wittekoek, 1992). Problems with respect to accurate dose control due to low reproducibility of pulse to pulse laser power have been resolved more recently (Kowaka et al., 1993). Excimer lasers can be integrated with reflective or refractive reduction optics to form useful images. As indicated by the major exposure equipment manufacturers, projection systems for use in 193 nm lithography are currently on the verge of moving from R&D to production tools. It is evident that several basic requirements are still not met by the machines available today. Among the biggest challenges are the material selection for, and optimization of the lens system, as the high-energy radiation causes lens compaction and formation of color centers in al-

25 20

8 $ 15

C P)

?! L L 5 n "

-30 -20

-10

Error / nm Figure 4-10. Overlay errors of an ASM-L DUV stepper. (Courtesy of ASM-Lithography. Reproduced after Wittekoek, 1992.)

4.2 Exposure Tools

most all suitable materials (Schenker et al., 1996). The potential and future of optical lithography, including sub-half-micrometer resolution, has been discussed in detail from various more specialized aspects recently (Arden, 1990 and Yamanaka et al., 1993). The supply of irradiation equipment for device fabrication, in general steppers, is presently dominated by six companies: Nikon, Canon, Hitachi (all Japan), Ultratech, Integrated Solutions (U.S.A.), and ASM-Lithography (Netherlands). Step-and-scan machines are available from SVG Lithography (U.S.A.) (Cromer, 1993) and ASM-Lithography, Nikon and Canon also started to offer scanners. More recently, Japan-based Komatsu announced its intention to produce and market lithography exposure tools. 4.2.3.3 Nonconventional UV Lithography

An extension of optical projection lithography is expected from the use of optical tricks, like the phase-shifting mask technology (PSMT; Levenson, 1992), the off-axis illumination technique (Shiraishi et al., 1992), the optical proximity correction (OPC) (Levenson, 1997), the focus latitude enhancement exposure (FLEX; f*ckuda et al., 1991), or the outline pattern transfer imaging (OPTIMA; Tanaka et al., 1991 b), pupil filtering (f*ckuda et al., 1994) (all developed to practical performance by groups at Hitachi), holography (Omar et al., 199l), imaging interferometric lithography (Brueck, 1998) and phase contrast lithography (Mack, 1993b). Certain restrictions with respect to mask making and pattern geometry limit their general applicability. Levenson (1992) concluded from calculations that g-line PSMT would resolve sub 0.5 mm patterns. Later Terasawa et al. (1 989) presented 0.3 ym wide periodical gratings using a low NA i-line stepper. To-

191

day i-line PSMT is feasible for sub 0.3 pm printing (Shirai et al., 1991; Watson et al., 1997), which favors it as a major competitor to DUV lithography for 64 MBit memory fabrication. Several IC giants with their own well-developed mask shops have selected i-line PSMT as their first candidate for printing 0.35 ym. PSMT is usable for all variants of photonic radiation, including excimer laser lithography (Sewell, 1991). It takes advantage of interference to omit certain diffraction effects typical for light projected through small apertures, which results in an improved aerial image (Fig. 4- 11). Light, as an electromagnetic wave, has a phase and an amplitude. A conventional mask (Fig. 4-1 la) consists of a quartz plate imagewise covered with an opaque layer, which defines the apertures of the patterns. Constructive interference between periodic openings enhances both the electric field and the light intensity to a maximum between them, thus reducing contrast and resolution. In the Levenson-type PSMT (Fig. 4- 1 1b) bordering apertures are covered with a transparent phase shifting layer, which reverses the sign of the electric field with the effect that bordering waves are 180" out of phase with one another. At the wafer plane destructive interference occurs, which minimizes the undesired light intensity between two adjacent openings (Levenson, 1992). Using simple pattern geometries, k l factors of ~ 0 . 3 have 5 been demonstrated under laboratory conditions, resulting in minimum patterns of 0.24 pm and 0.16 pm for i-line and DUV irradiation, respectively (Ohtsukaetal., 1991; Baiketal., 1993; Matsuoka and Misaka, 1997). The Levensontype mask layout offers the greatest increase in resolution and DOF; however, it is limited to periodic grating patterns (Brock et al., 1991), because of its termination problem: phase shifts in the middle of clear ar-

192

4 Photolithography

Radiation

Mask Phase shifter

n n

Electric field at mask

Electric field at wafer

at wafer (a) Conventional mask

(b) Phase shift mask

Figure 4-11. The change of aerial image intensity by applying Levenson-type PSM-technology: use of (a) a conventional and (b) a phase shift mask

eas of the mask produce artefacts on the device, when positive tone resists are used (Jinbo et al., 1990). During the last years, many alternative mask configurations, which can be used for printing of isolated patterns have been discussed (Toh et al., 1991 a; Yanagish*ta et al., 1991; Levenson et al., 1992: Rome et al., 1993). An overview of the important PSM technology variants is given in Fig. 4- 12. To get highly precise masks is difficult due to possible errors in phase and transparency. Pupil filtering is proposed to relax the mask error tolerances (Nakao et al., 1997). because a strict control in mask structure is required to obtain CD control. The main PSM suppliers, namely Dai Nippon Printing, Hoya and Toppan, have started sampling masks. Currently off-axis illumination has become very popular as a resolution enhancement technique. However, pattern deforma-

tion phenomena may occur mainly in island type patterns (Kim et ai., 1997). Line width deviations caused by lithography or etch effects can result from local pattern density variations (Fujimoto et al., 1997). OPC is a low cost technique to reduce such problems (Liebmann et al., 1997').The FLEX method is used for printing of isolated transparent patterns, like contact holes, using positive resists (f*ckuda et al., 1991), while the OPTIMA approach was applied to 0.2 mm regular patterns with practical focus (> 1.0 pm) latitudes and 0.13 pm-wide groove patterns using a 0.5 pm thick negative-tone i-line resist (Tanaka et al.; 1991b). The off-axis illumination techniques are favoured by the exposure equipment suppliers, as only minor modifications in the optical path are required. Canon and Nikon offer units called CQUEST (Canon quadrupole efficient stepper technology) and SHRINC (super high

193

4.2 Exposure Tools

4Phase Shifting Mask Technology

PSMT - Type

Edge

Resolution & DOF Enhancern.

50-80%

15-60%

40-6OYo

15-25%

10-20°/0

Application

Specialized

General

Packed patterns

General

Contacts

General

Resist required

Negative

Pos./ neg.

Negative

Positive

Subresolution Attenuation

Alternating

Chromeless Attenuation

Non Attenuated

Attenuated

Rim

Figure 4-12. Overview of various phase shifting mask technologies. (Reproduced from Buck et al., 1991.)

resolution by illumination control), respectively, for their existing g-line, i-line and DUV steppers, and have reported 100% D O F enhancements (Shiraishi et al., 1992). The advantage of this approach is restricted to the patterning of periodic structures (Partlo et al., 1993). Imaging interferometric lithography combines off-axis illumination with interferometric optics. Modeling results show that the limits of optical lithography should be extended to roughly CD-A/3, which means 120 nm for i-line (Brueck, 1998). A holographic method with an effective NA of 0.7 has been investigated by Clube et al. (1993) from Holtronic Technologies for printing 0.25 pm features into a 0.5 p m thick i-line resist. The holographic proximity printer achieves a high imaging resolution over a very large field size. The improvement of the present overlay capability of k0.5 pm is currently under study.

4.2.4 Post-Optical Lithography The requirements of optics and materials are becoming increasingly crucial for even smaller patterns, such that optical lithography seems to be approaching its technological limit. Therefore, nonoptical lithographies such as electron beam, X-ray, and ion lithographies are increasingly important in order to replace or mix and match with optical lithography. It should be noted that post-optical lithography requires not only higher resolution capability but also more accurate controllability in terms of mask and overlay than conventional optical lithography. High throughput rate is also required (Ish*tani, 1998). Direct Writing Electron beam lithography (EBL) currently dominates the photomask manufacturing industry (Pfeiffer and Groves, 1991),

194

4 Photolithography

and has a strong position as patterning method for prototype devices and advanced application specific integrated circuits (ASICs) or very high speed integrated circuits (VHSI), which are produced in small quantities (Newman et al. 1992). EBL is a pivotal element in microlithography and has largely contributed to progress in miniaturization (Pethrick, 1991). Currently used ebeam machines have been developed from the electron microscope. The beam is deflected and shaped by a series of electrostatic and magnetic optics. Direct writing (“scanning”) e-beam lithography employs either a round gaussian or a rectangular (fixed or variable) shaped beam suitable for building high resolution devices or providing high throughputs, respectively. Gaussian e-beam tools work in two scan versions: in the raster mode the beam scans the entire wafer along a serpentine path and is “switched” on and off, whereas in the vector mode it is directly addressed to its pattern position resulting in a considerable throughput enhancement (e.g. Philips Beamwriter). The shaped beam tools normally work i n the vector scan mode. EBL is characterized by an extremely high resolution capability (40 nm; Classen et al., 1992), but electron scattering through the resist material and more intensively through the substrate limit practical resolu-

tions to > 100 nm (proximity effect), especially when thick resist layers are employed. Software for proximity correction has been developed, e.g. CAPROX (Knapek et al., 1991). Figure 4-13 shows a simulation of the electron scattering at 10 keV, and 20 keV acceleration voltage. Obviously, the scattering range increases drastically with increasing energy, while the beam expansion in the resist is significantly reduced resulting in higher resolution (Rosenfield et al., 1991). Unfortunately, this is accompanied by a higher defect density in the substrate, caused by electron bombardment (Pethrick, 199 1). High resist sensitivity helps to reduce these defects. Direct write e-beam lithography is highly flexible because it obviates the use of a mask. The main drawbacks are the low throughput due to serial writing, and the relatively large investment costs making the manufacture of ICs via e-beam equipment only competitive with mask replication methods, if a number of less than 50 wafers is considered. Suggestions have been made concerning raising the wafer throughput by means of an array of microcolumns, based on the scanning tunneling microscope aligned field emission (SAFE) concept (Chang et al., 1992). Throughput of 50 wafers per hour for 100 nm lithography may be achievable, depending on the number of col-

Figure 4-13. Monte Carlo simulated trajectories of 100 (a) 10 keV, ( b ) 20 keV electrons in a 0.4 mm poly(rnethy1 methacrylate) resist layer on silicon. (Reproduced after Kyser et al., 1975.)

4 . 3 Photoresist Processing

umns employed. The extremely sharp tips of a scanning tunnelling or a atomic force microscope (STM, AFM) are a source of low energy electrons (160 eV) even under normal atmospheric pressure, which can be used to pattern very thin resist layers (scanning nearfield lithography). These techniques offer a cheap way to get prototypes of sub- 100 nm patterns but their throughput is extremely low (Marrianet al., 1993; Snow and Campbell, 1994). More recently, optical direct write laser systems as provided by Lasarray using HeCd (442 nm) or Ar' (364 nm) lasers have proven their competitiveness with e-beam based processes by delineation of 0.5 p m structures under manufacturing conditions (Rensch et al., 1989). The writing of mask and ASIC patterns may develop to a domain of this exposure variant, as the equipment is comparatively cheap, less sophisticated, and allows the use of standard resists. Ion beam lithography (IBL), first described in 1973, is under investigation as a method of direct writing (Bischoff et al., 1993). The ions produce very slow secondary electrons with short ranges in the resist: compared to e-beam lithography, the proximity effect is negligible, which is the reason for the tremendous ultimate resolution of IBL. Some special applications include broad beam ion milling to remove resist materials by ions (Bischoff et al., 1993), or the repair of patterns via focused ion beam chemical vapor deposition (FIB-CVD; Robinson, 1989; Morgan, 1998).During the exposure, ions are implanted directly into the substrate, giving rise to yet unknown possibilities for new processes. Electron and Ion Projection Lithography

Electrostatic lenses allow the use of electrons and ions in reduction projection systems which are candidates for post-optical

195

sub- 100-nm-lithography. SCALPEL (scattering with angular limitation projection electron beam lithography) (Liddle et al., 1997) and IPL (ion projection lithography) (Chalupka et al., 1992; Mohondro, 1997) can circumvent the difficulties of low throughput in direct writing and extremely tight manufacture specifications for 1x masks in X-ray proximity lithography. Both particle beam techniques work with existing resists. The most critical challenge is the fabrication of thin membrane masks etched out of silicon wafers . Masks for SCALPEL consist of a silicon nitride membrane on which metal patterns, which scatter the electron beam, define the layout. IPL definitely needs stencil masks which makes resist exposure more complex since two complementary masks are needed for one photo layer. On the other hand, the limited penetration depth of ions into any material has the advantage, that ions can be stopped in the resist very precisely. In consequence, any radiation damage in the device can be avoided.

4.3

Photoresist Processing

4.3.1 Quality Control and Resist Deposition 4.3.1.1 Purity and Storage Stability

Metal ions, especially sodium, iron, potassium, magnesium, manganese, copper and chromium, affect the electrical properties of the final IC devices. In advanced photoresist applications, typically metal contents of c 10 ppb for each distinct metal are required, which are controlled by atomic absorption spectroscopy, AAS, or by inductively coupled plasma-optical emission spectroscopy, ICP-OES, or mass spectroscopy, ICP-MS. These specifications pose new challenges to resist manufacturers, as

196

4 Photolithography

all chemicals have to be synthesized via nonmetal involving equipment. Particles in the resist solution5 will raise the defects, lower the device yield. and increase the rework expenditure. They are removed by simple filtration through microfilters with pore sizes <0.1 pm. Adequate storage stability of photoresists is a prerequisite for their quality maintenance and reproducible use. Instabilities may occur through slow dark reactions, which after a longer storage period can produce severe performance changes, or particle and gel formation. The lifetime of a resist starts with the mixing of its components at the producer's facility. The logistics of shipping and storage require a solution stability of at least six months. Most photoresists are sensitive to both light and heat or, depending on the solvent properties, to moisture up-take. Inadequate storage conditions are an obvious source of poor shelf life. Viscosimetry, gel permeation chromatography, UV absorption -and fourier transform infrared spectroscopy support resist quality and shelf life control.

4.3.1.2 Resist Coating Prior to resist coating, the wafer is heated to remove absorbed moisture and treated with an adhesion promoter (White, 1986), and then it is spin-coated with a resist solution. The solvent is evaporated on a hotplate at elevated temperature (prebake, softbake), and, depending on the viscosity of the resist and the selected spin-speed (Fig. 4- 14), the resist solidifies to a film thickness ( F T ) of 0.2 to 2 mm with excellent uniformity. FT variations are a troublesome issue when the photoresist has to cover an existing device topography (White, 1986; Yang and Serafinowicz, 1998). The prebake is a critical step, as residual solvent and com-

2000

3000

4000

5000

6000

7000

8000

Spin speed [rpm]

Figure 4-14. Film thickness, of a resist as a function of \pin speed

ponent distribution in the solidified film contribute to the lithographic performance (Fig. 4-15; Paniez et al., 1990; Beauchemin et al., 1994; Rao et al., 1994). Typical prebake conditions are 80 to 140°C heating on a hot-plate for 1 lo 2 minutes (Yoon t al., 1989). The optimum temperature is governed by the thermal stability of the resist, the evaporation physics of the solvent and the resulting lithographic performance (Gardiner et al., 1997). A large variety of substrates is used in the semiconductor industry, e.g. silicon, silicon dioxide, gallium arsenide, lithium niobate. or alumina. Adequate adhesion between resist and substrate is important to avoid dewetting, loss of resolution, undercutting, or even complete pattern destruction upon processing (Kawai et al., 1991). The adhesion is enhanced through the application of adhesion promoters, like trimethylsilyldiethylamirie (TMSDEA), hexamethylcyclotrisilazane (HMCTS), or hexamethyldisilazane (HMDS) in the gas phase (Michielsen et al., 1990). These reagents adjust the surface energy of the substrate to that of the resist layer by transferring free hydroxy groups present on the substrate surface into silyl ethers in a

4.3 Photoresist Processing

197

Novolak -

O L '60' ' , 8 0 ' ' ' 100' ' i 2 0 ' ' 140' ' 160 Bake temperature [ " 1

Bake temperature [ O ]

Figure 4-15. (left) Residual solvent (diglyme) and (right) solubility rate as a function of prebake temperature (30 min air oven dried materials)

base catalyzed reaction. Details of the theory of this process, called priming, have been given by Moreau (1988). The relation between contact angle, degree of surface coverage (as measured by secondary ion mass spectrometry, SIMS), and adhesion quality has been studied by Michielsen et al. (1990). A contact angle of 65 to 85", corresponding to a surface covering from 46 to 75%, neither results in adhesion-failure nor in dewetting.

formation on the sensitivity, e.g. in the case of a positive resist the dose to clear, D:, the intersect of curve and x-axis in Fig. 4-16. The dose required to obtain lithographically useful, residue-free patterns is about two times higher. The resist contrast, y, is usually defined as the change in resist film thickness with log of exposure dose as defined in Eq. (4-5) for positive and Eq. (4-6) for negative-tone

4.3.2 Resist Exposure and Development

Dn(i)

4.3.2.1 Characteristic Curve and Standing Wave Effects

A satisfactory production throughput, high sensitivity, high contrast and hom*ogeneity of the development process are some of the basic requirements for modern photoresists. Sensitivity is defined as the incident radiation energy density required to form a lithographically useful image and depends on a variety of process parameters, e.g. resist thickness, spectral output of the irradiation source, or type and concentration of developer. A plot of the film thickness ( F T ) over the decadian logarithm of the incident exposure dose is called characteristic or contrast curve (Fig. 4-16). It gives in-

Dp(i)

no rev. bake c o n t r a s t -3.0 -

reversal bake 115 "C

c o n t r a s t 11.5 Dn(0)

\ ,

' , , , 4 5 6 78910

30 40 5060 2

Exposure energy [mJ/cm ]

Figure 4-16. Characteristic curves of AZ 5214 for positive processing (no reversal bake) and negative processing (with reversal bake).

198

4 Photolithography 1.8

materials:

(4-5)

x 1.6

c VI

I -

(4-6) where FT, denotes the initial resist film thickness i n pm and D:. Db. D t , Dk are defined in Fig. 4-16. Often the normalized contrast y/FT, is used as a measure for resist performance (Soane and Martynenko, 1989). High contrast resists require a certain threshold dose to change their solubility properties and do not respond to low levels of radiation remote from the desired image areas, which improves resolution capability and aspect ratios (Spragg et al., 19911. While y/FT, values of standard formulations are typically smaller than 3, modern high contrast materials may exceed a value of 4 and higher. A high contrast value corresponds to a high optical transmittance - the unbleachable absorption should be less than 0.25 pm-' for a hom*ogeneous exposure over the whole resist cross section. This aggravates reflectivity and interference effects, resulting in low dimensional control over topography on highly reflective substrates (Lamola et al., 1991). Among the various effects, thin film interference is a special problem of DUV lithography as evidenced by the swing curve: the image intensity at the resist/substrate interface depends strongly on the resist thickness, as shown by the calculated data in Fig. 4-17 (Horn, 1991; Brunner, 1991). This effect causes significant open point dose changes and aggravates process control, which is more pronounced at 248 nm than 436 nm radiation. as can be seen from maximum-minimum variations in Fig. 4- 17. Brunner ( 199 1 ) demonstrated that the swing ratio S is described by Eq. (4-7): (4-7)

E -

1.4 1.2

1.0 L

0.8

1000

1050

1100

1150

1200

1250

Resist Thickness [nm] 1400

-L

1200 1000

800

+ c ;.

600 400

01 [r

200 O L

Exposure [ rnJ/cm2]

Figure 4-17. Top: Average image intensity vs. resist thickness at the residsubstrate interface for 436, 365, and 248 nm radiation assuming a resist absorbance of 0.33 pm-' on a Si substrate; bottom: Prolith simulated characteristic curve of an i-line resist (MacDermid 1024 on Si) for four resist thicknesses D. A large open dose change is observed for a quarter wave in resist thickness. (Reproduced after Brunner, 1991.)

where R , is the reflectivity at the resist/air interface, R, is the reflectivity at the resist/substrate interface, is the resist absorptivity, and F T the resist thickness. 4.3.2.2 Process Latitudes The lithographic useful dose is defined by its ability to equally print opaque and clear features, which are nominally equal on

199

4.3 Photoresist Processing

the mask, or by the 1:1 reproduction of patterns with various dimensions, as demonstrated for a standard i-line resist in Fig. 4-18. The exposure dose is given in terms of the exposure time, which is usually the controlled variable in a production environment. The indicated value of 250 ms corresponds to a sensitivity of 150 mJ/cm2, a typical and accepted resist sensitivity of currently used DNQ resists. The measured structure transfer capability of the resist is called linearity. The point where linearity breaks down is a measure for the practical resolution of the resist. Its ultimate resolution is usually better, but requires a dose which does not allow accurate reproduction of features with different sizes. The dose range which allows the correct mask reproduction within a linewidth deviation of +lo% is called exposure latitude. For the resist of Fig. 4-18, a permissible dose deviation of 20% for 0.45 p m structures was found. Another process determining parameter is the practical depthof-focus (DOF)budget, i.e. a certain allowable deviation from perfect focus. Figure 4-19 shows the change of feature sizes as a function of various focus settings for 0.45 pm structures. The selected material's DOF is well over 2.0 pm at the best dose; a minimal range of 1.5 p m is required, when

CD mask [pm]

Figure 4-18. Linearity of a standard positive-tone iline photoresist (1 : 1 dense lines & spaces).

poiil k

0,40

0,30J

, -1,0

150 mJ/crn2

-0,5

160mJ/cm2

0,O

"4 ,

0,5

1,0

Focus setting [p]

Figure 4-19. Focus latitude of a standard positivetone i-line photoresist.

single layer resists without special planarization techniques are employed. The process window of a resist is defined as the area in a exposure dose/defocus plot where the correct critical dimension is reproduced from the mask. Different illumination techniques and resist processes can be compared with respect to the process windows as shown by Van den Hove and Rome (1994) for 0.25 pm design rules. After exposure and prior to development, standard NUV resists are commonly subjected to a post-exposure bake (PEB) to raise the thermal stability through solidification of the film and to improve, due to diffusion phenomena, the process latitude and the profiles scalloped by standing wave patterns (Norbury and Love, 1991; Yanagish*taet al., 1990). For chemically amplified resists, the PEB is one of the most critical steps, because it affects not only the resist sensitivity but proximity effects also (Zandbergen et al., 1998). Since hot plate temperature uniformity is never perfect, within-wafer linewidth variations are caused by local temperature differences (Kemp et al., 1997). 4.3.2.3 Dissolution Rate and Development Methods

Development transfers the latent resist image into the final three-dimensional relief

200

4 Photolithography

image and is a very critical step for resist performance. Most important is the ratio of the dissolution rates ( D R )between exposed and unexposed areas (Cowie, 1994, and Fig. 4-20). While positive resists are soluble in both the irradiated and unirradiated areas (kinetic development control), the exposed areas of negative crosslinked resists are totally insoluble in the applied developers (thermodynamic development control). Commercial positive resists have DR ratios of > 1 .000 in appropriate developers, with dissolution speeds of 3000 nm/min i n the exposed, and only a few n d m i n in the unexposed areas (dark erosion). The DR of a resist can be measured in-situ by reflectivity monitoring during development (Thomson, 1990). Commercially available in-situ dissolution rate monitors (DRMs) are important tools for resist manufacturers as they help to identify novel high performance resist materials. The DR measurement gives not only general information about the dissolution rate and contrast but also characterizes the resist dissolution at any film thickness at the same time. This allows the detection of minor dissolution gradients or film inhom*ogeneities, which usually cause formation of non-optimum profiles.

'Oo0

Both the selection of developer type and development method contribute to the resolution, the image profile and the dark erosion. The use of solvent-based developers, typically xylene, or anisole, is declining as they may cause resist swelling, severe environmental pollution and waste disposal problems. Therefore metal-ion free (MIF) developers, containing buffered aqueous solutions of tetramethylammonium hydroxide (TMAH), or similar amines as bases, are recently greatly favored over solvent developers. An aqueous 2.38% TMAH solution (0.26 N) has become the worldwide developer standard, and novel resists should show compatibility and excellent performance with this standard to be globally accepted. However, a large number of formulations with different base-strength are available for specific processes. Beside TMAH they may contain surfactants and wetting agents, to improve the across-the-wafer development uniformity and to reduce development time and surface residues, called scum (Shimada et al., 1993). The shelf life of aqueous-alkaline developers is limited, as they are gradually neutralized by carbon dioxide absorbed from the air. Modern resists are characterized by their development latitude, which is the allow-

*--4F

,-+;

-2

;-:-

01 0

I./"[

PAC concentration

Figure ~ 4-20. DRs of, an unexposed and fully expo\ed DQNnovolak resist The D R ratio is defined a j DR,,,/ DRunlxp (Data tdken from Meyeihoter, 1980 )

4.3 Photoresist Processing

able variation in development time at a defined linewidth loss. Spray, puddle and immersion development methods are currently in use. The first two methods give better process reproducibility and meet in-line process and automatization requirements. Normally, development is a time-controlled process. Better process latitudes can be obtained when end point detection methods are applied (Thomson, 1990). Developers are optimized for room temperature processing (23 "C), as pattern acuity decreases with increasing temperature.

4.3.3 Pattern Inspection and Resist Profile Simulation Prior to substrate etching, the lithographically generated patterns are normally inspected with respect to the remaining film thickness, linewidth, line profile and defect density. The resist thickness is measured either optically or mechanically with a profile meter. Patterns can be inspected without damage with conventional optical microscopes, digital laser microscopes (Worster and Politzer, 1993), scanning atomic force microscopes (AFM; Toledo-Crow et al., 1993; Nelson, 1998), or low voltage scanning electron microscopes (SEMs; Allen et al., 1993b; Yoshimura et al., 1998). Defects caused by particles are detectable by the measurement of electrical short circuits or line interrupts in special test patterns. Several computer programs which simulate the lithographic behaviour of photoresists have been developed. They are valuable tools for the design, characterization, property prediction, and optimization of photoresist processing, including off-axis or FLEX illumination, diazonaphtoquinone and chemical amplification resists or top surface imaging processes (Hartney, 1994). Simulators like Solid C/Sigma C GmbH, SAMPLE/University of California (Toh et

201

al., 199 lb) and PROLITH/Finle Technologies, Inc., Austin, Texas, (Mack and Connors, 1992), as the most popular programs, have tremendous value to the lithographic community and allow comparison of experimental versus theoretical image characteristics (Trefonas and Mack, 1991). PROLITH calculations showed that for partially coherent exposure systems there is a fundamental difference between positive and negative resists with respect to process latitudes. The existence of tone dependency in lithographic imaging leads to an important conclusion: for any one pattern there is an optimum resist tone to print this pattern. It is now widely accepted for example, that contact holes have much greater depth of focus when imaged with a positive resist (MackandConnors, 1992). The CARPS program is a simulator which makes it possible to optimize the resist composition (Ushirogouchi et al, 1990). The interested reader is referred to review articles (Neureuther and Oldham, 1985; Hartney, 1994).

4.3.4 Etching, Resist Stripping and Planarization Resist hardening procedures enhance the adhesion between film and substrate, and improve the thermal and the chemical resistance towards wet and dry etch processes. It is achieved through the application of a post bake (hard bake), where the shaped resist images are subjected to a forced heat treatment, which removes residual solvent and may crosslink the resist (White, 1986). The selection of the optimum temperature is critical, as resist flow and hardening are competing processes. Hardening is also achieved by DUV illumination combined with an increasing temperature gradient during exposure (deep UV curing; Vollmann and Pawlowski, 1988). Resist hardening crosslinks the resist surface while ther-

202

4 Photolithography

mal flow is negligible. It may severely impede the final stripping of the films. Etching: The main function of a resist is to protect underlying parts of the substrate from overall area chemical or physical processes (Thompson et al., 1983). These include wet etching of the substrate surface; i.e. a buffered hydrofluoric acid etch of a silicon dioxide surface. Other substrates require alternative wet etchants, e.g. hydrofluoric acid with nitric, acetic or phosphoric acid, ceric ammonium nitrate-nitric acid, or alkaline potassium permanganate solutions. Wet etching is isotropic in nature and may lead to undercut phenomena, especially if the resist shows insufficient adhesion (Fig. 4-21). Many etch chemicals attack and degrade the resist patterns. Wet etching processes are simple, cheap and provide high throughput (Murray, 1986). Dry etching methods, including reactive ion etching (RIE), sputter etching or ion milling (Thompson et al., 1983), find increasing attention for patterning and stripping purposes (Flamm, 1992). These processes can be performed anisotropically (Fig. 4-2 1 ), but they are very complex procedures and may give rise to high radiation flux and elevated temperatures. They require resists with high chemical resistance

and dimension stability. As a rule of thumb, the dry etch stability of organic resists increases with the amount of aromatic moieties. A major problem of today’s dry etch technologies are the formation of particles (Petrucci and Steinbruchel, 1990) or device contamination by metal ions from the reactor environment (Joubert et al., 1989). Details of the various dry etch techniques are given in the literature (Moreau, 1988 and Soane and Martynenko, 1989). Other high vacuum processes are additive processes, like ion implantation or sputter metallization. As ion implantation requires extremely high vacuum, the resist is subjected to DUV-hardening to avoid the emission of volatile products. Metallization is usually done by vacuum deposition methods, e.g. evaporation or sputtering, by which the whole device surface is metallized. Again, extreme vacuum is necessary and the resist has to withstand the metal deposition without drastic changes in its solvent solubility, which is important for its use in the metal lift-off technique (Fig. 4-22). Stripping: Only high-temperature stable photoresists, e.g., photosensitive polybenzoxazoles, will remain in the device as interlayer dielectric or buffer coat (Ahne et al., 1992). Standard resists are removed totally

Figure 4-21. Results of different etch processes: (left) wet etch (highly isotropic), (middle) dry etch (directional) and (right) dry etch (highly directional).

4.4 Photoresists

Figure 4-22. Process flow of the lift-off process.

after the above-mentioned processes have been finished. To avoid any damaging of the processed substrate, mild chemical methods at low temperatures should by used. Stripping solvents which dissolve the remaining resist portions include e.g. glycol ethers, trichloromethane (Soane and Martynenko, 1989), ethanol amine, dimethylsulfoxide, or N-methyl-2-pyrrolidone.The application of ultrasound may enhance stripping performance. Difficult-to-remove, thermally crosslinked materials are chemically decomposed by oxidation using Caro’s acid. Some of the known stripping agents cannot be applied to alumina surfaces due to corrosion problems (Pai et al., 1991); in this case ozone or oxygen plasmas (ashing) are advantageously used. These plasmas are also successfully employed as stripping agents for resists on non-alumina substrates, but damage of the device surface is a problem still to be solved (Flamm, 1992). Planarization: Advanced photo lithography needs almost flat topography for the

203

subsequent photo layers, since reflections at edges and slopes can cause defects, and high topography steps may consume the tight DOF-budget. Multilayer resist systems have been proposed to planarize critical topography. Their use is restricted to local planarization, since the lateral flow range during the soft bake of the planarizing bottom resists is very limited. Other local planarization methods are based on liquid silicon oxide precursors, like spin-on glass or a mixture of silane and hydrogen peroxide condensed at low temperatures directly onto the wafer (flow-fill process). Especially for the metal layers, global planarization is possible by chemical-mechanical polishing (CMP) of the silicon oxide interlayer dielectric (Murarka et al., 1993). Recently, metal CMP is of rapidly increasing interest, because for the 0.18 p m device generation low-resistivity copper interconnects are essential and unfortunately, the patterning of copper is difficult since it cannot be etched in current plasma reactors (Li et al., 1994). The most viable patterning technique is the damascene process, where the dielectric is deposited and patterned first, then the copper is deposited on top. CMP then removes the surplus copper to leave just the in-laid interconnect pattern (Murarka and Hymes, 1995). One problem connected with global planarization by CMP for the exposure tool is to find the very low step height alignment marks with high accuracy and reliability. New alignment mark designs and sensors are under development (Rouchouze et al., 1997).

4.4 Photoresists 4.4.1 Principles of Photoresist Chemistry The use of positive and negative photoresists is a key element in the photolithographic process predominantly utilized in

204

4 Photolithography

the IC industry. While negative resists are used for circuits with relatively coarse structures, the production of high-end devices is dominated by positive resists. It was believed for a long time that negative resists are limited in their resolution capability. However, several new negative-tone materials print submicron patterns with similar accuracy to positive ones. A historical overview is given by Willson et al. (1997). Resist chemistry is classified by the principle of the radiation induced solubility change: crosslinking (photopolymerization), polarity change or polymer degradation. It is obvious that resist performance is strongly affected by the properties of the different components and their relative concentrations. While the film forming polymer affects the thermal stability and solubility properties of the resist, the sensitivity to the applied radiation is mainly determined by the quantum yield of the photoactive compound's photochemical reaction. Two cases are distinguished: ( 1 ) single photon processes, where one photon changes the solubility property of only one chemical group and (2) chemical amplification processes, where one photon triggers many chemical reactions which change the solubility of the resist. In case (2) the resist sensitivity may be greatly enhanced compared with ( I ) .

horse in semiconductor manufacturing to delineate structures with resolutions down to 2 p m (Thompson et al., 1983). Although such systems show big DR ratios, their resolution capability is limited by swelling during solvent-based development. When irradiated, the azido group eliminates molecular nitrogen to yield a highly reactive nitrene in both the singlet ( S 1) and triplet ( T l ) state, which may dimerize (azo dye formation (TI, SI)), add to double bonds (aziridine formation, T l ) , form radicals (Tl), or insert into carbon-hydrogen bonds (secondary amine formation as main product, S1) (Fig. 4-23; Reiser, 1989). Nitrenes react with the ever-present atmospheric oxygen under formation of highlyabsorbing nitroso compounds, which deteriorate the image quality. Typically, difunctional azido compounds, namely 4-alkyl-2,5-bis(p-azidobenzal)cyclohexanones (ABC, sensitivity range 340 to 420 nm), or bis(p-azidocinnamy1idene)cyclohexanones (sensitivity range 365 to 480 nm), are employed (Thompson et al., 1983). Among the polymer binders suggested as matrix resins, poly-(cis-isoprene), became the most frequently used polymer

4.4.2 Negative-Tone Resists

f3-k

2 R-N.

4.4.2.1 Photocrossslinking via Azides

Two-component crosslinking systems based on bifunctional azido derivatives as photoactive compound (PAC) and a reactive polymeric binder, have found widespread application in the printing plate and photoresist industries (Reiser, 1989). The first product for the electronic industry was Kodak's Thin Film Resist (KTFRO), introduced in 1954, which became the work-

b) R-N

H-C-

R-N.

R-N=N-R

__ *

R-NH-C-

j C)

R-N.+

H-4-

R-NH

+ 'CI

e ) 2 R-N.

2R-N=0

Figure 4-23. Photoreactions of azides.

4 . 4 Photoresists

for large scale integration (LSI) microlithography (Reiser, 1989). The stripping of photocrosslinked isoprene resists may sometimes cause trouble and requires special strippers. Recently, Rutter et al. (1992) have used bifunctional azides to introduce photoreactivity into high-temperature stable benzocyclobutane (BCB) pre-polymers, which can be used as interlayer dielectric in multilayer interconnections due to their good thermal stability (>250°C) and very low dielectric constant. Combinations of novolaks or polyhydroxystyrene (PHS) with new monofunctional azide sensitizers, e.g. 4-azidochalcone derivatives (Reiser, 1989), yield resists with high sensitivity towards i-line (365 nm, 13 pJ/cm2) or g-line (436 nm, 55 pJ/cm2) radiation. The alkaline developers allow delineation of structures in the submicron range without swelling (Bendig and Gruetzner, 1990). Their interesting lithographic performance has revived world-wide activities (Kawai et al., 1989; Nonogaki and Toriumi, 1990). 4.4.2.2 Free-Radical- Initiated Polymerization

Methacrylate based photopolymerization is the basis for most dry-film photoresists and solder masks in printed circuit board manufacture and for high-temperature stable photoresists (e.g. photosensitive polyimides or their precursors) used as dielectric interlayers or buffer coats in the IC industry (Horie and Yamash*ta, 1995). Compositions useful for photolithography consist of a photoinitiator (PI), a matrix resin (e.g. polymers with methacrylate side groups) and optionally multifunctional monomers. Upon absorption of radiation, the PI is raised to an electronically excited state and generates radical fragments, which add to and initiate the polymerization of an unsat-

205

urated monomer (initiation). The resulting intermediate radical further adds to unreacted monomers, giving rise to molecular growth (propagation). The process is terminated by radical recombination, chain transfer or oxygen inhibition (termination). Oxygen is known to act as a quencher for the excited initiator and as a trap for free radicals by forming peroxy radicals of low reactivity. The chemistry and physics of the photopolymerization process (Fig. 4-24) are discussed in detail elsewhere (Rabek, 1987; Fouassier, 1989). Compared to many other photoimaging processes, systems based on photopolymerization have a remarkable high photospeed due to a chemically amplified mechanism. Although primary quantum yields (radicals produced per photon absorbed) are usually < 1 (Reiser, 1989), one absorbed photon may initiate polymerization of thousands of monomers. Shimizu (1988) reported an ultimate photopolymerization photoresist sensitivity of 13 pJ/cm2.The sensitivity and other resist parameters are strongly governed by the polymer morphology (Maerow, 1986). Like most negative working compositions based on an increase of molecular weight, the exposed, insoluble areas of the photopolymer film tend to swell, in particular during solvent development, making this chemistry definitively unsuitable for the fabrication of sub-ym microelectronic devices. The resolution requirements for hightemperature stable photoresists are less severe (>5 pm) and most of these materials on the market (Photoneece UR 5100@/ Toray, Pimel G-7610B/Asahi Chemical, XB 7020@/OCG, Pyralin 2732@/Du Pont, and Ultradei 7501@/Amoco) are based on special polyimide (pre) polymers with attached photopolymerisable methacrylate side groups. After exposure and development in organic solvents, these side groups

206

4 Photolithography

Formation of radicals:

Initiator (Initiator)'

(Initiator)' Initiator - H

Initiation reaction:

Propagation reaction: R-CI+-CH

+ n CI+=CH

Termination reaction:

R-Ck-CH

RfCb-CH-),+b-CH. I

R-CI+-CH-CH-Cb-R

Oxygen inhibition:

R-Cb-CH'

R-CH.-CH-O-O.

Figure 4-24. Simplified mechanism of the photopolymerization process

are released from the polymer i n a subsequent curing step at temperatures above 300 "C, and the final high-temperature stable (normally insoluble) polyimide is formed (Ahne et al., 1992; Horie and Yamash*ta, 1995). Most photoinitiators (PIS) are divided into two classes by their reaction mechanism: intramolecular bond cleavage to the radicals P* and I*, called photofragmentation, or intermolecular H-abstraction from a hydrogen donor RH, called a coinitiator, to form PIH* and R*. The former type of initiators is known as PI 1, as radical formation occurs in an unimolecular process, the latter as PI2, since two molecules are involved. Examples of both types and their decomposition mechanisms have been reviewedindetail (Reiser, 1989; Rabek, 1987: Vesley, 1986; Timpe and Baumann, 1988). PI 1 compounds form free radicals mainly via the Norrish type I cleavage (Fig. 4-25). As an example. benzoin alkyl ethers, which exhibit a weak absorption band at 330 nm, decompose to benzoyl and benzylether radicals, which both participate i n the initiation

reaction. The main side reactions of benzoin alkyl ethers are dimerization, H-abstraction and chain termination. Photoinitiators of the PI2 type include benzophenone, Michler's ketone, thioxanthones (QuantacureTM ITX, LucirinTM 85 13), benzil, quinone derivatives and 3ketocoumarines (Fig. 3-26; Reiser, 1989). These compounds abstract hydrogen from H-donors. typically tertiary amines with abstractable a - H atoms, such as triethyl amine, N-methyldiethanol amine, or 4-dimethylamino benzaldehyde. The intermediate exciplex decays to an a-amino radical, which acts as the initiator, while the ketyl radical does not contribute to this process. The oxygen sensitivity of PI2 systems is superior to that of the PI 1 type initiators, because the amine reacts with non-initiating peroxy radicals to reactive a-amino radicals. 4.4.2.3 Acid-Catalyzed Crosslinking

4.4.2.3.1 Cationic-Initiated Polymerization Besides radicals, cations and anions are capable of inducing photopolymerization

4.4 Photoresists

207

Figure 4-25. The Norrish type I fragmentation of benzoin ether, benzil diketal and dialkoxy acetophenonederivatives.

o +

Benzoinether

Benzildiketal

'0 Dialkoxyacetophenone

Michler's Ketone

Thioxanthone

Bis (ketocumarin)

Figure 4-26. Chemical structures of some Norrish type I1 photoinitiators.

reactions (Reiser, 1989). Photoinitiated cationic polymerization offers several advantages: (1) new monomers with unique properties can be polymerized, (2) recombination of the carbocations is excluded, giving rise to high polymerization degrees, and

(3) insensitivity to oxygen. Certain limitations have restricted its commercial breakthrough: (1) only few initiators are available, (2) sensitivity to termination reactions by nucleophilic impurities, e.g. bases and humidity, or (3) sensitivity to chain-transfer processes (Timpe and Baumann, 1988). The polymerization process, as exemplified with an epoxide in Fig. 4-27, is initiated by the photogenerated Lewis acid (BF3), which adds to the oxirane with ring opening and the formation of a carbocation. This reacts rapidly with a new epoxide molecule. The energy released during opening of the strained ring contributes to fast propagation of the addition. Several negative resists based on cationic polymerizable materials have been described by Crivello et al. (1988), Ito and Wilson (1984), and more recently by Hatzakis et al. (1991). They employed commercially available epoxy resins (e.g. Epi-Rez@ SU-8, Quatrex@ Epoxy Resins) together with triarylsulfonium salts for DUV and ebeam resists. An optimized material (EPTR) is capable of resolving 0.1 pm features in a 0.8 mm thick resist at an e-beam dose of

208

4 Photolithography

Ringopen R

Monomeraddition R

k Figure 4-27. Reaction mechanism of Lewis acid i n duced cationic photopolymerization.

~ 0 . pC/cm2 5 (Chiong et al., 1990; Hatzakis et al., 1991). Zeng et al. (1989) described a similar approach using alternating copolymers of vinylcarbazole and ethyl glycidyl fumarate. The contrast is approx. 4, and the carbazole unit renders adequate etch resistance to the polymer. A thick-film material developed by IBM using SU-8 resin has recently been investigated for microelectronic mechanical system (MEMS) applications (Lorenz et al., 1997). It was found that the material could be single-spin coated up to a film thickness of 500 pm and to more than 1200 p m upon multiple coating steps. In a thickness range from 80 to 1200 pm structures with an aspect ratio of 18 have been reproducibly formed using a broadband NUV contact aligner (Lorenz et al., 1998). 4.4.2.3.2 Acid Hardening Resists

Significant progress with respect to contrast, sensitivity and image stability was achieved with acid-hardening resists (AHRs) based on the thermally catalyzed crosslinking reaction of an acid-sensitive precursor (Lamola et al., 1991). Commercially available AHRs consist of three components: an alkali soluble matrix resin, e.g. novolak

or a PHS derivative, a photoacid generator (PAG), and an acid-labile crosslinker. AHR systems have a superior potential for optimization. Just by judicious selection of the PAG, the materials can be modified to fully meet the requirements of near UV (Barra et al., 1991), DUV (Pawlowski et al., 1990a), e-beam (Liu et al., 1988), or X-ray lithography (Padmanaban et al., 1992). The process flow and relevant chemistry of AHR systems are outlined in Fig. 4-28. Upon exposure, the initiator is activated to release a strong Bronsted acid, while the crosslinker remains unchanged. In a subsequent bake step the activation barrier of the acid-induced crosslinking reaction is exceeded, resulting in network formation with reduction of the DR (Thackeray et al., 1991). Compared with standard resist processing, this post exposure bake (PEB) step is the only additional process variable. It has a significant influence on the resist performance (f*ckuda and Okazaki, 1990; Azuma et al., 1993). The acid is regenerated during the crosslinking reaction, and one absorbed photon may induce a cascade of crosslinking events, giving rise to the phenomena of chemical amplification (CA), responsible for the observed high photospeed of chemically amplified resist (CAR) systems. In the real world several ways of acid loss exist, and as a matter of fact controlled acid consumption is a prerequisite for generating accurate images. It has been proposed that the PEB can induce thermally activated diffusion of the acid catalyst limiting the principle resolution of an AHR. Perkins et al. (1993) extracted an upper limit for the acid diffusion coefficient of 0.3 nm2/s from the PEB-time (1 10°C) dependency of the feature size generated with a scanning tunnelling microscope in an AHR. This value is smaller than reported previously indicating that diffusion of the acid has only a small effect on the linewidth.

4.4 Photoresists

209

Resist Substrate Exposure

Acid generation

Post exposure bake Acid induced catalytic reaction

Development

Figure 4-28. Process flow and chemistry of three component AHR negative resists.

Suitable crosslinkers for AHR chemistry include melamine and urea resins with a N,O-acetal structure, like hexamethoxy methyl melamine (HMMM), tetramethoxy methyl glycoluril (TMMGU), or mixtures thereof. Under acid catalysis, these compounds form a highly reactive carbocation with the loss of methanol, which either directly attacks the electron-rich aromatic ring of the polymer, or forms an alkyl-arylether bond (Fig. 4-28). This suggests that the reduction of the DR occurs via two separate mechanisms: consumption of phenolic groups, and increase of molecular weight via crosslinking (Thackeray et al., 1991). Both, high crosslinker purity and exclusion of water are mandatory to guarantee acceptable shelf-life stability of the photoresist solution. Beside melamine and urea ethers, the respective alcohols or acetates may be used (Fig. 4-29). In addition, acetal blocked benzaldehyde derivatives (Schaedeli et al., 1993), or multifunctional benzyl alcohols,

ethers, or esters have been recommended (Spak et al., 1990). The methylether derivatives are preferred over any other group because they are the most stable in both solution and film state, and cause a minimum film thickness loss during crosslinking. In contrast to positive tone CARS, AHRs are quite stable towards delay time changes between exposure and PEB: even after 24 hours no sensitivity or linewidth variations were observed on 0.5 ym patterns (Pierrat et al., 1990; Roeschert et al., 1992; Conley et al., 1993). All major photoresist suppliers have developed and are currently marketing i-line and DUV sensitive AHR materials. The iline photoresists are based on novolak as the matrix resin, but use different PAGs and crosslinkers. Their resolution using conventional exposure tools is well below 0.4 y m with a focus budget in the range of 1.5 ym (Amblard and Weill, 1993; Linehan et al., 1994; Puttlitz et al., 1995). As novolaks are

21 0

4 Photolithography R

R R

O 7

04"xN*o OJ"

d Melamine type XL (R = -H, -CH3 [HMMM]. -C4H9, COCH3)

y o\ R

Urea type XL (R = -H, -CH3 [TMMGU], -C4H9, -COCH3)

iH3 iH3

q Y

H3C -0

0 0

dH3 dH3

Terephthal aldehyde tetrarnethyl acetal

4,4'-Di-(methoxymethyl) diphenyl ether

KCH3 0

1,3,5-Tris-(acetoxy methyl) benzene

Figure 4-29. Chemical structures of crosslinkers used in AHR chemistry.

highly absorbing i n the DUV (248 nm) range and thus unsuitable for use in DUV resists, they are replaced with more transparent resins, such as poly-(4-hydroxystyrene) (PHS) derivatives, which typically exhibit optical densities <0.2 pm at this wavelength (Fig. 4-30). Due to their excellent film forming properties, solubility in alkaline developers, and high dry etch resistance, PHS based resins have become the standard polymer for both negative and positive DUV photoresists. The use of pure PHS as matrix resin causes incompatibility with standard 2.38% TMAH based development processes and an effect called microbridging (Linehan et al., 1995). Reduction of the dissolution rate by introduction of alkali insoluble comonomers overcomes these issues (Roeschert et al., 1992: Conley et al., 1993: Brunsvold et al., 1997).

During the last few years, astonishing improvements have been achieved in negative DUV resist performance (Das et al., 1990). While current negative DUV resists are capable of resolving sub 0.20 p m dense features, their real strength is excellent is0 line performance (Fig. 4-3 l), as demonstrated with Clariants AZ EXP 1400N (Kudo et al., 1998). FrCchet et al. (1991) have investigated two-component acid hardening systems based on selfcrosslinking copolymers of 4-hydroxystyrene with 4-acetoxymethyl styrene, 4-(3-furyl-3-hydroxypropyl)-styrene, or 4-( 1-hydroxy- 1 -methylethyl) styrene (Yoshida and FrCchet, 1994) and certain sulfonium salts as PAG. Upon exposure, the photoacid cleaves the benzyl acetate to produce a carbocationic benzyl intermediate, which attacks the hydroxystyrene moieties under regeneration of the acid (Fig. 4-32).

4.4 Photoresists

21 1

1.2

0.8 0.4

Polyacrylates (aliphatic)

;-.

;

-. -.

0.0 175

200

-.-._

225

250

275

300

325

350

375

400

Wavelength [nm] Figure 4-30. UV spectra of novolak, poly-(4-hydroxystyrene and aliphatic polyacrylates.

Figure 4-31. Depth of focus for 0.15 pm is0 lines of the DUV negative photoresist AZ EXP 1400N (Silicon). (Nikon NSR EXIOB, NA =0.55, si=0.55; film thickness, 0.70 pm dose: 44 pJ/cm2; development: AZ 300MIF).

-(-LH-CH2-CH-C&-)--

04c,CH3 I ,CH2 PAG = photo-acid generator

Figure 4-32. Photoacid induced crosslinking reaction of poly(4-hydroxystyreneco-4-acetoxymethyl styrene).

212

4 Photolithography

The material produces a high contrast ( g > 14) negative image with an DUV dose of 2 mJ/cm’, and alkaline development. It gives positive images by use of a photobase and a thermal labile acid precursor. Hayashi et al. (1990) have formulated negative CARS consisting of a novolak resin, diphenylsilanediol, and an onium salt for i-line, DUV and e-beam applications. These materials resolved 0.3 pm structures at 0.7 pm film thickness upon DUV (NA = 0.42) and phase shift mask supported i-line exposure. The dissolution promoting silanediol is converted into a siloxane oligomer under acidic conditions. The resist material is almost insensitive to the delay time (between exposure and PEB), and exhibits high DUV (3 mJ/cm’) and e-beam

sensitivity (0.8 pC/cm2 at 30 keV). Sachdev et al. ( 1994) crosslinked phenolic hydroxy groups with bifunctional dihydropyran derivatives by photoacid catalyzed acetal formation. This resist is equally well suited for X-ray, DUV and i-line exposure. Acid-catalyzed dehydration of phenylcarbinols is used for the insolubilization of phenolic resins yielding resist materials for i-line, DUV and e-beam applications (Uchino and Frank, 1991; Ueno et al., 1994; Kojima et al., 1996). 4.4.2.3.3 Photoacid Generators The PAG plays a dominant role in chemically amplified resists, such as AHRs. Its absorption properties require careful opti-

CF3SO3

....

CF3SO3H

....

+ &S

A ~ ~ S

’A\) A ,

Figure 4-33. M e c h a n i m of photolytically induced acid formation in iodonium and sulfonium d t \

4.4 Photoresists

mization, and its chemistry governs the acid properties produced upon exposure, such as acid strength, size and mobility, factors which influence the pattern quality. Two main groups are distinguished: salt-like ionic and nonionic PAGs. The most important representatives of the ionic type are the onium salts, e.g. triarylsulfonium or diaryliodonium salts with superacids forming anions (Crivello, 1984; Schwartzkopf et al., 1991). Among these, the trifluoromethane sulfonates are preferred in IC production (Cameron et al., 1997), as the metal-containing superacids, e.g. hexafluoroarsenate, are considered to be device contaminants. A simplified mechanism for the photoacid generation from diphenyl iodonium (DPI+) and triphenyl sulfonium (TPS+) salts is outlined in Fig. 4-33. More detailed mechanisms have been discussed by Tsuda and Oikawa (1990) and

Hacker and Welsh (1991). The excited onium cation cleaves hom*olytically. The intermediate heteroatom centred radical salt abstracts a hydrogen atom and forms the acid. Standard onium salts are active in the deep- or mid-UV region, their sensitivity may be extended into the near UV range by chromophore modification (It0 et al., 1988; Hayashi et al., 1990) or photosensitization (Crivello et al., 1988). Sulfonium salts are among the most efficient PAGs presently known with quantum yields of 0.24 to 0.4, depending on the polymer matrix (Allen et al., 1989). Nonionic photoacid generators are usually divided into two categories, as they produce either hydrogen halides (HX), or sulfonic acids (RS0,H). Examples of HX-generators include 1,l-bis(4-chlorophenyl)2.2.2-trichlorethane (Feely, 1985), 4,6-bis(trichloromethy1)- 1,3,5triazines (Fig. 4-34),

0 I/

O-S-R3

OR 1 , t '-Bis-(4-chlorophenyl). 2,Z.Z-trichloroethane

2,l-Diazonaphthoquinone4-sulfonate (R =aryl)

Pyrogallol-tnssulfonate (R = CF3, alkyl, alyl)

a,a-Bis(arylsulfony1) diazornethane (R =alkyl)

a-Hydroxy-P-sulfonyloxy ketone (R = -CF3, alkyl, aryl

CbC'

OSOzR

4,6-Bis-(trichloromethyl)1,3,5-triazin-Z-yl-stilbene (R = alkyl)

HowoHF? 8'

R I

o=s=o I

0 I

o=s=o

Br OH

Tris-(3,5-dibrorno-4-hydroxyphenyl) ethane

213

02N&No2 2,6-Dinitrobenzylsulfonate (R = CF3, alkyl, aryl)

R Naphthylimidylsulfonate (R = CF3, alkyl, aryl)

Figure 4-34. Chemical structures of photochemically active hydrogen halide and sulfonic acid precursors.

21 4

4 Photolithography

about one order of magnitude slower than TPS+SbF,, and their sensitivity towards PEB conditions is more critical.

or brominated phenols (Buhr et al., 1989a). Sulfonic acid producing PAGs (Fig. 4-34) include 2,1-DNQ-4-sulfonates (Buhr et al., 1989b), a , a - b i s arylsulfonyl diazomethanes (Pawlowski et al.. 1990b), a- and p sulfonyloxyketones (Onishi et al., 1991 ; Roeschert et al.. 1993a), arylsulfonates (Ueno et al. 199 1 ). N-sulfonyloxy-maleimide derivatives (Brunsvold et al., 1991), and o-nitrobenzyl sulfonates (Houlihan et al., 1991 A). The cx,a-bis arylsulfonyl diazomethanes are especially useful for photolithography, as they combine adequate thermal stability with high quantum yields, and efficiently bleach even at small exposure doses as required for DUV sensitive CARS. Houlihan et al. (1991) studied extensively the photochemical behaviour of nitrobenzyl sulfonate esters (NBSE) as PAGs (Fig. 4-35). Electron-withdrawing groups in the sulfonate group increase the acidity of the resulting sulfonic acid. The photospeed of NBSE based deprotection resists is

HO "0

4.4.3 Positive-Tone Resists 4.4.3.1 Dissolution Inhibition/Dissolution

Promotion

The majority of positive resists currently used in the IC industry are based on twocomponent systems, where a dissolution inhibitor, normally a cyclic 2-diazo-1 -naphthoquinone (DNQ) derivative, is transformed upon photolysis into a dissolution promoter for the aqueous-alkaline development of the resist. The base polymers are phenolic resins, typically novolaks (Dammel, 1993). The process flow of DNQnovolak resists and the chemistry of the photoactive compound (PAC) are given in Fig. 4-36. The dominance of DNQ-based resists arose in the 1970's, when they took over

0 N

Figure 1-35. Photochemistry of nitrobenzyl sulfonate esters.

4.4 Photoresists

215

Resist

.u-

~JJJ

Substrate

I-N

Exposure wolf

.u-

Development

Figure 4-36. Process flow and relevant chemistry of DNQ-novolak photoresists.

from isoprene resists for the production of 16 kBit DRAMS.Today, the 16 MBit DRAM with a 1000-fold increase in integration density is manufactured, still using the above shown chemical principle but with the aid of DNQ resists with substantially improved performance. However, the end of the DNQnovolak era is in sight now (Holmes and Sturtevant, 1993). 256 MBit DRAM production will definitively require departure from conventional NUV lithography. This long lasting success of DNQ-novolak resists is based on their high resolution capability, their relatively broad processing window and their excellent resistance against dry etch processes. In order to find out the reason for this remarkable performance this system has to be looked at in more detail. The unphotolyzed DNQ acts as an dissolution inhibitor for the alkaline soluble novolak due to molecular interactions between the phenolic groups of the novolak and the DNQ chromophore (Dammel, 1993). This dissolution inhibition phenomenon allows only for a small, but non-zero, dissolution rate (DR) of the resist in the developer which is smaller than that of the matrix resin itself. Upon imagewise irradiation

the DNQ-PAC is converted into an indene carboxylic acid (ICA) derivative which acts as a dissolution promoter, because: (1) the ICA is soluble in the alkaline developer and (2) the dissolution inhibiting interactions between the DNQ and the resin are destroyed. Therefore the exposed resist areas become more soluble in the developer. Modern resist materials may show DR-ratios (DRexposedlDRunexposed) of more than 10 000 with a DNQ loading of -20 % (Fig. 4-20). 4.4.3.1.1 Photoactive Compounds All technically used DNQ-resist formulations are based on two different types of photoactive compounds (PACs), namely aromatic 4- or 5- sulfonate esters of 2-diazo naphthoquinones. While the a-diazocarbonyl unit is the prerequisite for the photochemically induced solubilization reaction, the sulfonate group provides an anchor to modify the PAC properties without interference of the chromophore. Ballast compounds frequently applied for NUV applications include hydroxy-benzophenones (Reiser, 1989), bisphenol A derivatives (Tzeng et al., 1991), curcumin (Martin et al.,

216

4 Photolithography

1987),trihydroxy-phenylmethane (Kajita et al., 1991), and phenolic polymers (Hanawa et al.. 1993). Aromatic 2.1 -DNQ-5-sulfonate esters show absorption maxima at 350 and 400 nm, and are sensitive towards 365 nm (i-line), 405 nm (h-line), and 436 nm (g-line) radiation (Fig. 4-37, Thompson et al.. 1983).The absorption peaks of the aromatic 2.1-DNQ4-sulfonate esters are centred around 3 10 and 380 nm, and these PACs are insensitive towards g-line radiation (Fig. 4-37), but are advantageously used in i-line resists. With the switch from g- to i-line resists, the synthesis of new PACs with i-line transparent ballast compounds was a key project for many resist suppliers. The performance of DNQ-novolak based photoresists, e.g. exposure latitude, depth of focus, and resist profile shapes is characterized by three parameters, which are related to the bleachable (A-value), and the non-bleachable resist absorbence (B-value), and an optical sensitivity term (C-value), known as the Dill

,-line

r--

g-line

0.4

a C

0.3 0 n y.

02 0' 00 300

350

400

450

500

Wavetengtb [nrn;

Figure 4-37. Comparison of UV Spectrum of a 2,1DNQ-5-sulfonate and a 2.1 -DNQ-4-sulfonate derivative$ with 2,3.4-trihydroxybenzophenone a$ the ballast compound

parameters (Reiser, 1989). Examples of ballast compounds with a small Dill B parameter, include 2,3,4,4'-tetrahydroxy diphenylmethane (Tzeng et al., 1991) or certain spiro compounds (Tan et al, 1990). The photolysis of DNQs (Sues Reaction) is principally ratified, but several details have been understood only very recently (Reiser, 1989; Vollenbroek et al., 1989a, b). By absorption of a photon, an excited singlet state of the PAC is generated with a quantum efficiency of -0.2 (Thompson et al., 1983). 2,l-DNQ-5-sulfonates (Fig. 4-39, I) eliminate molecular nitrogen from this singlet state and undergo a ring contraction (Wolff-rearrangement) to form a highly reactive ketene (Fig. 4-39, 111; Tanagaki and Ebbesen, 1989), which is stable enough to be detectable by laser ilash photolysis (Rosenfeld et al., 1990). It reacts at room temperature immediately with nucleophiles, such as water ubiquitous in the resist film, to generate the main photoproduct (about 85% yield), the 1H-indene-3-carboxylic acid-7-sulfonate (ICA. Fig. 4-39, V) derivative. The mechanism indicates that water is an essential component of DNQ photochemistry, which becomes obvious in thick film applications (Shibayama and Saito, 1990). Two important physicochemical changes go together with the photoinduced transformation of the PAC to the ICA: (1) the resist absorbence i n the near UV region is considerably reduced (bleaching, Fig. 4-38), and (2) the carboxylic acid groups promote the resist dissolution in the exposed areas. If water is absent, the usually much slower ester formation of the ketene 111 with the free phenolic groups of the resin becomes dominant, yielding a crosslinked material with reduced solubility (Fig. 4-39, I + IV), which interferes with the formation of the desired positive image, but has also given rise to new imaging concepts

21 7

4 . 4 Photoresists

Figure 4-38. Dynamic photo1.03

200

300

resist bleaching absorption spectra of HPR 204 due to the photolysis transformation from DNQ to ICA. (Reproduced from Shankoff et al. (1980) with permission.)

400 500 Wavelength (nm)+

(Mutsaers et al., 1990). Other competing or thermally initiated reactions have been observed (Koshiba et al., 1988, e.g.: I1 in Fig. 4-39). In the presence of even relatively weak bases, the ICA decarboxylates readily via an indenyl anion to the two indene isomers (Fig. 4-39, V + VI, V + VII), which act as strong dissolution inhibitors (Vollenbroek et al., 1989a). The photochemistry described above is valid for both the 2, I-DNQ5-sulfonates and the 2, I-DNQ-4-sulfonates (Vollenbroek et al., 1989a, b). However, their corresponding ICAs may react quite differently under certain conditions. ICAs of 2, I-DNQ-4-sulfonate esters easily hydrolyze to the strongly acidic 1H-indene-3carboxylic acid- I-sulfonic acids, and to the free phenols (Fig. 4-40). This acid-catalyzed hydrolysis proceeds via an elimination-addition mechanism involving a sulfene intermediate (Buhr et al., 1989b). This elimination reaction will not occur with ICAs from 2,l-DNQ-5-sulfonates, as the formation of the corresponding sulfene would be energetically highly unfavorable. 2,l -DNQ-5-sulfonates of 2,3,4-trihydroxybenzophenone are the standard PACs for

g-line resists, e.g. Shipley Microposit 1300 and 1400, OCG WX-I 18, Tokyo Ohka TSMR series or Hoechst AZ 1300 and 4000 series. Occasionally, PACs derived from monofunctional phenols are employed, as

1 -NP

I S03R

(v)

I S03R

(VI)

SO3R

(VI/)

Figure 4-39. Possible sidereactions of 2,l-DNQ-5sulfonates.

21 8

4 Photolithography

. ROH

OH C

+HzO OH

t -

o=s=o

Figure 4-40. Product formation troni 7.1 -DNQ-Isulfonate\

the cumylphenol 2.1 -DNQ-5-sulfonate in Shipley Microposit 1 1 1 and OCG HPR 204 (Reiser, 1989). while MacDermid PR 1024, or OCG 895i employ partially esterified phenol oligomers. As a rule of thumb, polyfunctional PACs have better dissolution inhibition properties and contribute to a distinct resist contrast enhancement effect. Recently, Trefonas and Mack (1991) have published a plausible explanation for this so-called poly photolysis effect. To take practical advantage of this effect, multifunctional hydroxy-benzophenones are used as ballast compounds. The fully reacted DNQ derivatives are only sparingly soluble and tend to precipitate upon storage. This is the reason why, in technical PAC s y n t he s i s , subst ochio me t ric educt amounts are often applied, resulting in the formation of a complex product mix (Kishimura et ai., 1989). An excellent review on the chemistry and physics of DNQ-based resists has been given by Dammel (1993) recently. For DUV exposure g-line or i-line resist materials are less suitable, because their absorbence is too high below 300 nm to allow uniform illumination within the whole re-

sist cross-section. The first suitable dissolution inhibitor for DUV exposure was developed at IBM in the early 1980s. It was found that diazo derivatives of Meldrum's acid, a cycloaliphatic compound, exhibit high absorbence at 254 nm and undergo a Wolff rearrangement to yield volatile photoproducts (Reiser, 1989). These PACs effectively inhibit the dissolution of novolak resins, but tend to evaporate during the soft bake. A more promising approach is based on a-diazo-P-ketoesters as DUV-sensitive PACs. Suitable multifunctional derivatives have been prepared with effective dissolution inhibition ability for DUV transparent styrene-co-maleimide or PHS type binders (Sugiyama et al., 1989; Pawlowski et al., 1 9 9 0 ~ )A. diazoacetoacetate bound to polyvinylphenol is used by Jagannathan et al. (1994) in a DUV resist with wide process latitudes. In this case the the carboxylic acid generated upon exposure deprotects acid-labile groups bound to a second polymer backbone. Newer additions include the use of diazocoumarins as PAC (Willson et al., 1997). 4.4.3.1.2 Alkaline Soluble Polymers The empirical work of the last thirty years has clearly proven that novolaks, condensation products of phenolic derivatives with formaldehyde, are the best selection as resins for DNQ-based resists. The condensation is catalyzed by acids and yields low molecular weight oligomers with 8 to 25 phenolic units linked by methylene groups (Fig. 4-41) to give a molecular weight of 600-3000 mu (Reiser, 1989). The acidic phenol groups render the polymers soluble in aqueous bases. As a typical example, a mixture of m- and p-cresol isomers, formaldehyde and oxalic acid as the catalyst are heated. With increasing temperature, water formed during condensation is removed: the oxalic acid de-

4.4 Photoresists

CH20

H+

H20

composes to carbon dioxide, and finally pure novolak resin remains. Although this procedure looks simple, batch-to-batch reproducibility of novolak formation is very poor, and therefore blends of different batches are normally used to provide the required resist uniformity. The exclusion of any metal-ion contamination is a major target of novolak producers (Asaumi et al., 1991). Lithographically useful novolaks are made from meta-cresol with smaller amounts of para-cresol or certain xylenols, which give the polymer appropriate solubility properties in organic solvents. When meta-cresol with its three reactive sites is employed, the formaldehyde has to be added substochiometrically to obtain linear polymers; otherwise branched or crosslinked

H*C+OH + H ~ O

219

Figure 4-41. Chemistry of cresol novolak formation.

resins will result (Noguchi and Hiderni, 1991). This difficult-to-control reaction does not occur if para-cresol is used. Unfortunately, novolaks with a high para-cresol content are less useful, as they have unacceptably low glass transition points and process latitudes (Fig. 4-42a). The use of the different phenols rapidly increases the numbers of structural isomers, which all contribute differently to the resist performance, e.g. contrast, sensitivity and process latitudes (Honda et al., 1991 and Hanabata et al., 1991). metaCresol novolaks with highly regular ortho methylene bonds (high S4 ratio) show a significant decrease of the DR, possibly due to thermally induced coupling reactions with the DNQ during the PEB (Fig. 4-39,II).This

220

4 Photolithography

does not occur i n the exposed resist, resulting in an improved contrast and enhanced exposure latitude. without sensitivity losses (Fig. 4-42b; Hanabata et al., 1989). Besides the novolak isomeric structure, increasing molecular weights of otherwise identical resins decrease the overall D R and the resist sensitivity. but neither the contrast, nor the exposure latitude are influenced (Fig. 4-42c: Hanabata et al., 1989). A narrow molecular weight distribution without low molecular weight fragments improves thermal stability and image resolution. Based on these observations, Hanabata and coworkers proposed the stone wall model of resist dissolution: the low molecular weight fragments are small stones in a wall, which are readily washed out during development giving rise to a steadily growing r e s i d d e veloper interface area. After a certain penetration time, the resist structure collapses under formation of separate lumps, which are easily solubilized (Hanabata et al., 1991). In contrast to solvent developable resists, DNQ-novolak based resists do not swell during their development with aqueousbased developers. Kinetic studies revealed that the dissolution rate is influenced by the size of the base cations and the secondary structure of the novolak resin, in particular by the relative configuration of the phenolic groups (Reiser. 1989; Dammel, 1993). A comprehensive overview on the dissolution characteristics of DNQ-novolak resists (perlocation model of novolak dissolution) has been given by Reiser et al. (1996) recently. Novolaks are transparent above 300 nm (Fig. 4-30) and exhibit glass transition temperatures ( T G ) in a range of 70 to 140°C (Khanna et al., 1991). High TCs (hard bake deformation temperature) can be correlated with improved dry etch resistance (Joubert et al., 1993). Many attempts have been made

0.50

10/0

Q/l

8/2

7/3 m/P

6/4

5/5

4/6

1.25

m/p

= 1o/o S 4 = 14 - 15

- 1.009

- 0.75 4

53 m

0.50

$P W

5000

10000

15000

20000

25000

Moleculare weight

Figure 4-42. Effect of A: metalpara-cresol ratio, B: ortho/para link configuration ratio (S4), and C: molecular weight on contrast and exposure latitude. (Reproduced after Hanabata et al., 1986.)

4.4 Photoresists

to replace novolaks by new polymers to extend the applicability of DNQ resists. Due to their improved transparency in the DUV region and TGs up to 180 "C, poly(4-hydroxystyrene) (PHS) and copolymers thereof have received much attention (Pawlowski et al., 1990a). The film forming properties (Toriumi et al., 1991) and the unusual dissolution behaviour of PHS in aqueous-alkaline developers (Long and Rodriguez, 1991) have been investigated in detail. Its DR in standard MIF developers (2.38% of TMAH) is about 20 pm/min compared to 0.3 to 3 p d m i n for novolaks, which is far too much to delineate well defined relief images. PHS polymers have been modified with hydrophobic groups (Pawlowski et al., 1990a; McKean et al., 1990), which act as internal dissolution inhibitors to the attacking developer and make these materials promising for DUV resists. There are significant differences between, for example, DNQ-novolak and DNQ/PHS resists: while the former are inhibited by even small PAC-loadings, the latter are not. This experimental result suggests that there are links between the inhibitor and the polymer matrix. Depending on the secondary molecular structure, the hydrophilic groups may arrange themselves into more closed intramolecular, or more open intermolecular, hydrophilic assemblies. These assemblies may act as diffusion channels for the attack of the developer (Yeh et al., 1992; Dammel, 1993). The position of the hydroxy group in polyvinylphenols has a large effect on the dissolution rate. While the 2-hydroxy isomer is too slow and the 4-hydroxy isomer too fast for use in DNQ resists, the copolymerization of both allows one to choose any dissolution rate between the extremes (Dammel et al., 1994). The thermal flow resistance of such a 1 : 1copolymer resist was found to be improved over that of novolak resists.

22 1

DNQ resists based on aromatic poly-ortho-hydroxyamides with good lithographic performance have been introduced as photopatternable interlayer dielectric for multilayer electronic devices. These polyamides show comparable dissolution inhibition/ promotion characteristics in alkaline developers like novolaks, but by heating the developed resist pattern up to 350 "C the polymer converts into a high temperature stable polybenzoxazole with good dielectrical properties (Sezi et al., 1994; Sezi et al., 1999). 4.4.3.2 Acid- Catalyzed Deblocking

Conventional DNQ-resists exhibit only moderate photosensitivity and thus relatively poor production economics. With the present switch from NUV to DUV lithography required to print sub-quarter micrometer features, DNQ-based resists are no longer acceptable due to their high opacity below 300 nm. Furthermore, DUV irradiation tools provide only low photon densities due to their extreme spectral narrowing. This makes conventional resists far too slow to give meaningful device yields: resist sensitivity has become an increasingly important issue. New materials based on radiation-induced deprotection reactions and polarity changes of certain acid sensitive polymers meet these challenges (Fig. 4-43). The benefits of such systems for microlithography were first recognized by Ito, Willson, and Frechet (It0 et al., 1987), who introduced the concept of chemical amplification (CA) and called materials of that type chemically amplified resist (CAR). Positive CARS contain at least a photoacid generator (PAG) (compare Sec. 4.4.2.3), and a polymer with acid labile, hydrophobic protecting groups. Upon exposure, the photogenerated acid molecules induce a thermally catalyzed cleavage of the acid

222

4 Photolithography

Exposure

Acid generalion

Post exposure bake 7)-

-(-

Alkaline

Solvent

Acid catalyzed deblocking

Lv C& development

- ( / - )

0-C-CH3

3 I

CH3 C-CHs

COP

CH/

Figure 4-43. CAR concept: process flow of t-BOC protected positive resists

labile groups. A sophisticated design concept allows for regeneration of the photoacid during the deblocking sequence, and thus one single molecule can induce a cataract of cleavage reactions, providing a gain mechanism to overcome the sensitivity limitations imposed by the quantum efficiency of the photochemical event. The usually more polar degradation/deprotection products cause the exposed resist to be soluble in an aqueous alkaline developer (Reichmanis et al., 1992). According to the number of active components i n the resist, twoand three-component chemically amplified systems are distinguished. Ttoo- Cornpoi1 en t Resists

As implicated by the nomenclature, chemically amplified two component resists consist of two active resist components dissolved in a solvent, namely, a polymer masked with acid-sensitive protecting groups and a photoacid generator. According to the energy required for the deprotection reaction, three classes are distin-

guished: low activation energy (LAE) systems (E,<25 kcal/mol), such as silylethers, ketals or acetals, medium (MAE) activation energy systems (E,-25-30 kcal/mol), such as carbonates, and high activation energy (HAE) systems (E,>30 kcal/mol), such as carboxylic acid esters, or ethers. The first commercially accepted chemically amplified resist material was developed by IBM (APEX series) and is based on the acid induced cleavage of PBOCST (Fig. 4-43). a poly-(4-hydroxystyrene) blocked with r-butyloxycarbonyl (t-BOC) groups (Willson et al., 1990). The photolytically produced acid molecules cleave the carbonate moieties (re)generating the alkali-soluble PHS resin as well as the volatile byproducts of carbon dioxide and isobutene upon application of a PEB at approx. 100°C (MAE system) (Sturtevant et al., 1992). The reaction does not require the presence of water and works equally well under the high vacuum conditions required during electron-beam exposure. The intermediately formed t-butyl cation stabilizes to isobutene, and liberates a new proton, which is

4.4 Photoresists

capable of inducing the next cleavage reaction, The early PBOCST materials were 100% protected. It turned out, however, that a protection degree of 15-35% is sufficient to render the PHS polymer insoluble in the standard MIF developers and additionally improve certain lithographic properties, such as contrast and image stability. While pure, fully t-BOC blocked PHS resins are thermally stable up to 190°C (Reiser, 1989), partially blocked materials decompose at lower temperatures due to an autocatalytic deprotection reaction caused by the presence of acidic phenol groups in the polymer. The catalytic chain length for the deprotection reaction of t-BOC based resists varies from 10 for methane sulfonic acid, through 200 for toluene sulfonic acid to 8.000 for trifluoromethane sulfonic acid (Houlihan et al., 1991), with an acid diffusion radius of less than 5 nm (McKean et al., 1989). These acid parameters have tremendous effects on the resist performance and need careful adjustment (Hashimoto et al., 1997). The selection of non-nucleophilic acids is mandatory for t-BOC chemistry, as nucleophilic acids, such as hydrochloric acid, fail to deblock the t-BOC groups via a catalytic mechanism. Ota et al. (1994) have reported that the intermediate t-butyl cations may alkylate the aromatic rings of the polymer in a competitive reaction to the desired isobutene formation and thus deteriorate the dissolution rate in the exposed areas. PBOCSTsystems behave as a dual tone resist (Fig. 4-43). The negative process with anisol as developer was employed to manufacture 1 Mbit DRAMS via DUV lithography (Maltabes et al., 1990), while the positive one has been investigated for 0.35 mm patterning (Brunsvold et al., 1993a). Several modifications of PBOCST resins have been reported, including t-BOC protected poly(hydroxypheny1 methacrylates)

223

(Przybilla et al., 1991), hydroxystyrene sulfone copolymers (Reichmanis et al., 1991), or the more recently developed hydroxystyrene vinyllactame copolymers (Kim et al., 1997). Although PBOCST materials have several limits in lithographic performance and even some severe shortcomings with respect to delay stability (Nalamasu et a]., 1991), they are still used in state-of-the-art 0.25 pm production processes (Amblard et a]., 1997). More recently developed t-BOC based resist formulations are less susceptible to these problems. A large number of alternative protecting groups has been proposed to block phenolic polymers. Among these, acetal protected PHS resists have received wide commercial interest due to their excellent resolution capabilities (Endo et al., 1991; Pawlowski, 1996). The acetal bond is formed by the reaction of PHS with vinylethers such as ethylvinylether (EVE-PHS, Fig. 4-44) or tetrahydropyran (THP, Fig. 4-44). The activation energy required for the acid-catalyzed acetal deprotection reaction is lower than that for t-BOC material and image formation may occur at room temperature (LAE system). However, completion of the reaction is usually achieved during a postexposure bake at 90°C. Acetal-based resists work well with less powerful acids, such as methane sulfonic acid generated from pyrogallol tris methane sulfonate (PTMS) as the photo acidgenerator(Uen0et al., 1991; Hattori et al., 1993), and require stoichiometric amounts of water for accurate image formation. The polymers exhibit excellent transparency at 248 nm (<0.15 pm-’), but their TGis rather low. The diffusion ranges of two different acids (CH,SO,H; HPF,) in a THPblocked PHS CAR as a function of bake conditions were studied by Schlegel et al. (1991). High prebake temperatures reduce the diffusion range as the polymer matrix

224

4 Photolithography

solidifies. The mobility of CH,SO,H was found to be lower, resulting in superior images. Alternative THP-blocked polymers reported in the literature are hydroxy-polyimides (Omote et al.. 1992) and polymethacrylates partially esterified with benzylalcohol (Taylor et al., 1991) or with the 193 nm-transparent tricyclodecanol (Nakano et al., 1994). Acetal-based two component resists have been steadily refined in recent years with respect to the polymer properties, such as molecular weight, polydispersity, protection group. and PAC selection (Houlihan et al., 1997a).Recent materials offer excellent imaging properties with respect to resolution and process stability (Spiess et al., 1998) and are considered major candidates for 0.18 ym DUV lithography. In addition, they provide excellent compatibility with electron- and ion-beam lithography (Novembre et al., 1996; Hudek et al.. 1997). A solution to the TG issue of acetal-based resists is the incorporation of acid-labile crosslinks into the polymer (Taguchi et al., 1995: Schacht et al., 1997). An increase of the thermal flow stability by 30°C to approximately 150 "C while keeping the basic lithographic performance was demonstrated using this approach (Bantu et al., 1997). Schwalm and coworkers (1990) have used t-BOC blocked. phenolic sidegroups containing sulfonium salts acting simultaneously as photolytic acid generators and as acid-cleavable dissolution inhibitors in the highly transparent THP-PHS polymer matrix for their resist called SUCCESS (sulfonium compounds containing expellable sophisticated sidegroups). Although not fully compatible with standard processes, this resist series was considered a performance leader for a time of the best (Schwalm et al., 1994), and the SUCCESS concept is the basis for some of the best performing resist materials.

A class of protection groups requiring high activation energy (HAE system) is based on certain phenol ethers, such as allyl, benzyl, or t-butyl ethers (Ohnishi et al., 198 1 ). Although no commercial examples of pure ether protected PHS based resists are known today, some materials take advantage of mixed acetallt-butyl ether groups to improve certain lithographic properties. An important extension of PHS chemistry has been achieved with the introduction of novel co-monomers offering wider flexibility with respect to the protecting group selection. Particularly useful are (meth)acrylic acid esters obtained from t-butyl-, amyl-, or benzyl alcohol derivatives (Allen et al., 1993 a). The image discrimination is based on the polarity change caused by the de-esterification of the carboxylic acid esters. The original ESCAP material (Fig. 4-44) developed by IBM contained approximately 70% 4-hydroxystyrene units to achieve compatibility with standard development processes and 30% acid sensitive t-butyl(meth)acrylate groups (Ito et al., 1994). As the relatively high contents of aliphatic units deteriorate the resist's etch stability, improved versions using terpolymers with reduced t-butylacrylate loading have been developed (Conley et al., 1997). The t-butylester group is thermally quite stable (HAE system) and allows prebake temperatures above the glass transition point of the resist. This densifies the polymer matrix and improves the insensitivity towards airborne base contaminants (annealing concept) (Breyta et al., 1994). Highly sensitive, dual tone materials have been designed based on t-butyl blocked poly(viny1 benzoic acid) (Ito et a]., 1987). Due to transparency issues, their use is limited to i-line lithography. Similar systems based on poly-(4-hydroxystyrene) partially reacted with r-butyl bromoacetate (Fig. 4-44) exhibit better DUV compatibility (Onishi et al., 1996).

4.4 Photoresists

l . h__c v(H+) OH

2 . A T ( - 6 0 - 110°C)

% 00

H + n H,C+

H 3 c y H OH

O-Rq

OH CH3CHO

EVE-PHS (LAE system, R1 = C2H5, C3H7, etc.)

+ RICH

THP-PHS ( M E system)

CH3 + n H,C+

+nco,

PBOCST (APEX E, MAE system, R1= CH3, C2H5)

ESCAP (HAE system, R1 = CH3, C2H5)

2.A T ( - 90 - 130°C)

PBOCMOST (HAE system, R1= CH3, C2H5)

Figure 4-44. Acid catalyzed cleavage reactions useful in DUV lithography

225

226

4 Photolithography

Even though industry standards with respect to DUV resist performance have not been settled yet, quite a few commercial and precommercial materials are available on the market. Commercially promoted positive tone resists include APEX and KrF-K materials (Shipley, Japan Synthetic Rubber) using r-BOC chemistry, AZ DX, PEK. TDUR, ARCH, and KrF-R materials (Clariant, Sumitomo. Tokyo Ohka, Olin Microelectronic Materials, Japan Synthetic Rubber) using acetal chemistry. and UV and KrF-M materials (Shipley, Japan Synthetic Rubber) using r-butylester chemistry. A detailed performance comparison study between t-BOC. acetal and r-butylester type resists has recently been published by Lai et al. (1997).

hyde produced upon acetal cleavage crosslinks with the polymer and deteriorates the image contrast (Ito et al., 1991). More recently, however, three-component systems have regained attention in the design of practical chemically amplified resists. Major changes from the first generation materials include the switch from inactive polymers to the acid-sensitive polymers described in the previous chapter and novel, more sophisticated dissolution inhibitors. Such combinations improve the resolution capability. usable depth-of-focus range, and pattern shape accuracy. In fact, several state-of-the-art resist materials use mixtures of these polymers with additional dissolution inhibitors as provided from Tokyo Ohka. ShinEtsu and Clariant.

Three - Coinpoiz ~ ir S!Ssteiiis i

Issues in Chemically Amplified Resist

Three-component systems consist of a film-forming polymer (FFP). a photoacid generator, and a monomolecular or oligomer acid sensitive dissolution inhibitor, which is cleaved to a dissolution promoter upon the action of acid. Due to separation of the functions. three-component materials principally offer a broader chemical flexibility compared with two-component systems. Early examples used inactive FFPs, such as alkylated poly-(4-hydroxystyrene) together with t-butyl carbonates of phenols (McKean et al.. 1988: Aoai et al., 1994). r-butyl esters (Allen et al.. 1993A), vinylethers (Taguchi et al., 1995), or silylethers (Schlegel et al., 1989) and a variety of acetal derivatives (Dammel et al.. 1987; Roeschert et al.. 1993b; Padmanaban et al., 1994). Acetal based three component materials gained attention in previous years but were finally discarded due to their inherent small PEB process window: when PEB temDeratures above 70°C are applied, the alde-

Systeins

The acid amplification mechanism used in the earlier-described novel materials has resulted in considerable improvements with respect to photospeed, resolution capability, and other important performance properties. However, some inherent hurdles had to be overcome to allow their reliable use in a cost- and yield-orientated production environment. These problems are closely related to the photocatalytic mechanism, the relatively small amount of acid produced, and the acid diffusion properties in chemically amplified resist systems. Some of these problems include: storage stability, delay time stability, sensitivity to airborne contaminants, substrate sensitivity (He et al., 1997), linewidth stability, proximity effects, such as iso/dense bias or linewidth shortening (Ziegler et al., 1997), standing wave formation,

4 . 4 Photoresists -

process temperature sensitivity, and outgassing of volatile resist components.

All chemically amplified positive resists are more or less sensitive to these effects; to a first approximation, selection of the polymer material and the type of generated acid may increase or decrease their perception. The resist vendors have developed additional proprietary methods to minimize these effects, usually via the selection of optimized process conditions and resist components, or special resist additives. In addition, the equipment manufacturers have provided sophisticated tools, such as temperature control or air filtration devices, and highly accurate hotplates, to ensure constant process conditions and environments at their extremes. A critical point is the image stability of chemically amplified materials during the various process steps (Fig. 4-45). Most at-

Time sequence:

227

tention has been directed to the delay between exposure and post exposure bake, which significantly degrades the latent image, the photosensitivity, and the pattern linewidth. These effects intensify as the delay time is increased and may result in a loss of small lines or total failure of image formation. Schwartzkopf et al. (1991) have summarized the following causes for latent image instability in PBOCST onium salt resists:

- depletion of onium salt concentration at the resist surface during spin-coating, - loss of generated photoacid at the top of the resist by volatilization or migration, - contamination of the resist surface by ambient cleanroom air, resulting in neutralization of the photoacid, and - migration of base insoluble photoproducts towards the resist surface.

Reaction:

Effect:

Dark reaction

Shelf-life degradation (photospeed change, viscosity change, particle formation)

Absorption of base contaminants

T-top formation

Absorption of base contaminants

T-top formation

Bottling of resist

Spin Coating

Softbake

Exposure

Formation of acid Diffusion of acid Absorption of base contaminants Evaporation of acid Cleavage of acid sensitive groups (Evaporation of cleavage products)

Tool contamination

Diffusion of acid Evaporation of clevage products Evaporation of acid

Linewidth change Film thickness & CD loss, tool contamination Tool contamination

Lindwidth change T-top formation Tool contamination

Post exposure bake

Figure 4-45. Delay time effects in chemically amplified positive resists.

228

4 Photolithography

For the superacids produced by onium salts, virtually every compound is regarded as a base capable of neutralizing the acid. Amine concentrations in the ppb range were found to cause an insoluble skin at the top of the resist (Nalamasu et al., 1991), resulting in the T-shaped pattern profiles which can bring about complete bridging of the patterns after a few minutes (Fig. 4-46). Therefore PBOCST systems require an amine-free atmosphere for their proper function, which was achieved by filtering air through activated charcoal filters, yielding a stable manufacturing process (MacDonald et al., 1993). Another method to improve the latent image stability is the application of a protecting overcoat with the inherent disadvantage of a multi layer arrangement (Kumada et al., 1993; Oikawa et al., 1993), or the use of environmental lithographic chambers (Reichmanis et al.. 1992; Holmes et al., 1993). Ito et al. (1993) observed that the meta isomer with a TG below the prebake temperature is much less sensitive to NMP contamination than para PBOCST leading to the general concept of resist annealing. Other countermeasures include the addition of bases or photosensitive base gener-

ating compounds (resist poisoning) to the resist formulation (Roeschert et al., 1993b; Przybilla et al., 1993). Such additives also improve the contrast of the resist material. The use of extremely acid-labile protection groups, such as ketals, gives the resist environmental stability comparable to that of DNQ resists (Huang et al., 1994) as image formation proceeds during the exposure event. However, the ease of deprotection causes resist storage stability issues, which have not yet been solved. A tremendous amount of work has been dedicated towards the understanding of the mechanisms operative in chemically amplified resists by various academic and industrial working groups (Kamon et al., 1997; Itani et al., 1988). It is evident, however, that the complexity of these systems will prohibit the development of'a universal description concept. It is worthwhile mentioning that additional issues have arisen from the rapid trend to print smaller features. While the industry's CD average is clearly above 0.6 pm, the most advanced gate applications require C D control for design rules below 0.15 pm. In practice, such geometries are printed in the same production environment.

Figure 4-46. SEM picture of a resist with strong T-top formation.

4 . 4 Photoresists

This translates into mix-and-match lithography using different resist chemistries and thus requires strict cross contamination control and full compatibility with previously introduced standard processes and process chemicals. With the decreasing pattern sizes, CD control becomes an important issue, requiring extremely tight photospeed control and lot-to-lot consistency of resist materials. An increasing list of metal ion contaminants at concentrations below the 10 ppb range have to be consistently monitored, and the requirements for numbers and ultimate sizes of defects have already surpassed current detection capabilities. Resists for 193-nm Lithography

According to the U. S. National Technology Roadmap for Semiconductors (NTRS) periodically provided by the Semiconductor Industry Association (SIA), ArF (193 nm) lithography is likely to be employed for the

229

delineation of features 0.15 pm and below (Brown, 1995). From the photoresists point of view, this technology change poses new, but “deja-vu’’ challenges to the materials: the development of a single layer resist with enhanced photospeed to minimize lens heating and destruction, improved etch resistance to allow the application of thin films, and adjusted thermal and hydrophilic properties to guarantee compatibility with established industry processes. Previously used polymers with etch-stability providing aromatic units, such as PHS, are ruled out due to their insufficient transparency at 193 nm (Fig. 4-30; Sec. 4.4.4.2). The first materials to meet at least part of these requirements were CARS, developed by IBM using aliphatic polyacrylates with acid cleavable t-butylacrylate units (Version 1 .O & Version 2.0 resists) (Allen et al., 1991). While their lithographic performance was found adequate, both process compatibility and etch resistance of these materials did not meet the requirements (Fig. 4-47).

RE,= -3.80r3 + 6.71r2 - 4.42r + 2.10

Non-imageable cycloaliphatic 1

100

Ring parameter r Figure 4-47. Correlation between the ring parameter r and empirical etch rates of several resists relative to standard DNQhovolak resists.

230

4 Photolithography

O.N. = Ntotal/N,- No

According to an empirical law discovered by Ohnishi, the RIE etch resistance of a polymer is proportional to the Ohnishi Number O.N. which is defined as the quotient of the number of atoms in a polymer repeat unit and the difference between the number of carbon and oxygen atoms (Ohnishi et al., 1981: Eq. (4-8)).

More recently, Kunz et al. (1996) introduced the ring parameter r , given in Eq. (4-9), to describe the RIE etch resistance more accurately. r =mass of carbon in rings/

total mass of carbon

‘C H3 IBM Verslon 1.O resst: Poly-(methyl methacrylate-co-rnethacrylylicacid-co-t-butyl methacrylate)

%i!-ti! 1 . hv (H’ )

Fu1itsulCiarianWNtppon Zeon: Poly-(2-methyladamantyl acrylate-cemevalonic lactone acrylate)

‘cH3 LucenWOlin EM: Poly-(no~mene-a/t-maleicanhydride-ceacrylk add-co-t-butyl acrylate)

-yJxp 1%) 2 AT

CH3

(4-8)

C Y H2C4 CH3 Univenity Austin Poly-(t-butoxycarbonyInorbornadme-alt-malic anhydnde)

Tiy3

Figure 4-48. Chemical approaches to 193 nm polymerh.

(4-9)

4 . 4 Photoresists

Researchers at Fujitsu included highly transparent alicyclic comonomers, such as isobornyl methacrylate, to increase the etch stability (Kaimoto et al., 1992), initiating the rapid evolution of alternative materials with improved overall performance (Fig. 4-48). An incomplete list of materials with the potential to find use in a production environment includes -

methacrylate based co- and terpolymers bearing alicyclic etch resistant menthyl (Shida et al., 1996), adamantyl (Takahashi et al., 1995), or tricyclodecyl units (Nakano et al., 1995), methacrylate based co- and terpolymers bearing etch resistant and solubility modifying tricyclodecyl, or tetracyclodecyl units with integrated partially protected carboxylic acid functions (Maeda et al., 1997),

231

- methacrylate based co- and terpolymers

with alicyclic etch resistant acid-cleavable 2-methyl adamantyl groups (Takechi et al., 1996), norbornene/maleic acid anhydride copolymers (Wallow et al., 1996). norbornene/maleic acid anhydride copolymers with cholate based dissolution inhibitors (Houlihan et al., 1997b), and nonacrylic copolymers (Allen et al., 1996; Okoroanyanwu et al., 1997)

Particularly interesting is the approach first used by Fujitsu, based on a copolymer of 2methyladamatyl methacrylate and mevalonic lactone methacrylate as polymer and an iodonium salt derived PAG. Both pendant groups are cleaved by the action of the acid. The material combines high photospeed (3 mJ/cm2), high resolution (0.12 pm) and excellent etch stability with industry standard 0.26 NTMAH developer compatibility (Fig. 4-49).

Formulation 1, Lot 10; 0.48 pm on 180 nm AZ BARLi II; SB 115 "C, 60 s; focus 0.0; 193 nm, 0.60 NA; PEB 110 "C, 60 s; LD26W developer, 20 s spray/puddle at 23 "C Figure 4-49. SEM pictures of an experimental ArF resist on basis poly-(2-methyladamatyl methacrylate-co-mevalonic lactone methacrylate).

232

4 Photolithography

Unfortunately, the mevalonic lactone acrylates are difficult to prepare driving the materials costs to unacceptable levels. 4.4.3.3 Poly rn er Degradation With a few exceptions. NUV radiation is not capable of cleaving thermally stable CJ bonds in organic molecules, because the average bond energy is about 350 kJ/mole. corresponding to photons of 340 nm wavelength. DUV radiation is able to break molecule bonds and photochemists have discovered several materials. which undergo lithographically useful scission reactions to provide positive-tone images. Poly(methy1 methacrylate) (PMMA) is a positive-tone chain scission resist with excellent resolution capability when irradiated with broadband DUV (240- 260 nm), KrF excimer laser (248 nm), or ArF excimer laser ( I93 nm) radiation (Reiser. 1989; Sasago et al. 1991). Initially. a Norrish type I reaction occurs, which is followed by main chain scissions. Small molecule fragments, including carbon monoxide or dioxide as well as methyl or methoxy radicals. are formed, while the intermediates stabilizes under formation of unsaturated, low molecular weight fragments (Fig. 4-50; Reiser, 1989). The cleavage of PMMA proceeds only inefficiently: high doses (> 1000 mJ/cm’) are

Figure 4-50. Photoreaction of PMMA

required to obtain adequate dissolution speed (Nakase, 1987). PMMA has several benefits as DUV resist (Wolf et a]., 1987), including excellent resolution capability, ease of handling, good film forming properties, wide process latitude, and low price. I n a 500 mm thick PMMA resist, patterns with nearly vertical sidewall profiles have been printed with XRL (Rogner et al., 1993). However, its low sensitivity is barely acceptable. The efficiency of the cleavage reaction is increased ( - 80 mJ/cm’) when the DUV absorption is intensified by copolymerization with 3-oximino-2-butanone methacrylate or by addition of r-butyl benzoic acid as a photosensitizer (Reiser, 1989). Polymers of polybutene sulfone (Thompson et al., 1983) or poly(methy1 glutarimide) (PMGI) are also scissionable with DUV radiation. The photospeed of PMGI is comparable to PMMA, but, due to its imide groups, it is developable with aqueous bases, has better dry etch resistance, and a high glass transition point (> l8O0C), making PMGI useful as planarizing layer for multi-layer schemes (Reiser, 1989). In addition to PMMA, poly(methy1 isopropenyl ketone) (PMIPK) based resists, commercialized by Tokyo Ohka under the trade name ODUR 1010, are widely investigated as photoscissionable one-component resists (Hesp et al., 1990). All of these mainly aliphatic materials show poor dry etch resistance which limits their application. The principle of chemical amplification can also be applied to polymers which undergo main chain scission (Frechet et al., 1989). Polycarbonates derived from tertiary diols and certain diphenols are degraded i n the presence of a PAG and by exposure to DUV (Fig. 4-5 1 ; Reiser, 1989). During development, advantage is taken of the higher DR of the degraded polymer fragments versus the intact polymer to

4.4 Photoresists

1 hV, PAG 2. kT

mLJ J&b2=&o+cop H+ CH3

Figure 4-51. Photoreaction of main-chain degradable polycarbonates.

generate a positive image. The degradation concept has been extended to generate positive resists using polyacetals, polyazomethines, polyethers and polyesters with acid-cleavable bonds in their main chains (FrCchet et al., 1989, 1990; lto and Schwalm, 1989).

4.4.4 Solvents for Photoresists and Main Resist Suppliers Photoresist materials for IC manufacture are usually sold as thoroughly filtered ( ~ 0 . pm) 2 liquid solutions (liquid photoresists) in organic solvents, which have pronounced effects on certain photoresist properties, such as photospeed, coating uniformity and thermal flow behaviour (Salamy et al., 1990). The ideal solvent is non-toxic and non-hazardous (safer solvents; Boggs, 1989). Examples include 2-heptanone, cyclopentanone, cyclohexanone, 3-methoxybutyl acetate, propylene glycol monomethylether or its acetate, propylene glycol diacetate, ethyl lactate, ethylene carbonate, ethyl 3-ethoxypropionate and ethylpyruvate (Hurditch and Daraktchiev, 1994). The main resist suppliers are Tokyo Ohka, OEM (Olin Electronic Materials), Shipley (Rohm & Haas), Clariant, Sumitom0 Chemical, Nippon Zeon, Japan Synthetic Rubber, Mitsubishi Chemical, Shinetsu, and others (Gutmann et al., 1990 a and

233

SST tabulation, 1993). The field of advanced g-, i-line and DUV resists is highly competitive and rapidly changing. In 1990 the authors believed that the resolution limits of DNQ-novolak resists had been reached with the performance obtained by the Tokyo Ohka g-line material TSMR-V3: 0.4 y m lines and spaces with vertical sidewall profiles were printed with a 0.54 NA stepper in a 1.26 pm thick resist (Satoh et al, 1989). This performance is now beyond standard for the last generation g-line resists. Today, i-line resists are available with an ultimate resolution <0.25 ym lines and spaces (Fig. 4-52), the capability to print 0.30 pm contact holes (e.g., Sumitomo Chemical PFI-66, Japan Synthetic Rubber PFR IX 1010, Hoechst AZ 7900, Fuji Hunt FHi-3900, OEM OiR 32, Mitsubishi Kasei MCPR i6600, Nagase NPR-Ll8SH5, Tokyo Ohka THMR-iP series, Hitachi Chemical RI-7300P), linearity better than 0.3 pm, and a focus budget > 2 . 0 pm for 0.35 pm patterns.

Figure 4-52. SEM picture of 0.25 km lines and spaces printed in JSR/UCB new high-contrast i-line resist 1x500 using the ASM-L PAS 5000/50 i-line stepper ( N A =0.48) with a Levenson type phase-shifter design. Courtesy of IMEC, Leuven, Belgium. Reproduced with permission.

234

4 Photolithography

4.5 Special Photoresist Techniques 4.5.1 Nonconventional Diazo Resist Processes 4.5.1.1 Resist Profile Modification

and Image Reversal The perpetual drive to improve the performance of existent DNQ-novolak resists has stimulated research into advanced process schemes. Additional processing steps and modification of the basic chemistry have resulted in variants capable of producing positive and/or negative patterns. Their implementation in a production environment largely depends on the additional complexity they cause. The profile modification technique (PROMOTE) offers the capability of producing positive images with variable profile angles (Vollenbroek et al., 1991). The resist is irradiated (NUV) through a mask to yield the latent positive image. A DUV blanket exposure under anhydrous conditions (vacuum or elevated temperatures of approx. 100°C; f*ckumoto et al.. 1989) follows, leading to a selective crosslinking of the resist surface through PAC-resin ester linkages in the previously masked areas (Fig. 4-39 IV). Since the esterified top of the resist exhibits a low dissolution speed, overdevelopment yields negative sloped patterns suitable for lift-off processes. Positive or negative tone images are produced by the image reversal resist schemes. Originally, they were developed to improve the process latitude of DNQ resists, but the use ofthe same photoresist in either its positive or negative mode is of greater practical interest with respect to warehousing, reduction of printing defects by appropriate choice of best defect masking and control of sidewall angles. Several versions of image reversal resists have been described:

The indirect. amine-promoted image reversal process was developed by Moritz and Paal at IBM (Thompsonet al., 1983). In their first experiments 1 -hydroxyethyI-2-alkylimidazoline was added to the DNQ resist. After an imagewise NUV exposure the latent positive image can be developed (positive mode). When a bake step (image reversal bake) is inserted prior to development, the ICA decarboxylates via its ammonium salt to the parent indene derivative, which acts as an effective dissolution inhibitor (negative mode). A subsequent NUV flood exposure converts the unreacted DNQ into the corresponding ICA and enhances the developability. Useful modifications are based on diffusion of amine vapours (Alling and Stauffer, 1988), or a liquid ammonia soak (Ziger and Reighter, 1988), to provide the base catalysts. The ammonia soak process has been used for a lift-off process in fabrication of CMOS devices (Joneset al., 1988). The relevant chemistry of this base-catalyzed process is given in Fig. 4-53 (Reiser, 1989). The indirect image reversal process suffers either from low shelf life (the base is i n the resist), or from an additional soaking step. An elegant approach to image reversal resists based on a 2 , l -DNQ-4-sulfonate ester PAC and a small amount of hexamethoxymethylmelamine (HMMM) has been made available by Clariant (Spaket al., 1985), followed by similar materials from MacDermid and Shipley. This direct image reversal process proceeds according to the reaction sequence in Fig. 4-54: during the bake of the latent image, the ICA photoproduct forms the highly acidic indene, sulfonic acid, which induces the crosslinking reactions of HMMM (Buhr et al., 1989b). A subsequent NUV flood exposure solubilizes the yet unexposed regions; upon alkaline development a high quality negative image is obtained (compare: Figs. 4- 16 and 4-54).

4.5 Special Photoresist Techniques

235

Figure 4-53. Process flow and relevant chemistry of (left) the amine-promoted image reversal process and of (right) the direct image reversal (crosslinking) process (XL = unreacted crosslinker; NW = network).

Figure 4-54. Change of sidewall profile of a direct image reversal resist by variation of 1. and 2. exposure dose. (a) positive [ 1. expos.: 1.5 s, 2 . expos.: 2000 pJ/cm2], (b) vertical [ 1. expos.: 1.5 s, 2 . expos.: 1000 pJ/cm2], and (c) undercut profiles [ 1. expos.: 0.5 s, 2. expos.: 1000 fl/cm2].

This chemistry is the basis of the i-line sensitive AZ@5200 resist series. A related resist with equally good g- and i-line applicability is based on 7-methoxy substituted 2,l-DQN-4-sulfonate esters (Buhr et al., 1989b). This material resolves 0.40 pm lines and spaces with vertical sidewalls with an 0.54 N A g-line stepper (Seha and Perera, 1990). The lithographic properties of direct image reversal resists have been investigated by several groups (Gutmann et al,

1990b; Reuhman-Huisken et al., 1990), and compared with the indirect type (Grunwald et al., 1990). A key feature of image reversal resists is the potential to control the pattern profiles, e.g. vertical slopes for sub-pm etch applications, and undercut profiles for lift-off (Fig. 4-54). Another benefit is the excellent thermal stability of the patterns (> 200 " C ) and the improved linewidth control over topography (Nicolau and Dusa, 1990).

236

4 Photolithography

4.5.1.2 Bilayer Systems f o r Contrast Enhancement

ized by General Electric under the tradename Altilith. The relevant chemistry of CELs is given in Fig. 4-55. The effects of CEL materials on critical dimensions and resist behaviour over highly reflecting topography have been studied intensively (Blanc0 et al., 1987). However, layer intermixing seems to be unavoidable, if CE-layers do not consist of water-soluble bleachable diazonium salts (Endo et al., 1989) and water soluble polymers, e.g. PVA (Halle, 1985). poly(viny1 phenol) (Sakurai et al., 1988), or poly(viny1 pyrrolidone) (Uchino et al., 1988). A system with two layers of different spectral sensitivity, introduced by Lin (IBM), consists of a thick planarization layer of DUV sensitive PMMA or PMGI and a thin NUV sensitive DNQ-novolak toplayer (Lyons and Moreau, 1988; Takenaka and Todokoro, 1989), which is opaque to light below 300 nm. The top material is patternwise exposed and developed, followed by a blanket exposure with DUV radiation and a second development with an organic solvent. The process was termed portable conformable mask (PCM), as the top resist

Contrast and quality of the latent resist image can be improved by the application of a contrast enhancement layer (CEL) on top of a conventional prebaked photoresist (White and Meyerhofer, 1986). A CEL is a thin photobleachable film with high initial absorbence of the applied radiation. During illumination, the CEL is bleached , and its non-linear transmission cuts off low intensity parts of the aerial image, allowing only the high-intensity parts to pass (Fig. 4-55). After illumination. the CEL is removed either prior to, or together with the development of the photoresist. Suitable photobleachable compounds for i - and g-line sensitive CE-layers were found among the substituted diary1 nitrones (West et ai., 1988) which exhibit high extinction coefficients in the near U V ( ~ 3 000) 5 and rearrange on exposure to nonabsorbing oxaziridines ( ~ ~ 5 0 0with 0 ) quantum yields of 0.3. Unfortunately, they are somewhat unstable towards moisture (West et al., 1988). CELmaterials for g- and i-line are commercial-

CH=N+

hv A

CEL

Resist

Figure 4-55. Prows5 flow and relebani cherni\try of the CEL-technology

4.5 Special Photoresist Techniques

acts as a zero-gap in-situ mask during DUV flood illumination, resulting in a nearly ideal image transfer to the bottom layer. Mid UV sensitive CARS based on blocked poly(viny1 benzoates) as toplayer in combination with PMGI as bottom layer have been described for use as PCM (It0 et al., 1987).

4.5.2 Suppression of Reflections and Standing Wave Effects 4.5.2.1 Dyed Resists

Accurate pattern transfer is heavily degraded when metallized, highly reflective topographic substrates are imaged. The degradation of critical dimensions is caused by both thin film interference effects due to non-uniform resist thicknesses over steps as well as by light scattering from underlying patterns, known as reflective notching (Bolsen et al., 1986). According to Eq. (4-7) (Sec. 4.3.2.1), these problems are alleviated by increasing resist absorption a through the addition of dyes absorbing in the actinic

1.20

I I

1.15

-5 e ‘S

1.10 1.05 1.00

.- 0.95 -I

0.90

0.85 0.80

1.30

1.40 1.50 1.60 1.70 Resist Thickness (prn)

Figure 4-56. Simulation of CD-variations of 1 pm lines and spaces with varying resist thickness on aluminium for undyed resist, dyed resist, and undyed resist with an ARC. (Reproduced from Noelscher et al., 1989 with permission.)

237

region (Fig. 4-56). The requirements with respect to absorbence, particle generation or solubility are met by only few dyes. These include, for example, coumarin and curcumin (Cernigliaro et al., 1989), or azodyes (Cagan et al., 1989). The main trade-offs for gaining added process latitudes on topography are losses in focus latitude and generation of non-vertical sidewall profiles (Fig. 4-57) due to the increase of the non-bleachable absorption (Cagan et al., 1989). Depending on the concentration and the chemical type of the selected dye, increasing dose requirements are often observed, which made the efficiency of this approach to a subject of intensive debate in the literature (Mack, 1988). 4.5.2.2 Antireflective Layers

The use of antireflective coatings (ARCS) is an alternative concept to minimize reflective notching and CD variations caused by interference effects (Brunner, 199 1). The interest in this approach has emerged with the recent progress of DUV lithography, as it is believed that the inclusion of the ARC concepts is vital for DUV technology to become relevant to ULSI mass production (Barnes et al., 1991). The more common way is the deposition of thin sputtered inorganic films with light absorption properties on reflective substrates as bottom antireflective coatings (BARCs). A precise control of their thickness is very critical for maximum effect. Optionally, these films remain in the final device (integrated BARC). Their application introduces additional complexity and new sources of defects (Horn, 1991). Focus and exposure latitudes are significantly enhanced and become less sensitive to substrate reflectivity, resulting in a more robust process (Sethi et al., 1991; Fahey et al., 1994; Figs. 4-56 and 4-57). Anorganic

238

4 Photolithography

Figure 4-57. SEM picture$ of positive resist patterns over silicide topography for (a) undyed resist, (b) dyed resist and ( c ) undyed resist on BARC. (Reproduced from Noelscher et al., 1989 with permission.)

BARC materials can be TIN, TaN, Si,N,, a-Si, a-C : H or other layers made by chemical vapor deposition. More recently, however, the use of organic BARCs has become popular (Krisa et al., 1996). These materials are simply spincoated at an optimized FT of 50- 200 nm on the wafer and baked at high temperature to avoid intermixing with the subsequently coated photoresist. By selection of the BARC material, and depending on the need of the user, conformal or planar coating of the substrate is possible (Fig. 4-58).

Organic BARCs are less sensitive to FT variations, prevent potential contamination of sensitive devices, and bring about tremendous cost reductions as no additional deposition equipment is required. Pattern transfer to the substrate is achieved by an oxygen RIE step after photoresist development. State-of-the-art organic BARCs for NUV and DUV processes are provided by Tokyo Ohka, Brewer Science, Shipley and Clariant. Figure 4-59 demonstrates the elimination of reflective notching (hole burning) by the use of AZ BARLi.

Figure 4-58. Conformal and planar organic BARC arrangement on a topographic wafer.

4.5 Special Photoresist Techniques

239

Figure 4-59. Hole burning by accidental mirror elements. Top: without BARC, bottom: with BARC.

From inspection of Eq. (4-7) (Sec. 4.3.2. l), it is obvious that the reflectivity of the resistiair interface also contributes to thin film interference. Improvements of the CD control through the application of a top antireflective coating (TARC), which is spun on top of the resist to minimize the resistlair reflection, have been reported first by Tanaka et al. (1991 a), and later by Brunner (1991). This technique uses a thin (30- 100 nm) organic film with a matched refractive index +ARC and an optimum thickness dTARC as defined by Eq. (4-lo), where A denotes the radiation wavelength. ~ T A R C =a14 ~ T A R C

(4- 10)

The optimum refractive index of the TARC of 1.28 is only met by Teflon, or certain perfluoroalkylpolyethers (Tanaka et al.,

1991 a; Brunner, 1991), which require special coating solvents and removers, and bring severe adhesion problems. Tanaka et al. (1991 a) have reported that on silicon substrates the CD control was improved by a factor of ten. A water-soluble TARC-material has been introduced by Clariant under the tradename AZ AQUATAR (Alexander et al., 1994). Although the optimum value of the refractive index is not matched by Aquatar (1.4), its water solubility allows easy processing and avoids intermixing with the photoresist. More advanced TARCs do not require extra bake, strip or etch steps, are nonabsorbing and therefore cause no exposure penalty or degradation of photoresist contrast. Recent work has demonstrated that TARC applications bring significant im-

240

4 Photolithography

provements, such as reduction of the swing ratio by a factor of 3 , thus improving linewidth uniformity over topography, improved across-the-wafer uniformity, and a larger focus budget. However, TARCs do not eliminate reflective notching effects. Yoshino et al. (1994) compared the BARC and TARC concepts with respect to the simulated process windows in DUV lithography. The TARC has a smaller thickness latitude but it offers a wider process window for the resist. Arrangements with organic ARCS are superior to dyed resists with respect to resolution, latitudes, and linewidth control on topographic substrates, but introduce additional process complexity. Figure 4-56 compares the simulated CD variations as a function of resist thickness for a standard resist, a dyed resist, and an undyed resist with an ARC (Noelscher et al., 1989). Franzen et al. (1998) compared the costs of various lithography technologies (dyed resist, BARC and bilayer CARL resist) for a mass production target of 3000 wafer starts per week. They calculated that the Cost of Ownership value of a dyed resist is lower than for any other process in their comparison. The COO value for an integrated TiN-BARC process without removal of the antireflective layer is 42% less than that of a CARL bilayer resist process (compare 4.5.4.2) and 53% less for an ex-situ TiN-BARC process. The a-Si-process with ex-situ etch and without integrated removal of the a-Si layer in the etch process is by far the most expensive process of all the processes described here. Thus the CARL process is an interesting possibility with high capability and comparable COO value. 4.5.3 Silicon-Containing Multilayer Resists The majority of the photoresists discussed in the previous chapters was devel-

oped for use as single layer resists (SLR). From the discussion it became evident that SLRs have certain limitations: restricted aspect (i.e. height/width) ratios, limited focus budgets, sensitivity to topography and thin film interference effects, and lack of stability against aggressive etch chemicals. Together, these factors have been met only with very few high performance SLRs. A way to alleviate these obstacles is the use of multi layer resist (MLR) systems, which permit specialization of the separate layers, e.g. optimized sensitivity and resolution of the imaging layer, and adjusted dry etch resistance, optical density, and thermal stability of the bottom layer (Miller and Wallraff, 1994). With respect to e-beam lithography, problems arising from proximity, or electrostatic charging effects can be resolved by suitable MLR combinations (Moss et al., 1991). The main handicap of MLR systems is the increase of complexity involved with two or more layers, which translates into multiplying the probability of defects or unexpected aging phenomena. Moreover, MLR processing requires expensive dry etching equipment not commonly available in IC manufacture for oxygen plasmas. Single layer resists will therefore be used as long as they fulfil the respective requirements, and it is difficult to decide at what stage the incorporation of an MLR system is clearly favourable. On the other hand, new prototype devices and ASICs are often tested and manufactured using MLRs (Hatzakis et al. 1988). In reality, all techniques using an organic BARC or TARC are multilayer resist processes and, although they are often termed SLR, their complexity is comparable to MLR systems (Franzen et al., 1998). MLRs are composed of a 0.5 to 4 p m thick radiation-insensitive bottom resist, or planarizing coating, which has low resistance towards oxygen plasmas, submerges

4.5 Special Photoresist Techniques

241

the substrate topography and reduces interSpin coating of DNQ- novolak resist ference effects by light absorption at the acand hard bake (> 200 "C) tinic wavelength (Thompson et al., 1983). Examples include hard-baked DNQ-novoSpin coating of silicon lak resists, polyimides or diamond-like carcontaining top-resist bon layers (Namattsu, 1988; Leuschner et al., 1993). In a MLR scheme, a second and normally \1 hv much thinner top resist or imaging layer (0.2 1 I Exposure to 1.0 pm) is coated on top of the planarizing coating. The top layer defines the feature dimensions and is thus sensitive towards radiation. Optionally, these two layers are separated by a third layer, an in Towresist development general extremely thin ( e0.2 pm) but stable barrier layer with respect to an image transfer via dry etching (Hartney et al., 1989). It is most often selected from inorganic mateR R Oxygen RIE rials, e.g. silicon, silicon nitride and dioxide, titanium dioxide, polysilane, or spinon-glass (Hartney et al., 1989), and can be applied by either sputtering, plasma chemFigure 4-60. Typical process flow of a silicon-based bilayer resist arrangement. ical vapour deposition (PCVD), or spincoating. The use of trilayer schemes has become quite unpopular, as the increasing complexity is not usually compensated by their benefits. Therefore, the following discussion will concentrate on silicon-contain2' 300 C .= ing top resists of bilayer schemes (Miller E and Wallraff, 1994). A typical process flow > is given in Fig. 4-60. 100 + The resistance of silicon-containing polymers towards oxygen reactive ion etch4' ing (0,-RIE) is controlled by their chemi0 c 30 cal structure, and the silicon content. Dur-c 0 ing treatment with an oxygen plasma, the ii polymer surface is converted to a thin ( 5 to I I 20 nm) layer of silicon dioxide, which is 10 1 3 10 30 highly resistant towards further plasma atPercentage of silicon in the polymer tack (Hartney et al., 1989). Oxygen etch reFigure 4-61. Effect of silicon content on the etching sistance is not a linear function of the silirate of organosilicon polymers in an oxygen plasma con content (Fig. 4-61): at silicon contents at I O mTorr pressure and power=O.IS W/cm2, The above 10 to 15% it remains constant (Juretching rate is independant from the silicon position. gensen and Shaqfeh, 1989). A problem of(Reproduced from Hatzakis et al., 1988 with permisten encountered with the incorporation of sion.)

242

4 Photolithography

silicon is the low glass transition temperature of these materials, which may lead to thermal flow and lack of resolution. Moreover, hydrophilicity is reduced as the silicon content increases, which may become an issue when aqueous-based development is desired. 4.5.3.1 Negative- Tone Silicon Bilayer Resists

The first examples of lithographically useful silicon-containing negative resists were based on poly(alky1 siloxane)s, which show an oxygen etch rate ratio of 1 : 50 compared to hardbaked novolak resist (Shaw et al., 1987). They exhibit low Tc’s ( c 100°C) and tend to image-distorting thermal flow. Poly(si1methylene-) and poly(silpheny1ene si1oxane)s containing highly regular siliconcarbon and silicon-oxygen linkages in their

main chain are reported to have higher TG and e-beam sensitivities ranging from 25 pC/cm’ (Babich et al., 1989). More recently, a three-dimensional crosslinked poly(silpheny1ene siloxane) was prepared as negative-acting photoresist. It exhibits higher rigidity than conventional siloxanes, resulting in an improved contrast, minimized swelling upon development, and improved thermal stability. The addition of 2,2-dimethoxy-2-phenyl acetophenone as a photoinitiator enhanced the UV photospeed by a factor of 20 to about 20 mJ/cm2 without deterioration of the pattern profiles. 0.25 pm patterns could be delineated in a bilayer arrangement (Watanabe et al., 1991). Researchers from NTT obtained a high TGmaterial (150°C) with a partially chloromethylated poly(dipheny1 silsesquioxane) in which two chains are linked together by oxygen atoms (ladder type polysiloxanes).

-(-si-O-~-(-Si-o-)I

? (-Si-o-)-

--(-si-O-)I

CH3

SNR

Vinyl-silsesquioxane

O Q i

QQ:

-(-Si-0-)-(-Si-0-)-OH I

P -(-Si-0-)

,i-

LO”, MSNR

? (-Si-0-)-OH

APSO

Figure 4-62. Chemical structure of silsesquioxane based negative working resists.

243

4.5 Special Photoresist Techniques

The material - called silicon based negative resist (SNR, Fig. 4-62) -is sensitive towards DUV and e-beam radiation ( 5 yC/cm2) and resolves 0.5 ym patterns on a hardbaked novolak (Tamamura and Tanaka, 1987). Adequate near UV sensitivity, resolution and oxygen etch resistance were achieved using the methacrylated silicon based negative resist (MSNR, Fig. 4-62), which utilized a methacrylated poly(pheny1 silsesquioxane) as polymer and a bisazide as PAC (Morita et al., 1986). The same group from NTT applied acetylated phenylsilsesquioxane oligomers (APSQ, Fig. 4-62) as the matrix polymer for both negative and positive bilayer resists (Ban and Tanaka, 1990). APSQ, together with azidopyrenes, gives a negative working DUV and e-beam sensitive resist with good resolution (Kawai et al., 1989). In combination with onium salts, the photoacid catalyzes the condensation reaction of the silanol groups in APSQ (Ban et al., 1990). This process is accelerated by a post-bake step, and 0.3 pm negative patterns have been obtained in a bilayer scheme (Tanaka et al., 1992). A silylated poly(viny1 silsesquioxane) gives an e-beam resist (7.6 pC/cm2) with an estimated etch rate ratio of 1 : 100 compared with a hardbaked positive resist (Saito et al., 1988). A three component material with improved DUV (25 mJ/cm2) and e-beam ( 5 yC/cm2) sensitivity has been formulated from poly(pheny1 silsesquioxane), a photoacid generator, and an additional crosslinker, e,g . hexamethox ymethy lmelamine. Crosslinking probably occurs through etherbond formation. The material offers a tremendous etch latitude (Hiraoka and Yamaoka, 199 1). 4.5.3.2 Positive- Tone Silicon Bilayer Resists

As reported by Miller and Michl (1989), polysilanes are attractive-positive acting

top resists for bilayer arrangements due to their bleaching ability and Si-Si bond scission reactions. These polymers with silicon in the main chain are glassy materials with high TG’s, exhibit good solubility in common organic solvents and form films of excellent quality. Their absorption maximum is centred around 320 nm, making them especially sensitive to mid- or deep UV radiation (Wallraff et al., 1991). Upon exposure, photodegradation occurs through cleavage of the Si-Si bonds into silyl radicals and silylenes, which stabilize via hydrogen abstraction to fragmented polysilanes (Fig. 4-63). As a side reaction, photooxidation to polysiloxanes with smaller molecular weights was detected. The fragmentation is accompanied by a pronounced bleaching effect. An extensive discussion of polysilane photochemistry has been given recently (Miller and Michl, 1989). Not surprisingly, the oxygen etch resistance of polysilanes is comparable to that of polysiloxanes. A large variety of aliphatic or aromatic polysilanes together with sensitizing additives have been studied as positive-acting top resists by Miller et al. (1991) and Wallraff et al. (1991). They have spun high molecular weight materials from toluene solu-

220 100

1060 580

1.2

~ n lo3 / 0

8 mJ/c

Figure 4-63. Change in molecular weight distribution of a 0.006% solution of poly(dodecy1methylsilane) upon irradiation with 0,2,4, and 8 pJ/cm2 at 3 13 nm. (Reproduced from Miller et al., 1989 with permission.)

244

4 Photolithography

tions on I pm thick hardbaked novolak films to yield adry film thickness of 0.1 pm. Their investigations revealed that high DUV sensitivity ( 15 mJ/cm’). high resolution. and clean oxygen RIE pattern transfer are possible. As main problems remain the low yield polysilane synthesis utilizing difficult-to-handle metallic sodium or potassium (Reiser, 1989). the exclusion of metallic impurities in the resist and the contamination of the exposure tools upon self development. Synthesis problems may be overcome by plasma deposition of polysilanes and, combined with dry development, this allows an all-dry lithographic cycle (Kunz and Horn, 1991; Joubert et al., 1994). Polysilyne derivatives have been explored as photoresists for ArF (193 nm) excimer laser lithography (Kunz and Horn, 1991 ). These materials are photooxidized to polysiloxanes upon exposure to high energy radiation. Wet development using po-

Poly-(allyltrimethylsilane-sulfur dioxide)

lar solvents yields a positive image with feature sizes smaller than 0.2 pm after oxygen RIE. Gozdz et al. ( 1986) prepared a bilayer resist by the copolymerization of sulfur dioxide, butene, and allyltrimethylsilane with 13% silicon content (Fig. 4-64), high ebeam sensitivity of 2 pC/cm2 and good resolution capability. Copolymers of 4-hydroxystyrene and vinyltrimethylsilane (Fig. 4-64) are excellent candidates for aqueous alkaline developable silicon-containing near and deep UV resists, as they show high transparency at 248 nm, no thermal flow up to 150°C and good oxygen RIE resistance (Sezi et al., 1989). Positive-acting DNQbased resists with a silicon content over 10% have been prepared by condensation of formaldehyde and a phenol with a siloxane group (Noguchi et al., 1990)(Fig. 4-64). Using a g-line stepper, 0.5 mm patterns were fabricated.

Silicon containing novolak resin OH I

-(-

CH~--CH-CHZ-CH-)CH3-SI-CH~

, , ,

CH3

C k

CHz

-~-si-o-)-~-sl-o-~ 0 OH

Vinyltrirnethylsilaneihydroxystyrene copolymer

(

o-~-~-si-o-~--

CH2

/c:,

CHz , ,

\-’, 4

OH Poly-(hydroxybenzylsilsesquioxane)

Figure 4-64. Exdmples of silicon containing positive working remt material5

4.5 Special Photoresist Techniques

By acetylation of phenylsilsesquioxane oligomers, a g-line sensitive alkali developable resist with a thermal stability up to 400°C and an ultimate resolution of 0.35 pm was obtained by Tanaka et al. (1989). The alkaline soluble phenolic groups containing poly(4-hydroxybenzylsilsesquioxane) resin of Hitachi's organosilicon positive resist OSPR-1334 (Fig. 4-64), acts in combination with DNQs as i-line, or g-line sensitive, positive top resist (Sugiyama et al., 1988). OSPR contains 18% silicon, has a TG of 107"C, an 0,-RIE rate ratio to hardbaked novolak of 28 and is strippable with alkaline developers after pattern transfer (Nate et al., 1991). A t-BOC blocked resin of this type has been evaluated by Brunsvold et al. (1993b) as DUV resist for 64 MBit DRAM production. The top layer materials for the MLR systems described so far contain silicon incorporated in their polymer structures. Another approach is to add a low molecular weight poly(pheny1 silsesquioxane) to a conventional g-line DNQ-resist. This mixture is commercialized by Hitachi under the tradename RG 8500P and has a submicron resolution capability (Toriumi et al., 1987). 4.5.4 Top Surface Imaging

Surface imaging in combination with dry development by means of an oxygen plasma has been suggested as a method of overcoming the inherent limitations present in conventional wet development photolithography. The strategy is to enhance the oxygen etch resistance of a metal-free resist through selective incorporation of silicon into the latent resist image by a suitable technique during or after the exposure (Roland, 1991; Taylor et al., 1990). The advantage of this top surface imaging (TSI) technique is obvious: the formation of the silicon-containing protective layer requires only a surface

245

modification. This should result in a reduction of exposure time, and an alleviation of both the depth-of-focus and thin film interference problems, as multilayer performance can be obtained with a single layer resist process. 4.5.4.1 Gas Phase Silylation Systems

The most prominent TSI scheme is the so-called DESIRE-process (diffusion enhanced silylating resist), which was developed in the mid 1980s by Roland at UCB Electronics, and Coopmans at IMEC. The pronounced interest arises from the fact that resists, based on dyed DNQ-novolak chemistry, with reproducible properties are commercially available (Plasmask) for g-line (150-G), i-line (200-g) and DUV (301-u) applications (Roland et al., 1990; Bauch et al., 1991). A scheme of the negative-tone DESIREprocess is outlined in Fig. 4-65. The resist is imagewise exposed, subjected to a socalled presilylation bake at approx. 160"C, and silylated in the gas phase at elevated temperature (140 to 170°C) to form a thin resist layer rich in silicon, which builds up the etch resistant SiO, layer during the oxygen etch (Laporte et al., 1991). The selectivity of the silylation has been determined by Rutherford backscattering spectroscopy: The thickness of the silylated layer is in the range of 150 to 200 nm in the exposed, and only 5 to 10 nm in the unexposed areas (Dijkstra, 1991). The silylation mechanism is critical and has been investigated in detail by Visser et al. (1987). It is a kinetically controlled simultaneous diffusion/reaction process following Fick's diffusion law. Its diffusion coefficient depends on the PAC concentration. A thermally induced crosslinking reaction between the unphotolized PAC and the resin occurs in the unexposed areas during the

246 Resist

4 Photolithography

r--l

Dark area

Substrate

C&-

-* -Nz kT

,Novolak

p-j o=s=o

Bake & Silylation

Exposed area C%-)-

Oxygen RIE

- NH3 OH

Si(CH3)3

Figure 4-65. Process flow of the DESIRE process.

presilylation bake. Therefore only the exposed areas can accommodate a large volume of the silylation agent. Due to finite contrasts of both the aerial image and the silylation, sloped silylated profiles are obtained (Reuhman-Huisken and Vollenbrock, 1991; Taira et al., 1991). Using the common silylation reagents, only the hydroxyl moieties of the resin are silylated in the exposed regions. while the carboxylic acid groups of the ICA are not. The Plasmask g-line material incorporates about 1 1 % silicon, which is accompanied by a vertical and lateral resist swelling. While the vertical swelling does not affect the image accuracy, lateral swelling results in a kind of proximity effect, which may give rise to image distortions. The lateral swelling is influenced by the silylation agent and decreases in the following order (Dao et al., 1991): 1,1.3,3.5,5-hexamethylcyclotrisilazane (HMCTS) > heptamethyldisilazane (HeptaMDS)> hexamethyldisilazane (HMDS)>trimethylsilyl-diethylamine (TMSDEA) >> I1l,3,3-tetramethyldisilazane (TMDS) (Fig. 4-66); it has been

reported that the latter suppresses any swelling and improves the processing latitudes (Goethals et al., 1991). Several research contributions denote specific advantages or drawbacks of DESIRE, when applied to practical design, imaging problems and proximity effects (Op de Beeck et al., 1990; Garza et al., 1991; Goethals et al., 1994). The main obstacles to the application of this technology are additional costs for a silylation machine and a plasma reactor, and low wafer throughput (approx. 5- 15 wafer/h). The major lithographic concerns are that of linewidth loss during etching, proximity effects, and stripping of the patterned silicon-containing resist. However, several advantages, such as the very impressive CD control over topography, offset some of these drawbacks (Fig. 4-67). The potential of DESIRE i n production has been evaluated by Garza et al. (1991). The results from more than 1250 wafers indicate that it certainly extends the applicability of exposure equipment already in place. Linearity and process windows were found to be superior to standard resists. A study by Tak-

4.5 Special Photoresist Techniques

b C C b H-Si-N-Si-H

Trimethylsilyldiethylamine TMSDEA

7 Fb

H35 H3C-Si-N-Si-CH3

CI-b

Tetramethyldisilazane TMDS

247

Figure 4-66. Chemical structures of silylation agents.

H3C

CI-b

Hexamethyldisilazane HMDS

H,H3c CH3 N-S< ‘ / Si, N-H Ch’ ,N-S/ H

C b

Heptamethyldisilazane HeptaMDS

1,1,3,3,5,5-Hexamethylcyclotrisilazane HMCTS

Figure 4-67. 0.25 mm lines and spaces of the Plasmask resist over aluminium topography (ASM-L PAS 5000/ 70 DUV stepper (NA=0.42)). Courtesy of IMEC, Leuven, Belgium. Reproduced with permission.

ehara et al. (1991) using the i-line material revealed that the resolution limit (<0.35 pm in a 0.75 pm thick resist) is dictated by the aerial image and not by the dry development performance. For a long time, the dry development was a critical point of the DESIRE process, yielding substrate residues (grass), or profile degradation (Hutton et al., 1990). Most of these problems have been overcome. Low-pressure - to avoid undercut - highdensity plasmas are required for sufficiently high etch rates. While low-density plasmas

with high ion energies in a parallel-plate reactor - reactive ion etching (RIE) - etch too slowly with poor etch selectivity, high-density plasmas in magnetron enhanced ion etchers (MIE) with low ion energies and better etch selectivity (Lombaerts et al., 1990; Hutton et al., 1990) expose the resist to elevated temperatures resulting in profile degradation (Joubert et al., 1993). High-densitiy plasmas provided by an electron cyclotron resonance (ECR) reactor at low temperatures allow a sufficiently high etch rate and selectivity (Lynch et al., 1992). Wafer temperature is one of the most important parameters to control (Dijkstra, 1991). Using an SO,/O, gas mixture instead of pure oxygen even at room temperature a perfect anisotropy with negligiable critical dimension loss is obtained with an ECR dry development process (Pons et al., 1994; Park et a]., 1997). DESIRE has been improved using the PROMOTE technology to obtain a higher contrast silylation profile and an enhanced photospeed (Reuhman-Huisken et al., 1991). A modification of DESIRE to yield positive patterns has been investigated at LET1 (Joubert et al., 1992). Standard PlasmaskR resist is imagewise crosslinked with 248 nm or e-beam radiation. A near UV flood exposure, silylation of the uncross-

248

4 Photolithography

linked areas and oxygen RIE follow. This process can be performed using a phaseshifting mask and DUV radiation (575 mJ/ cm2) to yield high contrast patterns with a minimum resolution of 175 nm lines and spaces in a 0.35 pm thick resist. When subjected to 193 nm excimer laser radiation, PlasmaskR resists crosslink with a higher efficiency than at 248 nm and give highresolution, positive dry-developed images (Hartney et al., 1992). For this purpose pure phenolic resins are superior to DNQ-PAC/ polymer mixtures with respect to resist sensitivity and silylation speed. Using a dose of - 70 mJ/cm2 and a 60 second silylation treatment at 140°C, 0.2 p m patterns with an aspect ratio > 5 have been obtained. The TSI scheme has been applied to PBOCST CARS (Fig. 4-68). Imagewise DUV exposure is followed by a PEB, to deprotect the phenol, and a treatment with a metallization agent, e.g. HMDS (Willson et al., 1990), chlorotrimethylsilane, (dimethy1amino)-trimethylsilane (MacDonald et al., 199 1 ), or titanium tetrachloride (Nalamasu

Resist

et al., 1989). Upon oxygen plasma etching, a negative image is obtained. The process offers an excellent silylation selectivity, because the unexposed, blocked polymer does not react. A positive working process, called SABRE (silicon added bilayer resist), is applied as a bilayer scheme. A planarization layer is coated with a thin imaging layer (< 0.5 pm) of a standard DNQ-novolak resist, which allows high resolution. The unexposed areas of the top resist remaining after development are subjected to a silylation treatment i n the gas phase. Upon oxygen plasma etching of the bottom layer, positive relief images are obtained (McColgin et al., 1988). A surface imaging scheme to yield positive dry etch resistant materials upon DUV irradiation was first described by Mutsaers et al. (1990). It relies on the AHR concept (Lamola et al., 1991): irradiated areas crosslink upon the application of a PEB at 80 to 120°C and thus prevent silicon uptake in the imaged areas.

07s'

Substrate Exposure

CF3SO3

(PpS

(PR + CF3S03H

-(&)-- -(d): Ch' I?CH2

H+ kT

Bake & Siiylatlon

Y F 0

0-c-C&

AH3 kT

.u.

Oxygen RIE

Figure 4-68. Process flow of surface imaging with t-BOC reAiqs.

HMDS

Con

249

4.5 Special Photoresist Techniques

A similar concept is employed in a DUV TSI process, developed at Shipley, called SAHR (silylated acid hardening resist; Pavelchek et al., 1993). SAL 607, a negative CAR for e-beam irradiation, was selected as resist and TMSDEA was used as the silylating agent. A contrast value of 6 has been obtained using low exposure doses ( l l 0 mJ/cm2). The process has been transferred to e-beam lithography, resolving 0.3 pm patterns with doses c 10 pC/cm2 (Vachette et al., 1991). The SAHR concept has been evaluated for 256 MBit DRAM patterns (0.24 pm) using a special resist and TMDS (Han et al., 1993; Park et al., 1997). 4.5.4.2 Liquid Phase Silylation Systems

A new resist chemistry based on carboxylic acid anhydride groups in the resin gives access to liquid phase silylation (Sebald et al., 1990). In a bilayer system the developed top resist patterns are treated at room tem-

perature on normal puddle equipment with a nontoxic aqueous/alcoholic solution of a bisaminosiloxane, resulting in a time-controllable widening of resist lines, called CARL (chemical amplification of resist lines) process (Figs. 4-69 and 4-70). As resin, co- or terpolymers of maleic acid anhydride with trimethylallylsilane, styrene or maleimide are employed, which have high glass transition points and are transparent above 230 nm. The selection of the DNQPAC thereby determines the spectral sensitivity. The i-line version is commercially available from Clariant. As DUV and ebeam sensitive CARS for the CARL-process, t-BOC-blocked maleimide or t-butylmethacrylate copolymers in combination with onium salts have been applied (Leuschner et al., 1992, 1994; Hien et al., 1998). The incorporation of cyclic anhydride groups into the polymer is mandatory for the process. The anhydride moiety is opened by the amino groups of the siloxane under the

U uuu ,,

TOPresist Bottom resist Substrate Exposure

I It

'7'

Bottomresist

-I

Top resist

dR Alkaline 7H3

7H3

N-R-Si-(-O-Si-&o-R-NH2 I H? I CH3 CHI

2 :(:'+

U Aqueous/

alcoholic silylatlon

0 Oxygen RIE

Si CARL

TOP CARL

Figure 4-69. Process flow and chemistry of (left) the Si-CARL and (right) the Top-CARL process.

250

4 Photolithography

Figure 4-70. Lateral CD increase vs. vertical silylation increase of 180 nm nested lines (diagram) and selected crossection SEMs after development and after two different silylation conditions. (Reproduced from Hien et al. (1998) with permission.)

formation of carboxamide linkages and the respective ammonium salts, as evidenced by FTIR (Sebald et al., 1990). The silicon uptake of - 25% by weight is responsible for the high etch selectivity. The lateral widening of resist lines makes it possible to compensate for linewidth loss during 02-RIE and to print equal lines and spaces in the sub quarter micron domain (Franzen et al., 1998). Furthermore, chemical biasing (CARL effect) after wet development can be used advantageously for a dramatic increase of focus windows in the high resolution domain at k , < 0 . 5 . Bossung plots of 160 nm dense lines (simulated by Prolith/2) in Fig. 4-7 1 show that the isofocal point is obtained

.-E

024

3 020

Chemical Elaslng

016

at an overexposure of approx. 60 nm i n this case, i.e., 100 nm lines and 220 nm spaces in resist. Using silylation conditions that increase the linewidth for 60 nm, the isofocal line is shifted to the target CD value and the maximum depth of focus is now available for the 160 nm equal lines and spaces in the resist (Fig. 4-7 1 ) . However, the silylation conditions and thus the extent of chemical biasing has to be adapted carefully in order to result in optimum process windows for a given target linewidth (Hien et al., 1998). Structures down to 0.3 mm were resolved with a g-line stepper (NA = 0.55) and 0.16 pm lines and spaces were achieved upon DUV exposure ( N A = 0.60), both cor-

(Silylatlon)

012

3 ow

!-I

Poor process window -06

-04

-02

Eesl

Fms

Focus Setting [pm]

0.04

Large process window 04

-06

-04 - 0 2

Best Fours

0.2

Focus Setting [pm]

Figure 4-71. Concept of Chemical Biasing in the CARL process shown for 160 nm dense lines. (Reproduced from Hien et al. (1998) with permission.)

4.5 Special Photoresist Techniques

responding to a k , factor of 0.38 (Sebald et al., 1990; Hien et al., 1998). The CARL process gives photolithographical accessibility to space dimensions that are beyond the resolution limit of the optics used; even 170 nm spaces and 150 nm contact holes have been made by Sebald et al. (1990) with i-line exposure ( N A = 0.40) and simply controlling exposure dose and silylation time. Recently, the CARL process has been applied in volume production with good CD control over severe topography and a defect density comparable to standard lithography (Franzen et al., 1998). Figure 4-72 demonstrates the resolution capability and focus latitude of the CARL process with 193 nm exposure wavelength. In a dry developing scheme called TopCARL the same chemistry is applied but the

251

development step is omitted (Sezi et al., 1990). A thin film (0.4 pm) of an anhydridecontaining copolymer and a DNQ-PAC is coated on a hardbaked bottom resist. The top layer is imagewise exposed, silylated selectively in the exposed areas and then dry developed to yield negative patterns (Fig. 469). The high etch stability of this system makes it possible to print 0.40 pm patterns in 2 ym thick resist with an i-line stepper (NA= 0.40) or structures with steep profiles in up to 42 pm thick polyimide layers (Leuschner et al., 1993). A positive working variant makes use of a photobase additive to the DNQ-based resist and an image reversal bake with subsequent flood exposure to change the tonality of the resist (Leuschner et al., 1993). For DUV exposure, a CAR version of the Top-CARL re-

Figure 4-72. (a): Crossection SEMs of 130 nm isolated and dense lines and 120 nm dense lines after dry development (imaging dose=6 pJ/cm2) best focus, standard illumination, COG mask); (b): Top view of dry developed 130 nm dense lines at different focus settings (values given in pm, imaging dose=6 pJ/cm2) (Reproduced from Hien et al. (1998) with permission.)

252

4 Photolithography

Silylation agent

Silylation time (min)

OH-silylation ( )

COOH-silylation (YO)

77.0 79.0

55.4

Figure 4-73. Chemical structures of several silylation agents with Si-N units, and the degree of phenolic OH-group and indene COOH-group silylation. (Data taken from Babich et al. (1991) with permission.)

58.9

CH3

H> ?-Ai: *Si; N-H C&’ ,N- S i I ‘CH3 H H

26.6

62.1

35.5

69.3

20.0

56.5

21.7

61 .O

1.7

2.6

1.7

4.8

CH3’

‘CH3

sist has been evaluated by Sezi et al. (1991) using a copolymer containing the r-butylester group and a PAC. It shows a high silylation contrast and resolves 0.30 pm patterns in 1.8 pm resist thickness with a DUV stepper ( N A =0.37). While the CARL process employs an aqueous phase based silylation, Yang et al. (1989) and Stewart et al. (1990) have investigated solvent based liquid phase processes with a variety of polyfunctional organosilicon compounds (Fig. 4-73). DNQ-novolak based resists are imagewise exposed, developed and treated with a xylene or n-decane solution containing a resist solvent as diffusion promoter and a silylation agent, e.g. hexamethylcyclotrisilazane (HMCTS; Stewart et al., 1990). orbis (dimethylamino) dimethylsilane (BDMADS; Babich et a]., 1991). In contrast to vapour phase silylation, liquid silylation causes crosslinking of

the resist and drives more silicon into it, resulting in higher thermal resist stability and better etch resistance. An ultimate resolution of 50 nm has been obtained by Vettiger et al. (1989). In a single layer arrangement, negative or positive tone patterns can be printed when the Plasmask 200-G or the acid hardening resists AZ 5214 and SAL-601 are used, respectively (Baik et al., 1993; Gogolides et al., 1994; Kerber et al., 1992). In the latter case, crosslinking of the exposed areas prevents penetration by the liquid silylation agent.

4.6 Trends in Photolithography Tremendous progress has been made in the development of new lithographic techniques during the last few years. Despite this, i t is anticipated that the majority of vol-

4.6 Trends in Photolithography

ume-orientated production processes will continue to use the established optical lithographic methods, mainly due to cost reasons and practical experience of the workforce. Wafer fabrication will continue to be a mix-and-match situation with state-ofthe-art lithography being used only for the most critical applications. Delineation of reproducible 0.25 pm patterns (and below) with high throughput seems to be the barrier for current i-line lithography. Short wavelength optical lithography using 248 nm or 193 nm excimer laser based systems is the candidate to delineate high resolution features down below 0.18 pm, and 0.13 pm, respectively, without any restrictions to pattern layout. Phase shifting mask or off-axis illumination techniques improve the resolution capability, but these approaches are not as easy to apply to isolated or random patterns (Okazaki, 1991). The combination of high NA DUV stepper with phase shifting mask and off-axis illumination seems to offer reasonable process windows even for ~ 0 . 1 pm 8 patterns (Van den hove and Ronse, 1994). An extension to sub 0.15 pm patterns using ArF lithography seems plausible. Next generation DUV lithography (157 nm) might even be able to print features well below 100 nm by using of F, excimer lasers and CaF, optics and masks in vacuum (Bloomstein et al., 1997). Tighter CD control and increasing reflection problems will expand the use of top and bottom antireflective coatings, thus blurring the current borders between single and multilayer resist applications. The depth-of-focus problem and the high absorbence of etch resistant materials stress the need for top surface imaging systems (Hartney et al., 1992). Approaching the resolution limits, optical proximity effects will become dominant and require sophisticated proximity correction strategies (Van den hove and Ronse, 1994).

253

X-ray lithography offers the potential to print features below 0.10 pm, but still suffers from difficult mask fabrication, inspection and repair, because the required accuracy for 1 : 1 X-ray masks is at least one magnitude higher than for optical reticles. Although the general infrastructure has been improved, several issues, such as metrology have not yet been addressed, and the rapid progress of optical lithography keeps XRL on the waiting list. Soft X-ray (13- 16 nm) projection lithography has considerably matured during the last few years. Despite the progress made in the coating techniques (White et al., 1991; Ito et al., 1994; Montcalm et al., 1998), the required reflection optics need improvements with respect to alignment, optical substrates and stage scanning (Sweeney et al., 1998; Kinosh*ta et al., 1998). And for all next generation lithography technologies mask fabrication is a challenge because chrome-coated quartz glas is no longer the mask material of choice (Abboud et al., 1998). Advanced parallel printing e-beam systems, like cell projection lithography, may develop to a competitive technique with respect to resolution and throughput. Questions remain with respect to wafer heating in the exposed areas, proximity correction and device damage due to high voltage. Fascinating evolutionary concepts, like the high voltage SCALPEL approach (Liddle et al., 1997) or the parallel-working direct writing system based on micro columns operating at low voltage may provide the best choices for future nanolithography (Chang et al., 1992; Kratschmer, et al., 1995). Ion projection lithography, however, has proven its capability to print sub-100 nm patterns (Mohondro, 1997). Independently of the above-mentioned advanced lithographic techniques, resist sensitivity will be an important issue because all new lithographic approaches pro-

254

4 Photolithography

vide lower radiation densities than conventional exposure tools. Therefore chemical amplification systems may be a prerequisite for cost-effective production of post 64 MBit DRAM generations, thus posing significant quality and specification control challenges to the resist suppliers. To avoid delay time effects between exposure and post exposure bake, improved cluster processes using environmental chambers have to be developed (Holmes and Sturtevant. 1993). Besides sophisticated lithographic techniques new IC-generations require improved design concepts like e.g. pass-transistor circuits or silicon-on-insulator MOS devices (Takeda. 1994) and new multilevel metallization techniques (e,g, global planarization by chemical-mechanical polishing (Murarka and Hymes, 1995). copper interconnects (Li et al., 1994) or new nonsilicon based elements with reduced space consumption, like giant magnetoresistance ratio materials as memory cells (Nordquist et al., 1997). Future electronics beyond the year 2000 may have totally different designs since even smaller feature sizes go hand in hand with even less controlled electrons per action which sets a trend towards single electron devices (Rohrer, 1994). On the other side, photolithography will be extended to even larger feature sizes for micro-mechanical or optical purposes thus providing integrated devices and machines with elements ranging from the nanometer to the millimeter scale.

4.7 References The literature cited here mainly considers articles published after 1987. Older publications can be found in the citation lists of these articles.

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General Reading Ahne, H., Leuschner, R., Rubner, R. (1992). “Recent Advances in Photosensitive Polyimides”, Polym. f o r Advan. Technol. 4. 2 17-233. Brambley, D., Martin, B., Perwett, P.D. ( 1994), “Microlithography: An Overview”. Advanced Marer Opt. Electron. 4, 55-74. Dammel, R. ( 1993). Diazonaphthoqinone-based Ru sists, SPIE Optical Engineering Press, Bellingham. Washington, USA. Horie, K., Yamash*ta, T. ( 1995). “Phorosensirivr Polyimides”, Lancaster, PA: Technomic. Moreau, W. M. (1988), Semiconductor Lithograph!. Principles, Practices and Materials. Plenum Press. New York. Rabek, J. F. (l987), Mechanisms ofphotoph>sical and photochemical reactions in polymers: theory and practical applications, John Wiley, New York. Reichmanis, E., Houlihan, F. M., Nalamasu, O., Neenan, T. X . (1994). “Chemically Amplified Resists: Chemistry and Processes”. Advanced Mater. Opt. Electron. 4, 83. Reiser, A. (1989), Photoreactive polymers. The science and technology of resists. Wiley & Sons, New York. Soane, D. S . , Martynenko, Z. (1989), Polymers in M i croelectronics, Elsevier Science Publ., Amsterdam. Timpe, H. J., Baumann, H. (1988), Photopolymere: Prinzipien und Anwendungen, Deutscher Verlag fur Grundstoffindustrie. Leipzig. 1 . Auflage.

5 Selective Doping Subhash Mahajan Department of Materials Science and Engineering. Carnegie Mellon University. Pittsburgh. PA. U.S.A.

List of 5.1 5.2 5.2.1 5.2.1.1 5.2.1.2 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.3 5.3.1 5.3.2 5.3.3 5.4 5.5

Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Atomic Diffusion Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 269 Interstitial Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Substitutional Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Phenomenological Description of Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Selective Doping by Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dependence of Diffusion Coefficient on Temperature . . . . . . . . . . . . . . . . . . . 272 Dependence of Diffusion Coefficient on Concentration . . . . . . . . . . . . . . . . . 273 274 Interaction of Diffusants with Charged Defects . . . . . . . . . . . . . . . . . . . . . . . . 275 Diffusivities of B, P, and As in Si . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diffusion of Si, Zn, Be, and Cr in GaAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Diffusion-Induced Dislocation Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Ion Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 279 Salient Features of Ion Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Ion Channeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ion Implantation-Induced Damage and Its Annealing Behavior . . . . . . . . . 282 Comparison Between Diffusion and Ion Implantation for Selective Doping . 288 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

266

5 Selective Doping

List of Symbols and Abbreviations impurity concentration dopant concentration interstitial concentration surface concentration of dopant net dopant concentration concentration of substitutional species initial concentration diffusion coefficient diffusivity intrinsic diffusion coefficients of neutral, singly positively charged and singly, doubly, and triply negatively charged vacancies, respectively energy of incident ion activation energy displacement energy complementary error function flux of inpurity atoms Boltzmann constant mass ion concentration number density impurity concentration at x free carrier concentrations total number of dopant atoms per unit area close ion range projected range projected straggle projected transverse or lateral straggle stopping power of the solid energy loss per unit length due to coulombic interactions energy loss per unit length due to nuclear collisions time anneal time absolute temperature; energy transferred anneal temperature atom fractions of vacancies under extrinsic and intrinsic conditions, respectively

distance from surface position

List of Symbols and Abbreviations

‘j

junction depth Young’s modulus solute lattice contraction coefficient strain scattering angle Poisson’s ratio differential cross section maximum stress dose

LSS MESFET PSG VLSI

Lindhart, Scharft, and Schiott metal-semiconductor field-effect transistor phospho-silicate glass very large scale integration

267

268

5 Selective Doping

5.1 Introduction At ambient temperatures, the carrier concentrations in intrinsic, technologically important semiconductors, such as Si, GaAs, InP, GaN, and CdTe, are fairly small. For example, in intrinsic Si it is lo1’ cmT3.As a result, intrinsic materials are not widely used in device technology. Instead, they are appropriately doped either during the growth of bulk crystals or during the deposition of epitaxial layers. These materials are referred to as extrinsic semiconductors and the doping is global in nature. In many situations in device technology, local variations in carrier concentrations and type are required. This is illustrated using a GaAs metal-semiconductor fieldeffect transistor (MESFET)structure, schematically shown in Fig. 5-1. One way to obtain the transistor action is to dope n-GaAs below the source and drain contacts with p-type dopants, i.e., selective doping, and apply appropriate voltages to the three contacts. Selective doping is achieved by the diffusion of dopant atoms through openings in a masked substrate or by ion implantation of the dopant into the surface of the wafer. Either process is followed by a “drive-in” anneal to obtain the final distribution of the dopant atoms. In this re-

view, the salient features of diffusion and ion implantation are highlighted, and their relative merits are compared. (The doping of compound semiconductors is also treated in Chap. 10 of this Volume.)

5.2 Diffusion

Figures-1. Schematic cross section of a GaAs MESFET.

Diffusion refers to the movement of atoms by random jumps. In a crystal, these jumps involve a series of some type of point defect. An energy barrier is associated with these jumps, because they may involve the displacement of adjacent atoms and broken bonds. Since at a given temperature atoms in a solid vibrate about their mean position with a certain frequency, they attempt to overcome this barrier during one of their excursions. Some of them are able to overcome this barrier during one of their many attempts, and move into new locations. By proper control of this diffusion process, the dopant atoms deposited at or near the surface of a semiconductor can be moved inwards to produce a desired impurity profile. This approach is referred to as selective doping of semiconductors by diffusion. Two approaches have been developed to describe the diffusion phenomena: (i) atomistic and (ii) phenomenological. The atomistic description considers the atomic nature of the diffusing species and host lattice explicitly. Since diffusion in semiconductors is complicated by a variety of dopantdopant and dopant-point defect interactions, the development of atomistic understanding is quite challenging. In the phenomenological approach the solid is replaced by a continuum and the flux of atoms is described by coupled diffusion. Both experimental studies and computer simulations are used to understand the atomic scale interactions. The results of

Source

n-GaAs

Gate

Drain

k Depletion Region

Semi-insulating GaAs

269

5.2 Diffusion

these studies are then incorporated into continuum models, such as SUPREME, which are used to design the concentrations and annealing schemes for semiconductor processing.

5.2.1 Atomic Diffusion Mechanisms In the silicon lattice some atomic species primarily occupy interstitial sites, whereas others reside on substitutional sites. Since the lattice is rather open, there are several species that reside on the interstitial sites. As indicated earlier, the movement of an impurity in a lattice takes place in a series of random jumps. A net flux of diffusing species results if there is a concentration gradient. The mechanisms by which jumps can take place are described below.

5.2.1.1 Interstitial Diffusion Interstitial diffusion is schematically illustrated for a two-dimensional lattice in Fig. 5-2a. As shown, interstitial impurity atoms move through thet lattice by jumping from one interstitial site to the contiguous one. Interstitial diffusion is rapid because the motion of impurity atoms is not impeded by the matrix atoms. The impurity atoms may be located at either substitutional or interstitial sites. The diffusion of these atoms occurs primarily by the atomic fraction residing on the interstitial sites.

0 0 0 0 0 0

0-0

oto

0 0 0

o o t o o o o 0-0

0 0 0 0 0 0

0 0-0-0

0 0

t 1 0 . 0 0 0 0 t

0 - 0 0 0 0 0

0 0 0 0 0 0

(a)

(b)

Figure 5-2. Schematic diagrams illustrating (a) interstitial and (b) substitutional diffusion.

very low, substitutional diffusion occurs at a much slower rate than interstitial diffusion. Furthermore, a modified version of substitutional diffusion is possible. This is referred to as the interstitialcy mechanism. In this case, the diffusing atom moves by pushing one of its nearest substitutional neighbors into an adjacent interstitial site and taking up the resulting, vacant substitutional site.

5.2.2 Phenomenological Description of Diffusion If an impurity concentration gradient, ac/ax, is present in a finite volume of a matrix, the impurity will diffuse to reduce the gradient. After a sufficiently long time, the impurity movement will cease because its concentration will become uniform. In 1855 Fick described this situation mathematically as

5.2.1.2 Substitutional Diffusion Substitutional diffusion is schematically illustrated in Fig. 5-2 b. As depicted, impurity atoms move through the lattice by jumping from one lattice site to the next. For this process to occur the adjacent lattice sites must be vacant, i.e., vacancies must be present in the lattice. Since the concentration of vacancies is generally

where J is the flux of impurity atoms, D is the diffusion coefficient of the impurity in the host lattice and c(x, t) is the concentration of the impurity that depends both on position and time. If it is invoked that mass is conserved during diffusion, then it can be shown using simple arguments that the variation in c with t is related to the

270

5 Selective Doping

changes in J with ac -

aJ .. ax

(5-2)

which is known as the continuity equation. Taking the derivative of J in Eq. (5-1) with respect to .Y and equating it to aclat, we have (5-3)

Equations (5-1) and (5-3) are referred to as Fick’s first and second laws of diffusion.

5.2.3 Selective Doping by Diffusion In semiconductor device processing, dopant diffusion is carried out under two different conditions. Suitably masked regions of a wafer are exposed to a diffusant whose concentration at the surface is constant. This step is referred to as predeposition. Subsequently, the wafer is annealed to diffuse dopant into the semiconductor. This anneal is termed drive-in. A constant dopant concentration at the surface during predeposition can be achieved by bringing a dopant source into equilibrium with a semiconductor surface. The source can be in the form of a solid such as phospho-silicate glass (PSG), liquid such as BBr, or POCl,, or gas such as ASH, or BH,. The dopant concentration at the surface is determined by its solubility limit in the semiconductor at the diffusion temperature. On the other hand, for a gaseous source the partial pressure of the dopant determines its concentration at the surface: the higher the pressure, the higher the concentration. Of course, when the solubility limit is reached, further increases in pressure will have no effect on the surface concentration. At high diffusion temperatures many dopants react with clean silicon surfaces caus-

ing pitting. For this reason, predepositions are generally carried out in a nitrogen atmosphere containing a small amount of oxygen. As a result, a thin layer of oxide is grown before admitting dopants into the diffusion chamber. Selective doping of group 111-V semiconductors via diffusion at high temperatures is cumbersome because the surfaces deteriorate by preferential evaporation of group V species. This is the result of their high vapor pressures at the diffusion temperature. Capping layers or counter pressures are generally used to prevent out-diffusion of group V atoms. The boundary conditions for predepositions are c(0, t ) = c , (5-4) and c ( x ,t)=O where c, is the surface concentration of the dopant. The solution of Eq. (5-3) under the above boundary conditions is

(5-5)

where erfc is the complementary error function. Normalized concentration versus distance curves for different times on linear and semilogarithmic scales are shown in Figs. 5-3 a and (b), respectively. As expected, for a given dopant concentration at the surface, impurity atoms penetrate deeper at longer diffusion times. The total number of dopant atoms per unit area of a semiconductor is given by x

Q(t)= J

C(X,

t) dx

(5-6)

For predeposition diffusion, Q ( t ) is given by

= LlJ D t c,

(5-7)

5.2 Diffusion 1 .o

0.8 0

0.6

271

Typical junction depths after predeposition are in the range of a few thousand angstroms. Both temperature and time affect the depth of penetration through the Normally, predeposition parameter is carried out at high temperatures so that a large number of dopant atoms can be introduced into the semiconductor as a result of the high solubility. Since predeposition is a high-temperature process, it is not suitable for fabricating very shallow junctions. The surface concentration of dopants obtained during predeposition cannot be maintained at room temperature, at which devices operate, because the solubility limit is exceeded. It is therefore essential to reduce the surface concentration of a dopant to its solubility limit at ambient temperature. This is accomplished by a second diffusion anneal in which the dopant atoms incorporated during predeposition are moved inwards. This step is referred to as drive-in diffusion. In the case of silicon, drive-in is carried out in an oxidizing atmosphere where the oxide tends to prevent out-diffusion of dopant atoms. The boundary conditions for drive-in diffusion are

fi.

0.4 0.2 I

n "

100

lo-'

10-2 0

10-3

10-4

105

x (pm) Figure 5-3. The complementary error function: normalized concentration vs. distance for successive times on (a) linear and (b) semilogarithmic scale.

In most predepositions, the objective is to achieve a certain specified concentration of dopant atoms. Furthermore, if the semiconductor is doped to a level cb and has a conductivity opposite to that introduced by the diffusant, then the net dopant concentration at a given x is given by

(5-8)

A p-n junction will form at a distance x where c,,, is zero. Using this condition, the junction depth (xj) can be determined from Eq. (5-8) and is given by (5-9)

7 c(x, t ) d x = Q 0

and c(o0, t ) = O

(5-10)

The solution of Eq. (5-3)under the above boundary conditions is given by (5-1 1)

The above solution is a Gaussian function and is shown as normalized concentration versus distance curves for successive times on linear and semilogarithmic scales in Figs. 5-4a and b, respectively. It is evident

272

5 Selective Doping

1 xi05 I

-E

0.8

0.6

0.4 0.2 0 0

105

104

-k

io3

0 102

x Mml Figure 5-4. The Gaussian function: normalized concentration vs. distance for successive times on (a)linear and (b) semilogarithmic scale.

given by

c, = c(0, t ) = -

Ji ot

(5-12)

As before, the junction depth x j is given by

(5-13)

As a result of the drive-in diffusion, both the dopants and the junction depths are moved deeper into the semiconductor. The as a length scaling facimportance of tor is evident. Furthermore, the Gaussian solution given by Eq. (5-11) assumes that dopant atoms are confined to an extremely

narrow region after predeposition, so that their distribution may be treated essentially as a delta function. In the fabrication of microcircuits, diffusion is always carried out through windows in a mask that is in intimate contact with a semiconductor wafer. Equations (5-5) and (5-11) give correct values of c(x,t) at all locations, except near the edge of the mask window. This is due to the fact that the dopant atoms in the window region act as a dopant source, resulting in their lateral migration into the region contiguous to the window edge, which is underneath the mask. This effect is illustrated in Fig. 5-5 a, where contours of constant doping concentration obtained during predeposition are shown (Kennedy and O’Brien, 1965). These contours have been computed assuming that the diffusion constant is independent of the concentration. Figure 5-5 b shows the contours of constant doping concentration for drive-in diffusion. It is apparent from Figs. 5-5a and b that the lateral penetration by the dopant atoms is 75-85% of the vertical penetration.

In the preceding discussion, it was assumed that the diffusion coefficient is independent of temperature. This is, of course, not the case. It is observed experimentally that diffusion coefficients depend on temperature and this dependence can be described by (5-14) where D o is the diffusivity, E, is the activation energy associated with the diffusion process, kB is the Boltzmann constant, and T is the temperature in K. D o and E may vary with composition, but are indepen-

5.2 Diffusion

273

0 0.5 1.o

1.5

2.0 2.5

3.0

Diffusion Mask 0 0.5 1.o 1.5 2.0

0.003

2.5

3.0

2 2. 2.5

2.0

x / 2 f i

I 1.5

I 1.0

1 0.5

0 0.5 (b)

l 1.0

0.0001 I I 1.5 2.0

dent of temperature. Therefore, to compute correct values for the junction depths from Eqs. (5-9) and (5-13), the temperature dependence of D must be taken into consideration. The measured values of the activation energy for various diffusants in silicon vary from 0.2-2.0 eV for fast diffusers such as He, H,, O,, Au, Na, Ni, Cu, and Fe to 3-4 eV for slow diffusers such as B, As, P, and Sb. The low activation energies are associated with interstitial diffusion, whereas high values are associated with substitutional species. The differences in the diffusion coefficients are even more dramatic. For example, at 1100“C Cu diffuses interstitially with a diffusion coefficient of

Figure 5-5. Isoconcentration dopant contours at the edge of a window in an oxide (Kennedy and O’Brien, 1965).

2.5

cmz s-’, and the self-diffusion coefficm2 s-l. cient of Si is 4 x

5.2.5 Dependence of Diffusion Coefficient on Concentration The diffusion profiles shown in Figs. 5-3 to 5-5 were obtained assuming that the diffusion coefficients are independent of the composition. This is a reasonable assumption when the intrinsic carrier concentration at the diffusion temperature exceeds the dopant concentration. When the dopant concentration is high, the diffusion profiles calculated using Eqs. (5-5) and (5-11) do not agree with the measured profiles. This occurs because, at high

274

5 Selective Doping

concentration, D is not independent of the concentration. As a result, Fick's second law of diffusion must be rewritten as follows to reflect this situation: ac(x, t ) ~

= -[ D

&(x, t )

for each impurity-vacancy combination. If it is assumed that each combination behaves independently, it can be shown that the diffusivity under extrinsic conditions ( D ) is given by (Shaw, 1975)

- a D ac(x,

+D-

a2c(x, t ) ax2

(5-15)

[V2-1 + D i 3 +Di2- (5-16) [V2-Ii [V3- I i where Dio, D i + ,D i - , Di2-, and Di3- are the intrinsic diffusion coefficients and [VO], [V'], [V-1, [V2-], and [V3-] and [V0li, [V'Ii, [V-Ii, [V2-Ii, and [V3-Ii are the atom fractions of differently charged vacancies under extrinsic and intrinsic conditions, respectively. Both the diffusion coefficient and the activation energy for the motion of a vacancy depend on the charge state. The concentrations of vacancies having various charged states are determined by the position of the Fermi level. Figure 5-6 shows the energy-band diagram for charged vacancies in Si (Ghandhi, 1983). Seeger and Chik (1968) have hypothesized that in the presence of n-type dopants, the concentration of V + may increase due to the decrease in the enthalpy of their formation. The larger the difference between the V+ acceptor level and the Fermi level, the higher the concentration of V'. By captur~

It is difficult to obtain closed-form solutions for the inhom*ogeneous differential Eq. (5-15). Instead, a methodology referred to as the Boltzmann-Matano analysis (Shewmon, 1963) is used to determine D(c) from an experimentally determined c vs x plot. The interested reader may refer to Shewmon (1963) to understand the underlying mathematical argument.

5.2.6 Interaction of Diffusants with Charged Defect Unlike in the case of metals, point defects in semiconductors are electrically charged. For example, the presence of a vacancy in an Si crystal results in four unsatisfied bonds. These bonds could be satisfied by accepting electrons. Thus a vacancy tends to be acceptor-like in its electrical behavior (Ghandhi, 1983). In principle, four levels at successively higher energies are possible within the band gap. It can be argued in a similar manner that interstitials in Si should exhibit donor-like behavior. To illustrate the influence of charged defects on dopant diffusion in semiconductors, consider the case of substitutional diffusion involving vacancies. Furthermore, assume that in addition to neutral vacancies Vo, vacancies can be represented as V', V - , V2-, and V 3 - . The interactions of these vacancies with the diffusing impurity ions will be different, resulting in different activation energies and diffusion constants

-----____-----____

____---__--------_

+ + + + + + + + + + + ++ ++ + + + + + + + ++ +++ E' 0.06 eV - 0.1 6 eV E"

Figure 5-6. Energy band diagram for vacancies in Si (Ghandhi, 1983).

5.2 Diffusion

ing an electron, a V + vacancy can be transformed into a neutral V. Therefore doping with n-type impurities is expected to raise the equilibrium concentration of vacancies and may thus enhance the diffusion of n-type dopants via the vacancy mechanism. On the other hand, p-doping should have the opposite effect.

5.2.7 Diffusivities of B, P, and As in Si In the fabrication of microcircuits, B, P, and As are used as dopants. Hence the diffusivities of these impurities in Si are of interest. Figures 5-7 to 5-9 show the observed temperature dependence of the dif-

275

fusivities of B, P, and As under different doping conditions. As an illustration, let us consider the case of boron diffusion shown in Fig. 5-7; the experimental data points are indicated by various symbols. If it is assumed that boron diffusion results from its interaction with neutral vacancies, then it is possible to estimate a diffusivity vs. temperature trend, as shown in Fig. 5-7. It is apparent that this trend is not consistent with the experimental results. On the other hand, the fit is much better (“calculated” lines) if it is invoked that the boron intrinsic diffusivity is dominated by the interaction of boron ions with singly positively charged vacancies, and is designated T(”C)

1300 1200 1100

1300 1200 1100 1000 10-11

900

1000

900

800

1012

P t

h o

10-73

1014

10’6

Estimate

\ 1

10-16

10-17

6.0

6.5

I 7.0

7.5

I 8.0

10-18

8.5

9.0

1041 ~ ( ~ - 1 1

Figure 5-7. Intrinsic diffusivity vs. temperature for B diffusion in Si: symbols 0 , A, 0, represent data from diffusion in intrinsic Si; A , data from n-type Si doped to 1.5 x lozocm-’; 0, data from p-type Si doped to 5 x 1019cm- 3. DO and 0: are, respectively, the intrinsic diffusion coefficients due to neutral and positively charged vacancies (Fair, 1981).

1019 6.25 6.5

7.0

7.5

8.0

8.5

9.0 9.5

i o 4 1 T(K-~)

Figure 5-8. Intrinsic diffusivity vs. temperature for Pdiffusion in Si: symbols 0 , A, a, represent data from diffusion in intrinsic Si; 0, A , 0, data from high concentration diffusion; V,data from diffusion in extrinsic Si. DO,D;, and DZ- are, respectively, the intrinsic diffusion coefficients due to neutral, singly n e g atively charged vacancies (Fair, 1981).

276

5 Selective Doping

Table 5-1. Intrinsic diffusivity of B, P, and As in Si"

T("C) 1000

1300 1200 1100

900

D o (cm2 s-') 0.76 (Dl+)B 3.85 (Dp)p 22.9 ( D , - h S

B P As a

10-16

lo-''

1 t

10-18 6.0

6.5

7.0

7.5

8.0

8.5

9.0

io4/ T(K-')

Figure 5-9. Intrinsic diffusivity vs. temperature for Asdiffusion in Si: symbols 0 , 0, 0,represent data from diffusion in intrinsic Si; V , V , data from represent data from diffusion in extrinsic Si. A, intrinsic Si due to neutral and singly negatively charged vacancies (Fair, 1981).

( D i + ) BOn . the basis of the results shown in Figs. 5-8 and 5-9, it can be argued in a similar manner that the intrinsic diffusivities of P and As in silicon are, respectively, dominated by the interaction of dopant ions with neutral and singly negatively charged vacancies, and are referred to as (Dio)pand (Di-)*,. The values of Do and E for B, P, and As in the intrinsic concentration range are listed in Table 5-1 (Fair, 1981).

5.2.8 Diffusion of Si, Zn, Be, and Cr in GaAs Si can diffuse on either the Ga or the As sublattice. An Si atom may behave either

E, 3.46 3.66 4.1

Fair (1981).

as a shallow donor occupying a Ga site, Si:,, or as an acceptor occupying an As site, Si,, . From the available in-diffusion data, V,",- are involved in Si& diffusion (Yu et al., 1989; Tan et al., 1991). Furthermore, diffusion profiles of Si in GaAs are not of the error-function type, mainly because of the existence of a very steep diffusion front which may be attributed to the presence of charged point defects (Tan, 1994). The diffusion profiles of p-type dopants, such as Zn and Be, and the deep, mid-gap acceptor Cr, are also not of the error-function type (Tan, 1994). These impurities are substitutional-interstitial diffusers. The concentration of substitutional species occupying the G a sites (cSu,,)is larger than that of the interstitial concentration (c,). During diffusion, a change in c , , ~occurs by the rapid migration of the diffusant atoms on interstitial sites and their subsequent switch to substitutional sites, and vice versa. For example, Zn, is a donor while Zn, is a shallow acceptor, and the switchover can be described using the following reaction: Znif

zns-

+ Iii

(5-17)

where I,, refers to a Ga interstitial. The reaction given by Eq. (5-17) is referred to as the kick-out mechanism (Gosele and Morehead, 1981; Tan et al., 1991). Reactions similar to Eq. (5-17) also hold for Be and Cr.

5.2 Diffusion

5.2.9 Diffusion-Induced Dislocation

Networks When the diffusant atoms are dissolved in the host lattice, the lattice parameter of the diffused region will either increase or decrease with respect to that of the undiffused region. The sign of the change will depend on the difference between the tetrahedral radii of the host and the dopant atoms. Prussin (1961) has given the following expression, which gives the strain ( E ) introduced in the material due to the incorporation of dopant atoms whose concentration is c: (5-18)

&=-PC

where P is the solute lattice contraction coefficient. As a result of the strain, stresses are introduced in the material. The maximum stress which develops near the surface region during predeposition is given by omax

c s ( z ) 1-v

(5-19)

where c, is the surface concentration of the diffusant, Y is the Young’s modulus of the substrate, and v is its Poisson’s ratio. When the value of 0c, is large, omaxmay exceed the critical resolved shear stress of the host lattice, resulting in dislocations in the diffused regions. Levine et al. (1967) have examined in detail dislocation structures in heavily doped B- and P-diffused (111) and (110) wafers. Some of their results are reproduced as Figs. 5-10 and 5-11. Figure 5-10 shows an example of the dislocation structure seen in B-diffused (111) Si. It is evident that the dislocations are not aligned along crystallographic directions. The authors have shown that the majority of the dislocations have Burgers vectors which lie in the (1 11) plane; they are delineated by short lines on

277

the micrograph. In addition, dislocations whose Burgers vectors are inclined to the substrate surface are seen and these vectors are indicated by arrows. In the (1 10) B-diffused wafers, the dislocation networks are quite complex (see Fig. 5-11). The network consists of long ( 4 2 ) [l TO] dislocations aligned along the [OOl] direction. In addition, the dislocations whose Burgers vectors are inclined to the (110) plane are visible and these are delineated by short lines which represent the projections of their Burgers vectors onto the (110) plane. Two mechanisms have been proposed to rationalize the observed dislocation structures. It is hypothesized in one of the models that diffusion-induced dislocations can be likened to misfit dislocations. These dislocations form to accommodate the lattice parameters difference between the diffused and nondiffused regions. Mechanistically, the lattice parameter difference produces a misfit stress. Under the influence of stress, dislocations undergo glide and interact with each other to form a network. On the basis of this model, it is anticipated that this network should be located in the region where the diffusion-induced composition gradient is the largest. This assessment is not consistent with experimental observations (Ravi, 1981). Alternatively, it has been suggested that under the influence of diffusion-induced stress dislocation loops nucleate from steps at the surface. This is a reasonable suggestion because the stresses are highest there due to the very high dopant concentration. Subsequently, these loops undergo glide on their respective slip planes. They will continue to glide until the diffusion-induced stresses fall below the critical resolved shear stress of the material at the diffusion temperature and will interact with each other to form a network. In this

278

5 Selective Doping

Figure 5-10, Dislocation structure observed in a B-diffused ( 1 11) Si sample; short lines delineate dislocations whose Burgers vectors lie in the (11 1) plane, whereas arrows mark dislocations with inclined Burgers vectors (Levine et al., 1967).

Figure 5-11. Dislocation networks observed in a B-diffused (1 10) Si sample. Dislocations whose Burgers vectors are inclined to the (110) plane are marked by short lines (Levine ct al., 1967).

case, the network will be located somewhere in the diffused region and not at the interface between the diffused and nondiffused regions. Since diffusion is carried out at high temperatures, the network dislocations may undergo climb, leading to nonaligned dislocations. This is indeed borne out by experimental results (Ravi, 1981). When the concentration of the diffusant in the solid exceeds its solid solubility limit, the excess diffusant atoms can either cluster to form elemental precipitates or combine with atoms of the host lattice to form intermetallics. As the concentration of the diffusant is generally highest at the wafer surface, precipitation effects are confined to the surface and near-surface regions. Doping by diffusion methods is also treated in Chap. 10 of this Volume.

5.3 Ion Implantation Ion implantation refers to a process by which dopant ions having high kinetic energies can be introduced into a semiconductor to change its carrier concentration and conductivity type. The energies range between 50 and 500 keV for most device applications. In VLSI technology, ion implantation is primarily used to selectively dope surface regions of a wafer. To acquaint the reader with the physical processes occurring during ion implantation, its salient features are briefly reviewed first, followed by a discussion of ion implantation induced damage and its annealing behavior.

5.3 Ion Implantation

279

Log Ion Concentration

n(R)

Vacuum

Gaussian

0,6n(R ) P

Ion Beam

..................

..'

Ion Beam

J Y

5.3.1 Salient Features of Ion Implantation In passing through a solid, ions interact with electrons in the solid, thereby losing energy. They can also collide with the nuclei of the atoms in the solid. Eventually, they come to rest within the solid after some distance R (the range). The ion paths are not straight because of collisions and thus R can have different values. The projection of R in the implantation direction is a more meaningful parameter, because it determines the implant depth and is referred to as the projected range, R , . The relationship between R and R , is schematically illustrated in Fig. 5-12a. Some ions will collide less times than average, so stopping further than R , , whereas some will collide more and stop short of R,. The statistical fluctuations in the ion concentration along the projected range are referred to as the projected straggle ( A R , ) , as shown in Fig. 5-12b. Ions are also scattered perpendicular to the incident direction. The resulting fluctuations in the ion concentrations in the transverse direction are called the projected transverse or lateral straggle ( A R L), and are depicted in Fig. 5-12b. The implications of the two straggles for device fabrication are that the vertical and lateral composition profiles of the implanted regions will not be sharp. Figure 5-13 shows the projected ranges for B, P, and As ions in amorphous Si and

(b)

Figure 5-12. (a) Schematic diagram of the ion range, R, and projected range, R,. (b) Two-dimensional distribution of the implanted atoms. n is the ion concentration (Sze, 1985).

thermal S O , . For a given energy the lighter ion has a longer range than the heavier ion. The calculated values of A R , and A R , for B, P, and As ions in Si are shown in Fig. 5-14. It is evident that these values follow the same dependence on the ion mass as depicted in Fig. 5-13. Incident ions are slowed by nuclear collisions and coulombic interactions with the electrons. Assuming that the energy losses due to the two mechanisms are indepen-

Energy I k e V ) Figure 113. Projected range for B, P, and As in Si and SiO, at various energies. The results pertain to amorphous silicon targets and thermal SiO, (2.27 g cm-3).

280

5 Selective Doping 0.2

A description of the scattering process by a nucleus can be provided by referring to Fig. 5-1 5. Assume that an incoming ion, having energy E , and mass MI, collides with a target atom whose mass is M , . As a result of the collision, the incoming ion is scattered through an angle 0 and the target atom is displaced from its equilibrium position as shown. The energy transferred (7') to the target atom is given by

0.1

0.01 U

C K l

U e, c 0

e, .-

2 a

0.001

, ,

I I , I

100

(:)

T = 4 M l M 2 E , sin2 (MI + M d 2

........

1000

Energy (keV) Figure 5-14. Calculated ion projected straggle A R p , and ion lateral straggle A R I for As, P, and B ions in silicon.

dent of each other and are additive, Lindhard, Scharft, and Schiott (LSS) have developed a theory for determining the range of an ion (Lindhardt et al., 1963). The energy loss per unit distance due to nuclear and electronic collisions is given by

where the nuclear and electronic losses depend on the ion energy. The range of the ions, R , is given by

(5-22)

The energy transferred is maximum for a head-on collision (0 = 1SO'). The scattering angle (0) can be obtained by integrating the equation of motion for the scattering trajectory. The nuclear energy loss is given by

where d o is the differential cross section. LSS have introduced a number of simplifications to make the above integration tractable. Using their approach, the values of (dE/dx),u,l= S,(E) for the implantation of As, P, and B into Si have been computed by Smith (1977), and they are shown in Fig. 5-16. In addition, the electronic losses ortional to the velocity of the ion,

(E)

=kc,,h

(5-24)

where E is energy of the incident ion, N is the number density of target atoms, and S ( E ) is the stopping power of the solid. If S,(E) and S,(E) are, respectively, energy losses per unit length due to nuclear collisions and coulombic interactions, then s ( E )= s, ( E ) s, ( E ) .

Mass = M,

Energy = E,

Figure 5-15. Schematic diagram illustrating the collision bctwcen two hard spheres of masses M , and M , . .V, is at rest and M , has energy E , . 0 is the scattering angle.

281

5 . 3 Ion Implantation

The proportionality coefficient ( k , ) is a relatively weak function of M , and M , and the atomic numbers of the incident ion and the stopping atom. The computed values of (dE/dx),, = S , ( E ) for the implantation of As, P, and B into Si are also shown in Fig. 5-16. Note that in Fig. 5-16 S,(E) increases with the mass of the implanted ion. Thus, the heavy ions will transfer much more of their energy through nuclear collisions than the light ions. Also, for B, S , ( E ) is the dominant loss mechanism over the whole energy range, while for P and As ions, S,(E) dominates for energies up to 130 and 700 keV, respectively. The concentration profile of the implanted ions in an amorphous solid is given by (Ghandhi, 1983) (5-25)

103

v) v)

10‘

P Q)

10’

I I

,,,I

100

1000

Energy (keV) Figure5-16. Calculated values of dE/dx for As, P, and B at various energies. The nuclear (N) and electronic (e) components are shown. Note the points at which nuclear and electronic stopping are equal.

N (x) = L/r;E QoAR, e x p [ - i ( z y ] where N ( x ) is the impurity concentration, Qo is the dose (ions/cm2),x is the distance from the surface in centimeters, R, is the projected range in centimeters, and AR, is the straggle in centimeters. The above equation ignores the effects of the transverse straggle ( A R I). This omission may introduce some error in determining the concentration of ions near the edges of a mask. The profile of the ion concentration, as given by Eq. (5-25), is schematically shown in Fig. 5-12b. The peak concentration is at R, and falls off symmetrically on either side of R,. With some dopants, considerable deviations from the Gaussian profile have been observed. These observations cannot be explained using Eq. (5-25) because it is based on the simple range theory. 5.3.2 Ion Channeling

Atoms in amorphous solids do not exhibit long range positional correlations.

However, some short range correlations may exist. When the ions are incident on such a solid, the probability of the ions encountering atoms within the solid is extremely high. However, this is not generally the case with crystalline materials. This is due to the fact that the presence of three-dimensional atomic arrangements within the crystal creates open channels along certain crystallographic directions. This effect is illustrated in Fig. 5-17 a, which shows the perspectives of ball models of the diamond cubic lattice when viewed along the (100) and (1 10) directions. The “openess” that is observed along a specific direction is referred to as a “channel”. The channel width along a (110) direction is greater than that along a (100) direction. If ions are incident along a channeling direction, some go down the channel and hence experience fewer nuclear collisions. They are primarily slowed down by the coulombic losses, as schematically illustrated in Fig. 5-17 b. As a result, they can

282

5 Selective Doping

<110>

(a)

penetrate deeper into a crystalline solid than in an amorphous material. This effect is called ion channeling. Implantations for the fabrication of devices are not carried out in the channeling directions because it would be difficult to control the concentration versus distance profiles of the implanted ions. To make crystalline solids appear more like amorphous materials to the incident ions, the crystal is tilted away from a channeling direction. This approach assures that the ions do not initially channel. However, some of the ions may subsequently be scattered into a channeling direction. As a result, they may penetrate deeper than the range calculated from Eq. (5-21). This effect produces tails on the concentration versus depth profiles of the implanted ions. 5.3.3 Ion Implantation-Induced Damage and Its Annealing Behavior As discussed in the last section, when ions enter a solid they are slowed by both

Figure 5-17. (a) Ball model showing relative degree of “openness” of the diamond (Si) lattice when traversing in (100) and (110) directions. (b) Schematic representation of ion trajectories in an axial channel for various entrance angles.

electronic and nuclear interactions. The electronic interactions do not result in displaced atoms, but the nuclear collisions do. If the energy transferred by the incoming ion to the host atom exceeds a limiting value, usually a few tens of volts and called the displacement energy (E,), the atom will be dislodged from its site. The resulting situation is schematically illustrated in Fig. 5-18. The displaced atom can acquire enough energy, as a result of a nuclear collision, so that it can in turn displace other atoms from their lattice sites. Likewise, the incident ions will continue to cause displacement damage until their energy falls to a level where the transferred energy during nuclear collisions is less than E,. As a result of these multiple collisions, the displacement damage in ion-implanted solids can be quite extensive. The extent of the damage depends on the incident ion energy, ion dose, dose rate, ion mass, and temperature of implantation. The distribution of the damage produced by an incident ion will depend on

5.3 Ion implantation

whether the ion is lighter or heavier than the host atoms. Since the energy transferred in a collision is directly proportional to the mass of the ion (see Eq. 5-22), a light ion will transfer less energy during each collision with the lattice atom. As a result, the incident ions will be scattered through large angles. The displaced lattice atoms will possess a small amount of energy and may not be able to produce additional displacements. Furthermore, the majority of the energy of the incident ion is lost by electronic collisions, so that there is relatively little crystal damage. The ion range is comparatively large, and the damage will be spread out over a larger volume of the target. The damage produced by a single, light ion may thus take the form that is schematically illustrated in Fig. 5-18 a. The stopping power for heavy ions is smaller when they are moving rapidly (Fig. 5-16), so there is often a region at the surface that is relatively free of damage. The situation with heavy ions is quite different. In this case, the energy transferred to the host atoms by nuclear collisions is quite substantial, implying that the displaced atoms in turn can produce displacement damage. Also, the ions are scattered through smaller angles and the ion

Target

Incident Light ion

1 I

Target

(b)

Figures-18. Damage due to (a) light ions and (b) heavy ions.

283

Figure 5-19. High-resolution electron micrograph showing an amorphous cascade region in a (001) Si sample implanted with 100 keV Si' ions to a dose of 1 x 1014 cm-2 (Narayan and Holland, 1984).

range is small. These factors localize the damage within a small volume, as shown in Fig. 5-18 b. The disordered regions produced by each incident ion have central cores called displacement cascades, in which the defect concentration is extremely high. Figure 5-19 shows a disordered region, observed by high resolution transmission electron microscopy, in an (001) Si crystal implanted with 100 keV Si+ ions to a dose of 1.0 x 1014cm-2 (Narayan and Holland, 1984).If it is assumed that the dots represent atoms, then the figure suggests that atoms are missing in some regions. The vacancies and interstitials in the collision cascades will persist after the implantation only if they are far enough from each other that they do not recombine immediately. In the case of Si, only Si vacancies and interstitials are produced, whereas group I11 and group V vacancies and interstitials must be generated during ion implantation of compound semiconductors. Higher-order defect clus-

284

5 Selective Doping

ters, such as divacancies, trivacancies, etc., may also form. In addition, many of the incident ions do not come to rest at substitutional sites. Therefore the carrier concentration in as-implanted material is very often below the ion concentration. Also, considerable long-range crystalline order exists in materials implanted to low doses. When the dose is increased further, more disordered regions form and eventually begin to overlap, resulting in crystalline regions surrounded by amorphous material. One such situation, observed in (001) Si crystals implanted with Si ions to a dose of 2 x 1014 cm-2, is shown in Fig. 5-20 (Narayan and Holland, 1984). With a further increase in the dose, the implanted volume may become amorphous, as shown in Fig. 5-21 for the case of self-ion damage

in Si (Narayan and Holland, 1984). It is also apparent from Fig. 5-18 that the crystalline-to-amorphous transformation, indiced by ion implantation, would occur at lower doses for heavy ions. Amorphous regions have also been observed in (001) GaAs crystals implanted with 450 KeV SeC ions to a dose of loi4 c m P 2 (Sadana et al., 1985). The resulting damage situation is schematically shown in Fig. 5-22. The amorphous region (a-GaAs) is 250 nm thick and extends all the way to the surface. Also, there is a damaged volume containing channel cascades, which separates the amorphous and crystalline portions of the crystal. As indicated above, the damage produced by ion implantation is extensive. Since the point defects in semiconductors

Figure 5-20. High resolution electron micrograph showing amorphous and crystalline regions (indicated b> an arrow) in a (001)Si sample implanted with 100 keV Si' ions to a dose of 2 x IO" cm-' (Narayan and Holland, 19841.

Figure 5-21. High resolution electron micrograph showing the interface between amorphous and crystalline Si. Note the presence of microcrystals in the amorphous regions that are indicated by an arrow (Narayan and Holland. 1984).

5.3 Ion Implantation

50nm

loo

-I a-GaAs

285

50 nm

100

150

200 Dislocations Isolated Faults

300

Unannealed

350

400°C 350

Figure 5-22. Schematic diagram of damage distribution in (001) GaAs samples implanted with a dose of 1014 Se' ions cm-' at 450 keV (Sadana et al., 1985).

Figure 5-23. Schematic diagram illustrating the damage distribution observed after the annealing of GaAs samples implanted with l O I 4 Se' ions cm-2 at 450 keV (Sadana et al., 1985).

are electrically active, as-implanted materials have poor electrical characteristics. Generally, the minority carrier lifetime and mobility are severely degraded after ion implantation. Furthermore, only a fraction of the implanted ions are located on substitutional sites and contribute to the carrier concentration. To eliminate the detrimental effects of ion implantation, the material has to be annealed at elevated temperatures. This procedure serves two purposes. First, the point defect density is reduced because of the annihilation of some of the vacancies by the interstitials. Second, the implanted dopant atoms in interstitial sites could m,igrate to lattice sites and become electrically active. It is emphasized that unless the implantation energy and doses are

low, the implanted material cannot be restored to its pristine condition by annealing. This limitation has not so far posed a problem in the fabrication of devices using ion implantation. The residual damage after annealing may consist of dislocation loops, dislocations, faults, and twins. This is illustrated in Fig. 5-23 for -(001) GaAs implanted with 1014 Se' ions cm-2 at 450 keV, and subsequently annealed at 400°C (Sadana et al., 1985). Comparing Figs. 5-22 and 5-23, it is clear that the extrinsic dislocation loops form in the channeled cascades, whereas isolated faults and dislocations are seen near the original amorphous-crystalline interface. A high density of faults is observed in the formerly amorphous region.

286

5 Selective Doping

In addition, the orientation of the crystalline region is replicated in the volume that evolves from the amorphous solid during annealing. This is only possible if the crystalline region in Fig. 5-22 serves as a template during the amorphous-to-crystalline transition on annealing. This type of growth is referred to as solid phase epitaxy. The production of damage during ion implantation is statistical in nature, and this affects the damage distribution. It is, therefore, difficult to predict a priori the type and the nature of the residual damage after annealing. However, some generic ideas can be developed to understand the evolution of the defect structure during annealing. When the implanted materials are annealed, vacancies and interstitials that are within the capture volume of one an other are annihilated. Complete mutual annihilation of the two types of defects is not possible because of their spatial separation. Consequently, after a short anneal, the implanted material will contain residual concentrations of the two types of point defect. However, the respective distributions and concentrations of the point defects are different in the two cases. O n further annealing, the point defects coalescence together to form intrinsic and extrinsic faulted dislocation loops lying on { 111) planes that are bounded by ( a / 3 ) (1 11) Frank partials. The driving force for the coalescence is the reduction in the surface energy of the defects. To form such loops in group 111-V materials, groups 111 and V vacancies and groups 111 and V interstitials are required simultaneously. The faulted loops can grow on further annealing. This is achieved by absorption of the appropriate point defects at the cores of Frank partials. When the loops grow, their energies increase because the fault area and the length of the partial increase. At a certain size, the energy of the faulted

loop will become equal to that of the unfaulted loop bounded by f( 4 2 ) (1 10) dislocations. Conversion of the faulted loops into unfaulted loops is accomplished by the passage of Shockley partials across the fault planes. If the implanted material is still saturated with point defects, perfect loops can also expand by the absorption of point defects. During growth, different loops may interact with each other according to the following reaction to form a dislocation network:

Generally, the covalent tetrahedral radii of the implanted ions are different from the radii of the host atoms. Consequently, the occupation of substitutional sites by implants during annealing would lead to local strains. The overall strain energy of the system can be lowered by the migration of implanted atoms to dislocation loops and dislocations produced during the anneal because of favorable elastic interactions of the dislocation and the impurity strain fields. The fault bundles shown in Fig. 5-23 are very likely growth faults. If the amorphousto-crystalline transformation occurs at a very rapid rate, growth mistakes can occur in the { 11l } stacking sequence, leading to stacking faults. This situation may be further complicated by stresses that may develop in the lattice due to the incorporation of dopant atoms of different tetrahedral radii. Now let us apply the above generic ideas on damage production and annealing to two specific situations: the isochronal annealing behavior of Si implanted with B or P ions. Figure 5-24 shows the isochronal annealing behavior of B ions implanted into Si at 150 keV and at three different doses (Seidel and McRae, 1971). The low-

5.3 Ion implantation

1.o

e -

I“

0.1

0.01 400 500 600 700 800 900 1000

T/J0C) Figure 5-24. Isochronal annealing behavior of B. The ratio of free carrier concentration, PHall, to dose, I$, is plotted against the anneal temperature, T,, for three doses of B.

dose samples implanted to 8 x 10” cm-’ show a monotonic increase of the free carrier concentration, i.e., PHallin Fig. 5-24, implying that the implanted ions shift to lattice sites on annealing. However, the annealing behavior of the samples implanted to higher doses is much more complex and can be divided into regions I, 11, and 111. In region I, the free carrier concentration increases with the annealing temperature. Extended defects, such as faulted dislocation loops, are not observed in this regime. The plausible explanation is that B atoms are migrating to the lattice sites during annealing. In region 11,the free carrier concentration decreases with increasing temperature. In addition, a dislocation substructure is observed after annealing. It is likely that B atoms migrate to the dislocation cores. This is due to the fact that B atoms are extremely small and will have strong elas-

287

tic interactions with dislocation cores. Once the dopant atoms are removed from substitutional sites, they will not contribute to the free carrier concentration. In region 111, the free carrier concentration increases with increasing temperature, indicating that B atoms are returning to the lattice sites. This suggests that the binding energy between B atoms and dislocations is overcome thermally. The released B atoms migrate to the lattice sites and increase the carrier concentration. It is apparent from the above example that interactions between the implanted atoms and the annealing-induced defect structure could complicate the activation of the dopants. To develop a full understanding of the behavior of the implanted dopants during annealing, electrical measurements must be coupled with structural observations. Figure 5-25 shows the isochronal annealing behavior of P ions implanted into Si at 250 keV and at six different doses (Crowder and Morehead, 1969). Comparing Figs. 5-24 and 5-25, it is clear that the annealing behaviors of Si implanted with B or P are qualitatively different. When the dose is increased from 3 x 1 O I 2 to 3 x 1014 ions/ cm’, higher annealing temperatures are required to eliminate the progressively more complex damage. Amorphous layers are produced at doses of 1 x 10” and 5 x 10” cm-’, and they extend to the surface. On annealing, the amorphous-tocrystalline transition occurs by solid-phase epitaxy. During regrowth of the amorphous layers, the implanted atoms are incorporated into substitutional sites. Furthermore, after annealing, the carrier concentrations in the samples implanted to higher doses are lower than the low dose specimens. It could be that after annealing the residual damage in the high-dose samples is considerably more extensive.

288

5 Selective Doping

280 keV Phosphorus

1.0 -

0.8 -

. 8

1x 101-5

,*-

0.6 -

6x10’3

1XI

0.4

< , ,

, ~

0.2 -

;

, ’

. _ _ _ _

Not Amorphous

,’

-Amorphous

,:,:,, 1

I ( I

t--

014

, I

The annealing behavior of Si implanted with As or Sb ions at room temperature is similar to that for P ions, except that lower doses are required for amorphization. This is due to the fact that As and Sb ions are considerably heavier than P ions. (The doping of compound semiconductors by ion implantation is also treated in Chap. 10 of this Volume.)

5.4 Comparison Between Diffusion and Ion Implantation for Selective Doping For selective doping, ion implantation is superior to chemical diffusion because the lateral diffusion effects are minimal. As a result, implantation has essentially replaced diffusion doping in the fabrication of stateof-the-art microcircuits. Ion implantation offers the following advantages over diffusion doping: 1. The total amount of dopants introduced can be controlled because it depends on the total ion flux.

Figure 5-25. The ratio of free carrier concentration N,,,,to dose $ plotted against the anneal temperature (TA)for various P doses. The solid curves represent amorphous layers that anneal by solid phase epitaxy. The dashed curves represent implantation where the damage is not amorphous (Crowder and Morehead, 1969).

2. The dopant can be deposited uniformly over a large wafer by carefully designing the rotation and translation of the wafers through the ion beam. 3. The penetration depth of ions into a substrate increases with increasing accelerating voltage. Therefore, by varying the voltage, the implant depth can be controlled. 4.For Si and group 111-V technologies, ion implantation is generally carried out below 673 K. Consequently, the thermal stability requirements on mask materials are less stringent than those for chemical diffusion; silica, silicon nitride, and different metallizations can be used as masks for selective doping. 5. A wide range of ion doses, l o l l to i o i 7cm-2, i.e., from very low to very high, can be delivered to substrates and the dose can be accurately controlled ( -t 1 YO). The lateral uniformity in the ion concentration is also fairly good. In both of these aspects, ion implantation is superior to chemical diffusion. 6. Various ions can be mass separated to produce monoenergetic, highly pure, dopant ion beams.

5 . 5 References

7. Ion implantation is a nonequilibrium process. It is therefore possible to dope the substrate in excess of the solid solubility limits in the host lattice. However, for implanted species to remain in solution, the wafers should not be subsequently processed at high temperatures where excess dopant atoms become mobile and cluster together to form precipitates. There are some inherent disadvantages to ion implantation. The high-energy ions damage the lattice. Therefore, the implanted materials must be annealed at high temperatures to “heal” them. Since Si is quite stable at high temperatures, the annealing step does not entail any problems. However, in implanted group 111-V materials the group V atoms tend to boil off due to their high vapor pressures. Another complication is that the implanted profile may change during annealing because of bulk diffusion. The equipment for ion implantation is highly sophisticated, is very expensive, and has to be manned by experienced operators. However, the high degree of process control results in reproducible dopant profiles, and this has made ion implantation the method of choice for doping semiconducting wafers.

289

Ghandhi, S. K. (1983), VLSI Fabrication Principles. New York: Wiley. Gosle, U., Morehead, F. E (1981), J. Appl. Phys. 52, 4617. Kennedy, D. P., O’Brien, R. R. (1965), IBM J. Res. Devel. 9, 179. Levine, E., Washburn, J., Thomas, G. (1967), J. Appl. Phys. 38, 61. Lindhard, J., Scharff, M., Schiott, H. (1963), Mat.Fys. Medd. K. Dan. Vidensk. Selsk. 33, 1. Narayan, J., Holland, 0. W. (1984), J. Appl. Phys. 56, 2913. Prussin, S. (1961), J. Appl. Phys. 32, 1876. Ravi, K. V. (1981), Imperfections and Impurities in Semiconductor Silicon. New York: Wiley. Sadana, D. K., Zavada, J. M., Jenkinson, H. A . , Sands, T. (1985), Appl. Phys. Letts. 47, 691. Seeger, A., Chik, K. P. (1968), Phys. Status Solidi 29, 455. Seidel, T. E., MacRae, A. U. (1971), in: f s t Int. Con$ on Ion Implantation: Eisen, E, Chadderton, L. (Eds.). New York: Gordon and Breach. Shaw, D. (1975), Phys. Status Solidi 72, 11. Shewmon, P. G. (1963), Diffusion in Solids. New York: McGraw-Hill. Smith, B. (1977). Ion Implantation Range Data for Silicon and Germanium Device Technologies. Forest Grove, OR: Research Studies. Sze, S. M. (1985), Semiconductor Devices, Physics and Technology. New York: Wiley. Tan, T. Y (1994), in: The Encyclopedia of Advanced Materials. Bloor, D., Brook, R. J., Flemings, M. C., Mahajan, S. (1994), Oxford: Pergamon, p. 635. Tan, T. Y., Gosele, U., Ya, S . (1991), Crir. Rev. Solid State Mater. Sci. 17, 147. Yu, S., Gosele, U., Tan, T. Y. (1989), J. Appl. Phys. 66, 2952.

General Reading

5.5 References Crowder, B. L., Morehead, E E , Jr. (1969), Appl. Phys. Lett. 14, 313. Fair, R. B. (1981), in: Impurity Doping Processes in Silicon: Wang, E E Y. (Ed.). New York: NorthHolland, Chap. 7.

Bentini, G. G., Golanski, A , , Kalbitzer, S. (Eds.) (1989), Deep Implants. Amsterdam: North-Holland. de Souza, J. P., Sodana, D. K. (1995), in: Handbook on Semiconductors, Vol. 3: Mahajan, S. (Ed.). Amsterdam: North-Holland, p. 2033. Sze, S. M. (Ed.) (1983), V L S I Technology. New York: McGraw-Hill. Wolf, S., Tauber, R. N. (1986), Silicon Processingfor the V L S I Era. Sunset Beach, CA: Lattice Press.

6 Etching Processes in Semiconductor Manufacturing

Kevin G Donohoe Formerly with Applied Materials. Santa Clara. CA. U.S.A. Terry Turner Fourth State Technology. Austin. TX. U.S.A.

Kenneth A Jackson Arizona Materials Laboratory. University of Arizona. Tucson. AZ. U.S.A.

List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Wet Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 Dry Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.3 Etch Control and Metrology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Equipment: Description of Hardware ................................. 6.2.1 Wet Sinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Dry Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 Etch Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3.1 Barrel Etchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3.2 Plasma Etchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3.3 Reactive Ion Etchers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3.4 Remote Plasma Generation: Microwave and ECR . . . . . . . . . . . . . . . . . . . . . 6.3 Endpoint, Diagnostic and Control Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Endpoint Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1.1 Optical Emission Spectroscopy (OES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1.2 Laser Interferometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1.3 Residual Gas Analysis/Mass Spectroscopy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1.4 R F and Bias Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Diagnostic Tools/Metrology for Process Control . . . . . . . . . . . . . . . . . . . . . . 6.3.2.1 Machine Related Metrology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2.2 Process Related Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Control Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3.1 Present Control Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3.2 What is Needed? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3.3 Possible Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Process Discussion: General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

293 294 295 294 296 296 297 297 298 299 300 301 301 304 305 305 306 307 309 310 312 312 315 317 318 318 319 320 320

292

6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.5.8 6.5.9 6.5.10 6.5.11 6.5.12 6.5.13 6.5.14 6.6 6.7

6 Etching Processes in Semiconductor Manufacturing

Gate Definition . . . . . . . . . . . . . , . . . . . , , . . . . . . . . . . . , , . . . . . . . . . . , , . . . . . ................ Silicides . . . . , , . . . . . . . . . . . . . . . . . . , . . . . . . . . . . Contact Etching . . . . . , . . . . . , , . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . Planarization Etch Steps . . . . . . . ............................... Via Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........... .... ..................... Metal Etching Etch Processing r 4Mb DRAM . . , , . . . . . . . . .. ... .* * ..* * .......* Wafer Preparation . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N-Well . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P-Well Field Implant , , , , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .......................... Is0 Mask . . . . , . . . . . . . . , . . . . . . Connector Mask . . . , , , . , . , . . . . . . . . . . . . . . . . . . . . . . , , . . . . . . . . . . . . . . . . ................ Trench Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . Inter-Polysilicon Oxide Mask . . , . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . , , . . . Gate M a s k . . . , . . . . . . . . . . . . . . . . . . . ... ....................... . . . . . . . . . . . . . . .. . . . . . . . . . .....,.......... LDD Spacer Etch . . Contact Etch . , . . . . , . , . . . . , , . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . Poly 3 Polycide Etch . , ......................................... Contact Mask 2 . . . . . , . . . . . . . . . . . . . . . . . . . . . . . , . . , . . . . . . , . . . . . . . . . . Metal 1 Mask . . . . , , . . . . . . . . . . . . . . . . . . . . . . . . . , . . , . . . . . . . . . . . . . . . . . ............................... Pad Mask;’Polyimide Mask . . . . . . ........................ Summary . . . . . . . . . . . . . . . . . . . . . . . , . . . . . I

References I , . I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I . . . . . . . . . . . . .

321 322 323 326 328 329 331 331 331 334 334 334 334 335 335 336 336 331 331 331 331 338 338

List of Symbols and Abbreviations

293

List of Symbols and Abbreviations B d D E I n n, V r/; 1.

ARC ASIC BPSG CCD CD CMP CVD DRAM ECR IC I LD IMD LDD LOCOS MERIE MFC MOS NIST NTT OES

ON0 PID

Poly PSG RC RF RGA RIE ROI

magnetic field thickness of film drift vector electric field current refractive index density of intrinsic carriers potential threshold voltage wavelength anti-reflection coating application-specific integrated circuit boron phosphorus silicate glass charge coupled device critical dimension chemical-mechanical polishing chemical vapor deposition dynamic random access memory electron cyclotron resonance integrated circuit interlayer dielectric inter-metal dielectric lightly doped drain local oxidation of silicon magnetically enhanced RIE mass flow controller metal-oxide-semiconductor National Institute of Standards and Technology Nippon Telegraph and Telephone Corporation optical emission spectroscopy oxide-nitride-oxide proportional-integral-derivative. A proportional controller which uses an integral of the sensor signal to stabilize the long-term behavior of the control system, and uses a derivative of the sensor signal to adjust for rapidly changing conditions polysilicon phosphorus silicate glass time constant (characteristic time in a resistor-capacitor electrical circuit) radio frequency residual gas analyzer or analysis reactive ion etching return on investment

294

6 Etching Processes in Semiconductor Manufacturing

RSM SEM SILO SIMS SOG SPC SWAMI TEOS VLSI

response surface methodology scanning electron microscope sealed interface local oxide secondary ion mass spectroscopy spin on glass statistical process control side wall mask isolation tetra-ethyl-ortho-silicate very large scale integration

Glossary The point in an etching operation where the desired etching has taken place, and the etching process should be terminated to minimize unwanted etching. The active region between the source and drain in a MOS device. gate: Dielectric isolation, a dielectric layer providing electrical insulation. iso, isolation: First metallic conducting layer. Metal 1: poly, polysilicon: Fine-grained polycrystalline silicon. A conducting layer consisting of a layer of polysilicon and a layer of polycide: metal silicide. A polymer with a high glass transition temperature, used as a dielectric. polyimide: salicide: Self-aligned metal silicide. A hole through a dielectric layer to provide electrical connection via: through the layer. endpoint:

6.1 Introduction

6.1 Introduction Semiconductor device processing consists of patterning dopant distributions, dielectric layers and conductors on the surface of a semiconductor wafer. There are typically ten to twenty of these patterned layers in a semiconducting device. A layer is patterned in a sequence of steps such as: the required layer to be patterned is deposited on the surface; a photoresist layer is then deposited on top of it; the photoresist is exposed through a mask and then developed to make patterned holes in the mask; the underlying layer is then etched through the holes in the photoresist; then the remaining photoresist is stripped off. The scope of this chapter is to describe the dry and wet etching processes used in this pattern transfer technology. The etching technology has become very sophisticated in order to assure that etching occurs only where it is supposed to, and not elsewhere. Extensive use is made of selective etches which preferentially etch one material: ideally, the etch should etch the pattern into the layer and then stop, with no attack on the layer below, in order to compensate for the inevitable variations in etch rate across a large wafer. In addition, the shape of the side walls of the etched region becomes increasingly important as the feature size on ICs decreases. The primary focus of this chapter will be on dry etch processing in the silicon based IC industry with emphasis on techniques and etch tools which have been demonstrated to support volume production. The industry has moved substantially from wet etches to dry etches for reasons discussed below, and that trend is continuing. The use of wet etch steps (including cleans) is also an important issue because these steps must be well understood prior to either

295

replacing them with dry processing or continuing to use them. The structure of the chapter is to first discuss etch equipment and plasma generation technologies, then to discuss diagnostic techniques for process control and troubleshooting, and finally to discuss the specific etch processes used in IC manufacture. A process flowsheet for a 4 Mb DRAM will be used to discuss both the process steps and the interactions which can occur between them. See also Chap. 10, Sec. 10.5.

6.1.1 Wet Etching Wet etching for both cleaning and pattern transfer dominated the IC industry until the mid 1970s, when critical dimensions began to approach film thicknesses (Irving, 1971; Vossen and Kern, 1978). All semiconductor wet etching processes have had the same basic limiting factor: isotropy. Whether etching oxide or metal, the amount of lateral etching nearly always approximates the vertical etch depth. Along with the basic technology limiting quality of isotropy, wet etching also suffers from the downtime created by bath changes and poses a safety hazard even during normal operation. Regardless of the safety and technology related problems, wet processes are still widely used in the cleaning and preparation of wafers in the early stages of a process flow. Wet cleans for the complete removal of “buffer” or sacrificial films used during implantation and hard masks are still widely used. However, because of the problems outlined above, wet etches have been replaced by dry etching for pattern transfer even though the dry processes were originally not anisotropic.

296

6 Etching Processes in Semiconductor Manufacturing

6.1.2 Dry Etching The use of dry etch processing grew from stripping resist, thin nitride etching, and the isotropic etching of gate material, contact and via etching, and aluminum, to the highly anisotropic and selective etching of the same films. By the time the 1 Mb DRAM was in production in 1987, dry etching processes dominated all pattern transfer steps. Increases in IC performance requirements drove the development of etch tools that had better C D (critical dimension) control. better selectivity to mask and underlying films, and better particle and foreign material control. Cost (including operating costs. maintenance and downtime) became important once hardware that met product performance specifications was available. Damage issues, especially lattice and gate oxide damage, became process and hardware drivers in the late 1980s as the 1 Mb DRAM was being developed. More attention was focused on yield loss from microcontamination. Finally, the drive for more efficient production capability drove etch equipment to be designed and assembled to run for longer times between failures and between scheduled maintenance procedures. Both equipment suppliers and equipment users began to include measurements of, or at least expected, values of uptime, availability. mean time (or mean wafers) between failures and mean time to repair in their equipment performance specifications. It is normal for current etch tools to operate for more than 200 hours between failures. Many reviews of etch processing can be found in the literature: some are mentioned below. Early descriptions of the mechanisms responsible for RIE etching were presented in detail by Coburn (1982). An overview of chemistry and etch mecha-

nisms by Flamm and Herb (1989) uses classical engineering concepts of similarity variables to describe etch processing. Discussion of earlier technologies, including some considerations of radiation damage and sodium contamination was published in 1979 (Kalter and van de Ven, 1979). More recent discussions of etching (Powell and Downey, 1984; Coburn et al. 1986; Bondur and Turner, 1991) cover most of the current issues in plasma etching. Good sources for the latest results and trends in plasma processing are the yearly proceedings of the Electrochemical Society, the Materials Research Society, the American Vacuum Society. and SPIE meetings. The proceedings of the Dry Processing Symposium held every fall in Tokyo are also a valuable source of information on new processing techniques and are available in English. 6.1.3 Etch Control and Metrology Whether wet or dry technology is used, some form of control must be imposed on the process. To d o this, three basic components are necessary: a) sensing technology; b) control algorithm; c) communications among subsystems. Also, since no manmade system is perfect, some strategy to identify and correct fault(s) which cause the process to deviate from optimum or even catastrophically fail should be available, including the metrology tools to identify the fault(s). With regard to control technology, the objective is simply to maintain a consistent reaction throughout the process until the “endpoint” is reached. The endpoint of a process is attained when the film to be removed has been cleared. Therefore, the argument could be made that even if the process characteristics drift, as long as an endpoint can be detected, the run-to-run

6.2 Equipment: Description of Hardware

results should be similar. For this simple reason, the most important sensing technology on any etch process is an endpoint monitor. However, variations within the process can adversely affect run-to-run repeatability, so that process sensors and diagnostic tools are also important to successful production processing. In the early years of IC manufacturing, not much attention was paid to control techniques. Equipment was set up manually and operation verified by checking the various setpoints As repeatability became more important with increasing production volume and costs of manufacturing, the need for automated control of equipment operation became evident. Today, manufacturing is faced with the need to increase the return on investment (ROI) while meeting the needs of advanced product designs. It is evident that the control algorithms implemented in the late 1970s and early 1980s will not meet tomorrow’s process performance requirements and must be updated. The conflict between manufacturing ROI and improved performance requirements is not trivial and will require novel implementation of sensor and control algorithm technologies.

6.2 Equipment: Description of Hardware This section presents general descriptions of the various types of etching equipment used in manufacturing environments today. The basic physics and chemistry that differentiate various types of plasmas are discussed. Also, some indication of the track record of different types of dry processing equipment in industry is included. One important way to differentiate various styles of the same type of equipment (i.e.,“RIE etcher” or “microwave etcher”) is

297

in the techniques used a) to control the process and b) to terminate a step in the process. Batch size and level of integrated processing are also important differences between reactors of the same type. Included in control strategies are diagnostics which are commonplace (MFCs, leak rate tests) and strategies which are not yet in common use (for example, Langmuir probes for density evaluations). 6.2.1 Wet Sinks

Most wet process steps perform cleans: these steps serve to either prepare a surface for a subsequent step or remove a film from the wafer surface. Wet cleans are technically complex because different cleans leave different surface conditions on the wafer. However, pattern transfer is not usually accomplished with wet steps in today’s manufacturing technology because they produce isotropic profiles. The most important control required in wet stations is to control particle contamination by filtering and by preventing suspensions from forming particles downstream of the bath filters. The process flow discussed in Sec. 6.5 uses standard sinks for the various cleaning procedures including the RCA, phosphoric/HF, buffered HF, sulfuric acid/hydrogen peroxide steps. Most wet etching is still performed in an immersion mode. The precision of the removal is controlled by the temperature of the etchant, the time of immersion and the composition of the acid etchant. The composition of the etchant is adjusted to produce a controllable etching time, generally between one and seven minutes. Below one minute, the time for the operator to remove the wafers from the bath becomes an appreciable fraction of the etching time, thus introducing variations in the etch results. Above 7 min, the photoresist tends to

298

6 Etching Processes in Semiconductor Manufacturing

lift, resulting in excessive undercutting. A typical target etching time is 5 min. Spray applications, especially those applied when the wafer is rotating, result in a more uniform process. However, since spray etch processing has not been completely spray automated, most wet etching is still immersion based. Kern (1990) has reviewed wafer cleaning technology and discussed both spray and immersion cleaning techniques. Silicon wet cleans were studied by van den Meerakker and van der Straten (1990). Some new dry cleaning techniques which replace sinks include anhydrous H F wafer cleaning: see Deal et al. (1990) and Miki et al. (1990). 6.2.2 Dry Processing

A useful model of both dry process equipment and the processing itself is the idea that dry process results come from a balance between physical and chemical processes at the wafer surface. Figure 6-1 illustrates how a process dominated by sputter etching at low pressure and high ion energy can be compared to a process dominated by chemical etching at high pressure and low ion energy. Typically, LOW

PRE SSURF

1 1

HIGti

PHYSICAL PLASMA PROCESS

BALANCtD

HIGH

NF I N (;Y

LOW

sputter etching processes provide anisotropic profiles but do not provide selective etching between the different films on the wafer such as the photoresist, the etch film, and the layer under the etch film. Faceting of the mask is also a characteristic of sputter etch processes. At the other extreme is purely chemical etching, often referred to as plasma etching, which usually provides excellent selectivity between films that have different chemical composition but tend to etch with isotropic profiles. Successful etch processing occurs when the correct balance between these two extremes is struck. Figure 6-2 illustrates the same trade-off in terms of the effect on etched features. The term “reactive ion etching” or “RIE” is used to describe etch processes which combine both physical and chemical processes to give the desired balance bet ween anisotropy, selectivity, and damage. This concept, the idea of considering process results as a balance of two types of processes - physical and chemical will be used discussed further below. During the discussion of the tool designs, the reader should remember that each tool design has a certain range of ion energies, ion densities and neutral densities in which it

SPUTTER ETCHING

REACT1 VE ION

ETCHING

PLASMA ALl:!prPROCESS

PLASMA ETCHING

Figure 6-1. Physical and chemical processes in a plasma.

6.2 Equipment: Description of Hardware SPUTTER ETCHING

(PHYSICAL)

REACT1 VE ION ETCHING

LOW

HIGH

299

HIGH

t t

SELECT1 VI TY

ANISOTROPY

HIGH

DAMAGE POTENT I AL

LOW

Figure 6-2. Results on the wafer for physical and chemical etching.

Table 6-1. Trends of DRAM process technology Characteristic

1 Mb

4 Mb

16 M b

64 M b

256 M b

1.3-1 0.3-0.4 3.0-2.5 2 1.o 1.2 200

1.0-0.7 0.2-0.3 2.0- 1.5 3 0.7 1.o 150-100

0.5 0.1 -0.2 1.5 4 0.5 0.7 125

0.35 0.12 1.2 5-6 0.35 0.5

polycide

Storage capacitor

buried/ stacked

buried/ stacked O N 0

100 pol ycide/ refractory buried/ high E

0.25 0.08 0.9 6 0.25 0.35 I80

Wafer size (mm) Production

125-1 50 1987

150 1989

150-200 1992

200 1995

Design rule (pm) Overlay (pm) A1 pitch (pm) Conductor levels Contact size (pm) Via size (pm) Gate oxide thickness Gate conductor

(A)

can operate while still providing reasonable etch rates. For example, RIE tools are not usually operated below 25 mtorr because the large RF voltages required to sustain low pressure capacitively coupled plasmas result in excessively high ion energies.

6.2.3 Etch Hardware Historically, dry etch equipment developed from sputter etch tools (dominated by physical etch mechanisms) and from isotropic barrel etchers (dominated by chemical etch mechanisms) into what have been termed RIE etchers and plasma etch-

polycide,’ refractory buried! high E 200 - 300 1998

ers. In these etchers, the etch chemistries involve a balancing act between ion and chemical dominated mechanisms. Table 6-1 summarizes the pattern transfer requirements of existing and evolving technologies (Cook, 1991). The need for better CD control, selectivity to mask and underlying films and improved damage control has led to newer types that combine multiple sources of excitation energy. In these evolving tools, the functions of plasma generation of sufficient numbers of ions and neutrals are decoupled from the control of the ion energy at the wafer surface. Typically, the source is physically removed from the region near the wafer and is called

300

6 Etching Processes in Semiconductor Manufacturing

a “remote source”. These include low pressure etchers such as low pressure microwave, helicon, and ECR sourced tools as well as high pressure microwave sources which are typically used for isotropic, low damage processing such as resist stripping. The tools described below are summarized in Table 6-2. Details of their operation have been specifically discussed by Fonash (1985):a good review of equipment choices and a discussion of their physical characteristics is provided by Broydo (1983).The typical pressure ranges that each type of tool operates in as well as the range of ion energies at the wafer surface are listed in Table 6-3. Typical values for n i , the ion density, are also listed in this table. Note the relatively high ion energies which always accompany RIE and Magnetron tools compared to those obtained with barrel and ECR tools. These estimates of

energy describe values typical for real operating conditions that give reasonable throughput. If low ion energies are required for future processes, the parallel plate reactors will not be able to meet this requirement. The flowing sections detail the characteristics of equipment presently used in the manufacturing environment.

6.2.3.1 Barrel Etchers

A typical barrel etcher is shown in Fig. 6-3a. The chamber consists of a vacuum vessel, large enough to hold 1 or 2 boats of 25 wafers. The RF electrodes are usually located outside the quartz vessel and consist of coils or simple electrode pairs. Inductively coupled geometries in which the outer electrode consists of a number of turns of copper tubing wound around the vessel often actually operate with capacitive coupling. Ion-surface reactions driven by the difference between Table 6-2. Most common plasma tools used in IC fabthe wafer surface and the plasma potential rication. are reduced by use of an internal metal Common Source type Used in shield (termed an “etch tunnel”) which name makes the wafer region electric field-free (and, incidentally, makes R F matching easL or C coupled strip is0 etch Barrel ier and more stable). Tunnels usually lower 13.56 M H z dielectric etch Plasma etch rates and increase across-the-chamber parallel plate nitride stripping. These processes are rela13.56 MHz metal, poly RIE tively insensitive to long overetches so 2456 M H z (typ) resist strip (hi P) Microwave poor across-the-chamber nonuniformities remote resonant poly, metal ECR are often acceptable. Even so, slow mass transfer between the edge and center of the wafers often requires that the space beTable 6-3. Comparison of different types of etch tools. tween wafers be increased to as much as Type P Range Miwmax (eV) Typical n , 10 mm (reducing the load size) in order to of tool (torr) (at surface) (~rn-~) maintain across-the-wafer uniformity. Thin nitride etch (isolation mask, for example) 0 1 10 Barrel 3 20 1012 1013 and even polysilicon gate etch processes Plasma 1 5 100 loo0 5 x 1012 RIE i00,iooo 1 0 ~ - 1 0 ~ ~ have been run in production with these 005 0 5 5011000 109 1011 Mag 001 o 1 tools. One 4 M b fab has used a barrel ECR 5 500 1011 1013 0001 0 2 etcher to clean poly gate lines after partial (at source) RIE etch: the reason for this is to avoid

6.2 Equipment: Description of Hardware

gate oxide damage on their devices. The use of barrel etchers is in general not popular because these tools usually have high particle counts and because their capabilities can be duplicated by downstream single wafer tools like microwave etchers.

6.2.3.2 Plasma Etchers So called “plasma etchers” (Fig. 6-3 b) are a high pressure configuration of parallel plate RIE etchers with mechanical differences that permit their operation at high pressures (up to 10 torr) and high power densities (up to 3 W/cm2). The main mechanical difference between them and RIE tools are in the physical design of the electrodes and their use of a relatively small (about 10 mm) electrode gap. These tools have been used extensively for high speed single wafer dielectric etching and operate with a mix of chemical and physical processing. The utility of the design arises from the increase in etch rate that occurs as the electrode space is decreased below 10 mm in the few torr pressure range. The typical design trade-off is the balance between process stability and uniformity for larger gaps and high rate for smaller gaps. For certain layers, these tools are successful in 4 Mb DRAM production technology. They are characterized electrically by a nearly zero D C bias voltage, a relatively high plasma potential, and high power densities. They frequently use coolec‘ \!infer chucks and lower frequency (100-400 kHz) excitation for dielectric etch. Some have the capability to split the applied power between the two electrodes: this helps control geometric asymmetries inherent in any reactor and permits truly “anode” or “cathode” coupled operation. The control of damage that is achieved with these machines stems from their high pressure operation.

30 1

6.2.3.3 Reactive Ion Etchers Reactive ion etching (RIE) tools are characterized by a large ( > 2 : 1) area ratio between the anode and cathode (Coburn and Kay, 1972), operation in the 20400 mtorr range and have been designed in both single wafer and batch configurations. The schematics in Fig. 6-3 c show the important components of an RIE etch tool: a blocking capacitor is in series with the power supply (see Kohler et al., 1985, for capacitor discussion). The wafers are placed on the cathode (the smaller, powered electrode for this design). These are the tools which support virtually all high resolution pattern transfer etch processes in the industry. The low pressure operation provides good mass transfer which reduces microand marco-loading effects. The diode performance of the plasma provides high ion energy at the wafer surface for ion assisted etching and low ion energy at the anode for reduced sputtering of the chamber walls. The success of these tools stems from their ability to operate in physically dominated etch modes (oxide, nitride, and trench etching, for example), chemically dominated modes (aluminum etching) or mixed modes (poly/silicide, or A1-4% Cu etch). They also have the advantage of widespread acceptance and understanding of their mechanical and electrical components: that is, people know how to adjust setpoints to obtain different wafer results and how to keep the equipment operational in production. Most RIE tools currently available are evolutionary in that they represent continuously improved designs of a mature technology. One limitation of RIE tools has to do with the lowest pressure at which they can be usefully operated. Large R F voltages are required to maintain them at low ( 4 - 1 0 0 mtorr) pressure and typical

302

6 Etching Processes in Semiconductor Manufacturing

(a)

r - - - - - - - -

' 3 56 MHZ

If* ANODE CATHODE

Figure 6-3. Schematic view of typical etchers: (a) barrel; (b) "plasma etcher"; (c) RIE ctcher: (d) microwave etcher; (e) ECR etcher; (f) "NTT" ECR design

6.2 Equipment: Description of Hardware

303

304

6 Etching Processes in Semiconductor Manufacturing

power densities (1 W/cm2). These high voltages result in large voltage drops across the cathode sheath and in ion damage on the wafers: lattice damage and etchant implantation (Current et al., 1989) can be a dominant process. Thus, the parallel plate RIE etcher has some limitation with respect to the lowest pressure at which it is useful, especially for sensitive etch steps like gate and contact etch. Note from Table 6-1 that the 4 M b process requirements are met with this technology. The operating voltages of RIE tools can be reduced by applying a magnetic field to the gas gap: a number of different configurations of such magnetically enhanced RIE (MERIE) or magnetron tools are used in industry.

6.2.3.4 Remote Plasma Generation: Microwave and ECR Microwave strippers (Fig. 6-3 d) are one type of remote source or downstream etch configurations. They consist of a microwave plasma source located upstream of the wafer, a method of distributing the source effluent uniformly to the wafer surface, and often include radiant heating and passive cooling for wafer temperature control. The temperature control is critical for resist strip applications which run at a few torr pressure and which have a temperature sensitive strip rate. External wafer biasing is common in lower pressure microwave systems (see Fig. 6-3e) which perform anisotropic etching: systems are currently available to preform resist strip, metal etch and gate etch. Most microwave etchers use closed loop temperature control of the RF biased wafer chuck to prevent overheating of the wafer. Finally, Fig. 6-3 f shows the “NTT” ECR (electron cyclotron resonance) design: here the effluent from the tubular resonant re-

gion reaches the wafer directly. The distance between the source and the wafer controls the balance between uniformity and rate. The rationale for this type of tool is that the process can run with very low ion energy (and low ion current to the wafer surface, if necessary): ion densities as low as 107/cm3have been measured in argon at 2 torr a few cm downstream of the microwave source (Cook, 1991). This is expected to reduce damage on the wafer and also reduce surface heating. In addition, the microwave plasma can be operated at pressures lower than an RIE parallel plate system: this is expected to provide better particle control by reducing deposition. Better loading performance is also expected since the pressure is lower. The ECR source is similar to a microwave source in that it uses a 2.45 GHz driving frequency. It also uses a localized magnetic field of 875 Gauss to generate a resonance between the electron gyro frequency and the frequency of the applied field. ECR plasma sources operate effciently at low pressure ( < 1 mtorr) and can generate high plasma densities (up to 1Ol2/ cm3). Operation at true resonance also generates a high energy tail on the electron energy distribution: these electrons can generate high energy radiation (soft X-rays) which is a new possible source of device damage (Buchanan and Fortuno-Wiltshire, 1991). ECR tools are of interest to many device manufacturers but have not yet matured to the point where they are in common production use. Other sources such a helical resonators show promise but are not currently available on production hardware. The attraction of the resonator design is that it is relatively simple mechanically, that is uses RF, not microwave frequencies, and that the plasma is inductively coupled so low plasma potentials are possible, even at low pressure.

6.3 Endpoint, Diagnostic and Control Techniques

6.3 Endpoint, Diagnostic and Control Techniques Metrology (the science of measurements) and communications are as critical to the success of a process module as any hardware component. The ability to known when a process is complete, and to avoid unnecessary exposure of underlying films to subsequent processes, is of utmost importance. Not only does endpoint detection reduce the propensity for damage to underlying films, but it can also enhance run-to-run uniformity. Hence, it is desirable to have an endpoint detector for any etch process. It is common for engineers today to use designed experiments, or response surface methodology (RSM) techniques to establish operating points and characteristics of their processes. A major drawback of these procedures is that, although they allow for multivariate input, they only provide optimization for a single output for control of the system, rather than providing for the optimization of several control outputs. Exceptions to this rule are neural networks, which are truly multivariate input and output, but techniques such as these are not commonly in use today. The absence of multivariate input and output techniques creates two problems. First, since all equipment fails at some point in time, the need for diagnostic tools in troubleshooting a failed process is a “must”. Also, it is important to realize that the purpose for using designed experiments is to identify a window of operation which is stable and meets specifications. As circuit designs become more complex these specifications get tighter and the need to maintain process optimization in a smaller window of operation becomes increasingly difficult. Add to this the problem of responding to the variability of incoming material (sometimes drastic and often in-

305

tentional as in the case of ASIC design), and a second problem arises: the dynamic control of the process tool. In this section each of these three topics will be discussed with regard to current and future process requirements. It should be noted that due to the time frames of interest, emphasis will be given to technologies applicable to dry processes only. 6.3.1 Endpoint Monitors Due in part to the normal surface topography of IC designs, film thickness will vary over a wafer. This necessitates a certain amount of “overetching”, i.e., etching beyond the point where the top film has begun to clear. However, as mentioned above, it is important to minimize the exposure of sensitive underlying layers such as gate oxide. Often this means converting from a very fast anisotropic etch with poor selectivity to the underlying film, to a much slower less anisotropic process with higher selectivity. This conversion from high anisotropy can result in loss of dimensional control if not minimized. Therefore, endpoint detection is an important part of process control. Initially the concept of determining when a very thick film (a few thousand angstroms) clears seems difficult. However, inspection of the actual etching process reveals numerous opportunities for signal generation and monitoring. Flamm and Herb (1989) give an excellent account of film volatilization and the chemical makeup of the plasma throughout a dry etch. It is easy to conceive that if one could monitor a signal proportional to the chemical composition of the plasma, such as density of the etchant or a by-product of volatilization, that the level of this signal would change as the film is removed. This is the basic method of operation of most end-

306

6 Etching Processes in Semiconductor Manufacturing

point detectors. Another type of monitor makes use of the optical properties of the film being etched. As the film is removed the optical properties of the wafer surface change and can be monitored to detect endpoint. The following subsections are a review of the most widely used endpoint monitors. 6.3.1.1 Optical Emission Spectroscopy (OES)

All plasmas emit light at some wavelength. The most common example of this is a man-made plasma contained in a fluorescent lamp. Plasmas used in dry processing of simiconductors also emit broadband radiation. Emissions can emanate from etchants, etch products or their fragments. There are numerous manufacturers of OES equipment. There are three basic types: a) multichannel analyzers with up to 1024 light sensitive pixels; b) scanning monochromator with typically only one light sensitive element; c) fixed wavelength. The most common is the scanning monochromator. Figure 6-4 contains an actual endpoint trace taken with a scanning monochromator type system. Table 6-4 lists characteristic emitter wavelengths for a variety of film/etch chemistry combinations. Endpoint detection by OES has been used quite successfully for many years. Systems can be cheaply constructed or purchased at a reasonable price. The most expensive and flexible is the multichannel analyzer with the capability to capture highly temporally resolved broadband snapshots of the process. The least expensive systems are the fixed wavelength variety. Functionally, these systems work as well as any of the three, however, the user must know in advance of purchase, exactly which wavelength will be monitored. For

Overetcp h

c ._

x .L

Time

Figure 6-4. Typical optical emission endpoint signal taken from MERIE poly etch.

Table 6-4. Characteristic wavelengths for optical emission endpoint monitoring via selected species in various etch chemistries. Film

Etchant

Wavelength

Emitter

('4 AI cu Cr Resist

Si,N,

SiO, (P-Doped)

2614 3962 3248 3579 2977 3089 6563 6156 7031 7770 2882 3370 7037 6740 1840 2535 7037

AlCl AI cu Cr

OH H 0 F SiF Si N2

F N

co P F

fabrication facilities with changing loading, multiple processes, resists or product designs this may not be practical. Therefore the most common unit found in use today is the scanning monochromator system, which allows for changing the monitored wavelength. As good as these sound, not everything is perfect with OES endpoint detection.

6.3 Endpoint, Diagnostic and Control Techniques

The first problem encountered in the normal fabrication environment is the availability of a port on the chamber with a good view of the discharge. Although some older machines may not have such access, most newer equipment does. The next obstacle which a process engineer must overcome is finding a relevant wavelength to monitor. Plasmas emit broadband, and there is much light available, but usually the intensities of only a few wavelengths correlate with what is happening at the wafer. Also most detectors are sensitive only in the very near IR through the very near UV portions of the spectrum (200800 nm) so much information relating the heavy molecules typical of a process plasma is lost. Even if the installation of an OES system is successful and a spectral feature which can serve as an endpoint detector can be identified, clouding of the window is one last problem which can never be solved. Most OES systems use a quartz window for optimum transmission, but the quartz is etched, or deposits form on it, just as they do on a wafer or on the chamber walls. So the window must be periodically cleaned. Cleaning is a major problem for very low pressure tools, such as ECR, or C1, based process systems which should be exposed to atmosphere as little as possible.

6.3.1.2 Laser Interferometry Another production proven endpoint technique is based on the reflection of monochromatic light from the various film surfaces on the front side of a wafer during process (Donnelly, 1989). Monochromatic light, usually from a laser, has a reflected intensity which depends on its wavelength, the index of refraction and thicknesses of the films in the stack. The reflected intensity depends on constructive and destructive interference of light reflected from the various

307

interfaces. This phenomena is used to monitor the thickness of materials such as polysilicon, silicon oxide and silicon nitride. When a laser, such as He-Ne (632.8 nm) is directed at the wafer surface, interference maxima and minima occur when twice the thickness of the film, d, is a multiple of the wavelength, I,, divided by the refractive index, n

d = rz (142)

(6-1) The light intensity reflected from these silicon based films varies sinusoidally with film thickness. The etch rate can be monitored by determining the time interval between a maxima and minima on the signal trace. This technique permits real time monitoring of etch rate. Hence, changes caused by variations in the composition of the film with depth can be detected. Laser interferometry has been used in a wide variety of etch processes due to its adaptability. Even in metal etching where the film is reflective, interferometry can be applied. As the reflective metal film clears the optical characteristics of the underlying film become apparent in the amount of laser light reflected. Figure 6-5 shows representative laser interferograms for (a) metal etch clearing followed by polysilicon etch, and (b) silica being stripped from a silicon substrate. A major problem with laser interferometry is its lack of ability to deal with etch non-uniformity. Interferometric techniques by nature must operate with a very small spot size (IO-’ cm in diameter) in order to achieve a sharp interferogram. Therefore since endpoint determination is made from sensing a small area, variations in film thickness or across the wafer etch rate will produce an unrepresentative sample. This is especially serious with batch processes or with single wafer etches which sacrifice selectivity for rate and anisotropy. A sec-

308

n "

6 Etching Processes in Semiconductor Manufacturing

I 13

I 14

I 15

I 16

ELAPSED TIME (MINUTES)

.-PLASMA

END P O I N T 1

4 40

20 t (min)

Figure 6-5. Typical laser interferometry traces for (a) metal over oxide. and (b) polysilicon over oxide.

6.3 Endpoint, Diagnostic and Control Techniques

309

Figure 6-6. RGA output from CF, plasma. 4

Mass

oridary issue, which may make the measurement impossible, is the requirement for normal incidence of the laser on the wafer surface.

6.3.1.3 Residual Gas Analysis/ Mass Spectroscopy As mentioned above, the plasma chemistry changes during the etch process from start to finish. This change is usually based on the consumption of either the etchant or the film being volatilized, their density should be inversely proportional to each other. Therefore, temporally resolved information relating to the density of various plasma constituents, should make endpoint determination trivial. This is the basic idea behind using mass spectroscopy or residual gas analysis (RGA) for endpoint detection. However, RGA and OES share the similar problem of identifying the critical peaks to monitor in the presence of an intense background. As a matter of fact, RGA is probably worse, since it looks at a much wider portion of its spectrum than OES. Figure 6-6 shows a typical RGA output. A more critical problem arises when the details of RGA sampling are examined. The most common mass spectroscopy systems in use today are based on the quadrupole mass analyzer which requires a low

operating pressure ( < torr). This low pressure is reached by placing a sampling orifice between the differentially pumped quadrupole region and the process gases. Depending on the RGA manufacturer, the sampling orifice may be a small bypass valve or a pin hole aperture. After being accepted into the differentially pumped region the sampled particles pass through an ionizer and then must travel some distance to traverse the quadrupole. The distance covered in exiting the plasma, passing through the sampling port and ionizer and then the quadrupole adds up to many, many mean free paths. The probability of any particles, especially a large charged particle, making such a trek without incurring a collision is small. Therefore it is safe to assume that for the most part what we see at the typical RGA display is a limited representation of the actual chemistry present near the wafer surface. A second problem arises for the use of RGA in newer magnetically enhanced machines. The principle of operation for quadrupoles is based on the interaction of a controlled electric and magnetic field with a charged particle. In the case of MERIE or ECR type tools, the externally imposed confinement fields may severely interfere with the quadrupole analysis field, even to the point of rendering the RGA useless.

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6 Etching Processes in Semiconductor Manufacturing

This is not to say that RGA is not a useful metrology tool. The problem of external magnetic field interference can be solved with special shielding. The problem of not truly sampling plasma at the wafer can be solved with special probes, although these may shadow the wafer. The dificulties do, however, tend to make RGA more of a development tool than a production sensor (Vasile and Dylla, 1989; Manos and Dylla, 1989 b). 6.3.1.4 RF and Bias Voltage

It is intuitive that as the plasma chemistry changes during the etch process so do the plasma impedance and the sheath characteristics. As the impedance and sheath change so do the RF voltage, current, phase and, providing the power is not controlled by the bias, so does the self-bias voltage. Monitoring of the RF network parameters is the most direct means of non-invasive plasma metrology because the signal-to-noise ratio is very favorable and, since the measurement is usually made at the wafer electrode, the discharge is sampled in a relevant area. There are no problems with shadowing the wafer or clouded windows involved in making RF measurements and implementation of voltage and current sensors can be almost trivial. As a potential endpoint monitor, RF analysis benefits from two different phenomena which complement one another. First, the constituents of the discharge change throughout the etch process which result in a changing impedance. Being able to measure the bias voltage, the current to the plasma, as well as the impedance of the plasma makes RF monitoring near the wafer surface a powerful endpoint detector. Second, since the wafer serves as an exposed electrode, and this entire surface changes (i.e., the electrical

properties of the powered electrode change), the entire wafer surface contributes to the endpoint monitor. This removes the problem of limited spot size associated with laser interferometry. Also with RF metrology, even though the spectrum may be broad there are only discrete frequencies contained within it (the fundamental and its harmonics). This makes identifying the proper endpoint signal much easier than with either OES or RGA. Figure 6-7 contains traces of the RF voltage, current, phase and the self-bias voltage. Of the relevant RF parameters, only self-bias is currently measured on a routine basis. Two problems exist with making self-bias voltage measurements. First, and most important, is that this is a DC voltage measurement which requires an ohmic path to the plasma exposed powered electrode surface. Many modern process tools use anodized electrodes which will stop the DC current flow to any resistive voltage divider set up to measure the self-bias voltage. This makes it impossible to obtain an accurate or even representative self-bias voltage measurement. The second problem is that several types of process tools use servo control of the power in order to keep the bias voltage constant. Therefore, as a film clears, the bias voltage does not change, since the power changes to keep the bias constant. It is anticipated that R F monitoring will find increasing use, since OES sensitivity is already at the limit of detection in some processes such as contact or via etching. OES is often not sufficiently sensitive for dependable endpoint determination, and it has been demonstrated that R F can detect endpoint in cases where OES cannot (Turner, 1991a). Systems for simultaneously monitoring the RF voltage, current, phase and harmonic content are becoming available and will probably

6.3 Endpoint, Diagnostic and Control Techniques 11s

31 1

118 117

-E

116 116 114 113 112 111

84.6 84.46 84.4 84.36 84.3 84.26 84.2 84.16 84.1 84.06

4.4

Ek 4

4.36 4.3 4.26 4.2 4.16 4.1 4.06 0

Time (s)

Time (s) 0

-320 -326

-F

-330

-340 -346

8 I I

-336

-360 -366 -360

Figure 6-7. RF parameter endpoint signals: voltage, phase, current, self-bias.

31 2

6 Etching Processes in Semiconductor Manufacturing

come into use as standard endpoint monitors because of their capability and because the monitoring system can be incorporated into the equipment needed for power control.

plasma or the incoming wafers. Proper metrology practices can remove all but the most catastrophic of these by providing timely information relating to the overall state of the process module. We will begin this discussion, as an etch begins, with the machine settings.

6.3.2 Diagnostic Tools/ Metrology for Process Control

The previous section dealt with stopping the process at the appropriate time to improve run-to-run uniformity and insure minimal damage to underlying films. This section deals with the metrology devices which can be used to correct a process either prior to going out of control, or after a control failure has occurred. Diagnostic tools and metrology for process control are based on both machine related and process related measurements. This is to say that etching can be viewed as having three components: a) the machine which is used to generate the plasma; b) the plasma used to generate the chemicals and kinetics; c) the wafer and etch results. This modular relationship can be best represented mathematically by the following three relations: etch parameters

(time, plasma (6-2) parameters)

plasma parameters = F (time, machine (6-3) parameters) etch parameters = F (time, machine parameters) (6-4) The time has been included explicitly to emphasize that this entire process is dynamic and time dependent. The primary concept intended to be conveyed by these equations is that machine settings are used to generate a plasma with certain properties and these properties in turn determine how the wafer etches. Failures, drifts, or out of control situations arise from the variability of either the machine, the

6.3.2.1 Machine Related Metrology

All plasma process tools have some amount of machine related metrology. Even the very first machines had RF power meters and pressure gauges. Today’s equipment is much more complex with mass flow, temperature, one or more R F generators, pressure, electrodes gap, magnetic field, backside cooling pressure, all requiring sensory equipment to operate. But the real problem is not how many measurements to make, but how to make them correctly, i.e., where, when and at what frequency. It is also important to remember that production versions of plasma etchers have been in use for the last decade and made many valuable contributions to the fabrication capability of advanced circuit designs. The goal of this section is to point out methods and techniques for improving and extending the capabilities of plasma etching into the next decade. R F Poirser Metrologj,

Present R F measurement practice provides a good example of misplaced metrology. Plasmas are by nature nonlinear phenomena with highly variable impedances. This necessitates the use of an impedance matching network to effectively couple the RF energy from the 50R output on the generator to the powered electrode in the process chamber. These matching networks are made of real, not idealized resistive, inductive and capacitive components,

6.3 Endpoint, Diagnostic and Control Techniques

which create losses due to 12R heating and other radiative effects. Also, matching the variable impedance network to the plamas impedance most often results in tuning to a minimum reflected power, so that some of the incident R F energy is reflected back to the generator. Yet even today, with this understanding, RF power measurements are still made at the output of the generator rather than at the powered electrode. Figure 6-8 illustrates present, correct implementation of RF metrology. A second serious error is also being made routinely in the measurement of delivered RF energy. R F power process setpoints are typically specified in terms of watts. However, it is important to remember that power is the product of the instantaneous voltage and current. Assuming that the voltage and current are both sinusoidal, the average power is given by average power = voltage x current x x cos(phase) (6-5) Since plasmas are by nature nonlinear, the sine-wave assumption of Eq. (6-5) does not rigorously hold, but does serve as a good approximation. Since the etching behavior of a plasma depends on the voltage and current, as well as on the power, it is easy to see that simply specifying the forward power does not properly define the operating conditions. Better control can be obtained by installing proper voltage, current, and phase sensors as part of the RF generator control strategy.

Vucuum Metrology All plasma processing is done at a reduced pressure. Therefore requirements for creating and sustaining a vacuum, for gas handling and delivery, for pressure measurement and control, are all fundamental to dry etching. Lower pressures are used

313

Figure 6-8. Present, improved placement of RF metrology.

more in some types of process tools than others. ECR, for example, require a low operating pressure. The lower the operating pressure, the lower the base pressure which must be used to insure a clean starting chamber. Achieving a low base pressure is usually a function of the pumping capability and the size, type and number of leaks in the vacuum chamber. Pressure metrology has been available for the last century and many improvements have been made resulting in the present capabilities. However, it is important to realize that the chemicals used in most etching processes either attack or alter the measurement capabilities of modern pressure transducers. Similarly, the mass flow controllers (MFCs) used to deliver regulated amounts of process gas to the chamber are adversely affected by use. These MFCs are made from high quality materials but are still subject to the corrosive nature of process chemicals such as Cl,. There is no immediate cure for the degradation of pressure flow transducers. However, simple techniques and available calibration systems can make significant improvements in the reproducibility of transducer performance. Again the problem of making measurements in the wrong

314

6 Etching Processes in Semiconductor Manufacturing

place jeopardizes the overall metrology process. An MFC, for example, can be set to control the gas flow based on a measurement of the flow and a conversion coefficient for the type of gas. This metrology process gives no information relating to the state of operation of the MFC. Gas is allowed to flow through the MFC by opening and closing an electrochemical valve. By simply measuring the drive current to this valve the time remaining before it fails can be monitored and appropriate actions taken to plan for the replacement of the unit prior to failure. Due to the corrosive nature of many process chemicals it is not practical to remove an MFC for calibration. Therefore, a volumetric technique is presently used to check MFC calibration. This “flow cal” technique is based on the assumption that the pressure transducer has not changed, however, as mentioned above, this is usually not the case. Presently there is a commercially available solution for this problem which makes use of a wellmaintained NIST traceable capacitance manometer (Chapman). This transfer standard calibration system is mounted onto the etcher under test and is used to develop a transfer function correlating the maintained manometer and the etcher’s transducer. Simple but effective techniques such as this will improve the reproducibility of the overall vacuum and gas handling system.

1”

Magnetics Metrology

Many modern “high density” etch systems make use of magnetic confinement techniques to create or sustain certain plasma characteristics. Response surface models generated on some machines indicate that the magnetic field is a prime independent variable. That is to say, it has a very strong influence on the resulting etch parameters. This is easy to understand with regard to uniformity. Figure 6-9 illustrates the establishment of a drift vector created by the interaction of an electric and magnetic field ( D = E x B). The drift phenomena affects all charged particles and can drive the uniformity of etch rate by causing the formation of etchant to be located off the wafer surface. The results of the etchant formation dislocation is that the etchant must diffuse an entire wafer radius to volatilize the exposed film in the center. For a more detailed descriptioin of the E x B drift effect see below. Often the magnetic fields are generated by electromagnetic coils rather than with permanent magnetics. Equipment such as this usually bases the magnetic field strength on a model which uses a measurement of the current flow through the coil as input. However, permeability of chamber components and field divergence are often difficult, if not impossible, to accommodate

Slit Valve

Figure 6-9. E x B drift field created in MERIE tool.

6.3 Endpoint, Diagnostic and Control Techniques

in a model. Therefore, use of a simple Hall effect probe or magneto-strictive fiber optic sensor would provide valuable information relating to one of the most important machine parameters. Presently, neither of these technologies is in routine use. However, providing that access to the chamber is available, either measurement is simple to make and the information generated readily made available.

Thermal Metrology

All etchers make use of thermal energy in some way. The range of temperatures used in etching varies widely from cryogenically cooled to heated well above ambient temperature. In each case the specific temperature aids or inhibits certain etch characteristics. Information relating to the temperature of the wafer can be important for use in overall process control. For example, the degree of anisotropy in the etching of certain films in a simple C1, plasma can be varied if the wafer temperature is known. There are numerous ways to measure wafer temperature. Phosphorus tipped probes have been developed to contact the wafer backside and make spot temperature measurements. Single point pyrometry is widely used in deposition processes and could be applied to etch as well. Spot or single location measurements work well and are a proven technique, however, suffer from the same lack of uniformity information that laser interferometry does for endpoint. Recently, there has been work on the use of two-dimensional CCD detectors for real time temperature analysis (Turner, 1991b). Based on the emission of IR radiation from the wafer surface, these CCD devices present a real time image of the wafer surface. As the wafer is etched the emissivity of the

31 5

top film changes. This makes absolute temperature measurement all but impossible. However, the effect creates two unique capabilities: first, the establishment of a whole wafer endpoint monitor; second, a monitor of thermal gradients caused by non-uniform ion bombardment or cooling (either can result in etch rate gradients).

6.3.2.2 Process Related Measurements As mentioned above the second type of etch module metrology deals with measurements of the chemical or kinetic properties of the discharge. Present process tools do little to exploit this type of metrology even though it is the plasma which actually defines the process results. For example, although it has been known for some time that electrons drive the creation of etchant, nothing has been done to incorporate a device for the routine monitoring of electron density and velocities. This fact alone illustrates the ability of equipment suppliers to empirically develop etch modules which have met industry needs. However, the development cycle for new equipment and processes as well as a significant reduction in yield loss could be achieved with the application of a few simple plasma metrology tools. For years the argument against the need for plasma metrology has been based on the ability to generate a repeatable discharge if the machine setpoints were correct. And, for years the required range in repeatability of the discharge was sufficiently large to support the argument. However, the present requirements being placed on dry etching require tighter overall control of the plasma. For example, due to the rising cost of processed silicon it is no longer practical to discard edge die simply because the process cannot be made uniformly across the entire wafer surface. This sort of uniformity informa-

316

6 Etching Processes in Semiconductor Manufacturing

tion is often impossible to obtain without some type of dedicated plasma metrology device. Hence, the need for better understanding and control is creating a need for plasma metrology. The following sections detail the capabilities of several fundamental plasma metrology tools. Application of some, such as the RF metrology, in a production process control environment is very simple. Others may require special support which results in their use only as a troubleshooting or SPC type measurement. Residual Gas Anulj-six

The use of RGAs as endpoint monitors and for determining vacuum integrity has already been discussed. However, an RGA provides a unique capability which may be successfully exploited for plasma metrology. One of the simplest measurements to make with an RGA is a partial pressure analysis to determine the concentration of a certain plasma generated component. Partial pressure analysis of a neutral compound such as C1 or F can be done on a periodic basis to ensure optimized generation of etchant. In this application the desired signal is known (the mass of the etchant atom), and the signal to noise ratio should be sufficient for monitoring this primary plasma constituent. Implementation of an RGA can be done in various locations throughout the vacuum system. However, it is recommended that the quadrupole always be as close as possible to the actual discharge. Since only neutrals actually etch, information relating to the etchant concentration can be valuable in optimizing, controlling and troubleshooting dry etch processes.

Optical Emission Spectroscopy

Aside from its capabilities as an endpoint monitor, OES can provide insight into the chemical composition of the discharge. Even though the information gathered from an OES is basically a line integral, it can still be very useful in determining the presence and relative concentrations of compounds with too short a mean free path to make it into the RGA. The most common examples of short-lived constituents are film formers and ions, both essential to anisotropic etching. Although not all ions emit in the OES operating bandwidth, typically a sufficient number do to generate a process “fingerprint” which can serve as a “go-no-go” plasma sensor (Turner, 1991 c). Langmuir Probes

Langmuir probes are probably the bestknown and oldest plasma metrology tools, second only to the human eye. In implementation, they are very simple. One reviewer described a Langmuir probe as nothing more than a wire inserted into a plasma (Manos and Dylla, 1989a). There have been numerous reviews and articles published and these will not be reviewed here (Smits, 1960-62; Langmuir, 1929; Langmuir and Blodgett, 1923,1924; Langmuir and Mott-Smith, 1923, 1924, 1926). It has been shown for molecules such as those commonly found in plasma etching, that the dissociation which generates etchant is driven by the electron properties (Phelps and Van Brunt, 1988). The relationship between dissociation and etchant generation is driven by the dependency of electronic excitation cross sections on electron energy. By mounting the probe tip on a moveable platform with known spatial resolution, it is possible to generate radial profile maps of electron energy and density.

6.3 Endpoint, Diagnostic and Control Techniques

scree-

31 7

Since the electrons drive the etch chemistry, information relating to their properties is essential to a complete picture of the process and for improved control. Figure 6-10 contains a schematic representation of a Langmuir probe. Figure 6-11 shows the spatial variance in the probe I- I/ characteristic. In Fig. 6-11, position 1 is over the edge of a 150 mm wafer, position 2 is at 75 mm and position 3 at the center. When making probe measurements, care should be taken to insure a good ground plane is available. Also, in order to avoid excessive particle generation and possible vacuum failure, the use of welded bellows in the probe assembly should be avoided.

alumina sleewng

6.3.3 Control Techniques

-or

Figure 6-10. Schematic representation of a typical Langmuir probe circuit.

Original plasma etch tools had little or no sophisticated control. For the most part, machine settings were established and the operator manually turned the R F power on and off to start and then stop the

Field at 270 Degrees

0.06

4 I

0.04

0.03 0.02

0.01

Figure 6-11. Typical Langmuir probe I - V characteristic.

POS3

31 8

6 Etching Processes in Semiconductor Manufacturing

process. Soon the need for pressure control became apparent, to be followed by mass flow control, then temperature control. As mentioned above, R F power has always been a source-controlled parameter, rather than controlled at the load. For the most part, even with RF, the control strategy has been simple proportional-integral-derivative (PID) control. However, as the industry progresses into the 1990s, the need for improved machine control is becoming clear owing to the requirements of larger, more expensive, more complex wafers and in some cases, more complex etch tools. The following sections explore machine control from its present state to possible solutions for future needs.

6.3.3.1 Present Control Strategy Etch processes are presently controlled by a number of independent P I D loops. Each loop is based on some metrology (often misplaced) and a simple algorithm for modifying the drive signal to either a valve or other electromechanical device. A classic example of this form of control is seen in the pressure PID. The following sequence of events is typical of what would happen should a C1, M F C corrode and fail shut. A transducer generates a voltage proportional to the chamber pressure, which is sent to the controller as input for a decision. Suppose the pressure is determined to be low. Then the controller would in turn send a signal to the throttle valve instructing it to close, causing the pressure to rise. Without some sort of plasma or improved mass flow metrology the user would not know that there was a problem until the processed wafte was inspected and found to be scrap. Existing, independently operating PID loops create just such problems. This problem is compounded by the current lack of plasma metrology. Since there

is almost no information presently generated relating to the discharge characteristics, the plasma essentially runs open loop. By its very nature this condition induces run-to-run variability.

6.3.3.2 What is Needed? The most obvious answer to this question is improved metrology. From the point of its contribution to the success of an etch process, the availability of good information generated from the correct location in the system and relating to critical process parameters such as R F voltage, current, phase and the electron properties would have a huge impact. Figure 6-12 illustrates the difference in present and future control strategies. It should be pointed out that as yet the use of single wafer process tools has not been optimized due to the inability to detect an out of control situation during the processing of a lot of material. The proper addition of metrology fulfills the promise of single wafer tools. For some, this may seem like a large if not huge step. However, the payback for such efforts can be readily measured in terms of wafers saved or added and is found to be very fast. The payback of a $50 k investment in metrology equipment would be less than a single shift’s production of a typical 4 Mb DRAM product. Secondly, correlated information will make examples like the one above non-existent by allowing the pressure control PID to know that there is a problem with the MFC. Another significant improvement would come in the form of a true multivariate input/multivariate output optimization utility to replace existing RSM techniques. Since RSM is only a multivariate input,’ single response technique, it is difficult to apply to problems such as etching which has multiple responses (rate, uniformity, selectivity, anisotropy, and damage).

6.3 Endpoint, Diagnostic and Control Techniques

31 9

Present Plasma Process Control [LEiF]

[L+G-]

R+ ITCH ESIJLTS.

LOOP

m a

OPm LOOP

PLPSMP.

SBM Approach Completes the Promise of Single Wafer Processors

COPITROUB,

Figure 6-12. Present and future control strategies.

6.3.3.3 Possible Solutions Along with the obvious solution of adding metrology, improvements in control strategies must also be made. A simple extension of present statistical process control (SPC) techniques to use data in real time could make a significant improvement in the ability to detect and correct for out of control situations. This simple solution could also eliminate mis-processing the wafer in the example of the failed MFC described above. A real time SPC routine

could be used with either machine (power, pressure, flow,. . .), or plasma information. Embedded control could also consist of empirical models generated with multivariate optimization routines. These models should be capable of predicting correct machine settings for the generation of specific plasma characteristics necessary for various product wafers. It is most likely that the final advanced control package will be a hybrid of PID, SPC and model based. The SPC package could detect the out of control condition and pass control

320

6 Etching Processes in Semiconductor Manufacturing

to the model. The model package could then determine a proper response and relay these new machine settings to the PID controllers for each subassembly. At the present time efforts to define the next generation control system are underway at various university and manufacturing locations. It is difficult to predict the outcome of current efforts; however, it can be anticipated that over the next decade etch tools will undergo drastic changes in order to meet product design specifications.

6.4 Process Discussion: General Considerations 6.4.1 Isolation

Etch processes for different isolation techniques are, as expected, operated with different process requirements. The SWAMI (sidewall mask isolation) process, for example, requires an anisotropic nitride and oxide etch, followed by a silicon etch-todepth with a smooth etch front and profile control at the bottom of the silicon feature (similar to trench etch requirements). The SILO (sealed interface local oxidation) isolation requires a more complex structure and a self-aligned etch of nitride-pad oxide-thin nitride structure followed by a silicon etch to recess the field oxide. The issue of stress control of the silicon after field oxidation requires a tapered, round-bottomed silicon etch. Some of these problems and trade-offs involved in the etch process are discussed by Parrillo (1986) and Brassington et al. (1988). Trench isolation can be described in the context of shallow or deep trench isolation. In this context, shallow trench isolation is a LOCOS (local oxidation of silicon) replacement that gives more planar isolation. Shallow trenches ( < 1 pm) do not sig-

nificantly improve isolation performance and latch up resistance but can be considered a more planar LOCOS replacement. The processing cost is in the trench etch (usually a photoresist mask/nitride/pad ox stack is used), the mask removal, the CVD oxide deposition, and the planarization etchback of this oxide. This etchback may involve multiple resist layerings to achieve a suitably planar surface. Deep trench isolation has the advantages of potentially eliminating latchup and using less real estate than other techniques. The fabrication complexity of this structure is the reason why it is not in common use at the 4 M b level. Here, “deep” means deeper than 3--4 pm: the trench etch step itself takes some minutes in the etcher and requires multiple etch chambers to meet factory throughput demands. The etch requirements are severe: The sidewall and bottom profiles must be controlled and the process must be well centered in a wide process window since only destructive, time consuming SEM techniques can be used to inspect these etch results. The sidewalls must remain undamaged and a high quality thermal oxide must be capable of being grown on them. (A sacrificial oxide may be used first.) Typically, deep trenches are etched with chlorine or fluorinebromine based chemistry: a hard mask is required for this etch. Tachi and Okudaira (1986) have measured the silicon reaction rates with F’, Cl’, and Br’ and have shown that of the three, Br+ etching of silicon has the strongest dependence on ion energy. Table 6-5 summarizes the range of geometries that are commonly associated with different etch chemistries. The use of bromine-containing gases in this etch process has a number of advantages, most notably higher selectivity to oxide masks and increased capability to etch deep, narrow feature. Figure 6-13 shows a 21 : 1 aspect

6.4 Process Discussion: General Considerations

32 1

Fdble 6-5. Trench etch chemistries for different geometries.

Chemistry Mask Etch depth (1 pm mask) Etch profile

Fluorinated

Chlorinated

Brominated

photoresist 3 Pm depends on mask profile

oxide 10-15 pm always vertical

oxide/nitride >20 pm always vertical

ratio trench etched in Si using brominecontaining etch chemistry. The high selectivity to oxide obtained with this chemistry also means that care has to be taken to avoid black silicon formation. After the trench is etched, it must be filled, the fill planarized or at least etched back, and the isolation structure capped with (usually) a LOCOS oxidation. The fill process usually uses polysilicon which is easily oxidized to cap the trench (Silvestri, 1986) and can fill the trenches without voiding. Details of trench etch processing are found in literature: the ion energy dis-

Figure 6-13. Trench etched with bromine chemistry: the 0.2 x 4.2 pm trench demonstrated the usefulness of bromine chemistry for etching high-aspect-ratio trenches.

tribution and ion scattering effects on sidewall profiles are discussed by Sat0 and Arita (1984). Mechanisms and sidewall analyses are presented by Hirobe and Nojiri (1987) and Oehrlein et al. (1990).

6.4.2 Gate Definition Gate definition etch tolerances now require operation to extremely tight specifications of control, rate, uniformity and particle control as well as control of gate oxide integrity and sidewall profile. Furthermore, the gate electrode now consists of a doped polysilicon layer that is frequently covered with a refractory metal silicide to decrease the resistance of the electrode. The common use of an LDD (lightly doped drain) structure to control hot carrier effects on small ( <2 pm) gates constrains the amount of taper that can exist on any poly line: this is especially important for lines in dense areas compared to lines at the end of an array. Finally, oxide selectivity values greater than 30 : 1 are often required because of the 100% overetches needed for circuits that have poly lines crossing the steep topography that comes from some isolation techniques. An example of such a structure can be seen in Fig. 6-14. Here, the polysilicon line crosses thick, vertical topography: the stringers must be removed with a long, anisotropic, highly selective overetch. Requirements for high resolution pattern transfer at the poly gate level has resulted in investigation of low pressure etch-

322

6 Etching Processes

in Semiconductor Manufacturing

3 (---ILICON I SOLATION

Figure 6-14. Polysilicon line over steep geometry.

ing at low temperatures. The general idea of low temperature operation is that the neutral reactions which cause undercut are suppressed and also that slow product desorption from the sidewalls will protect them from any undercut. The ion bombarded surfaces will, of course, still be etched. The next generations of poly etchers may have hardware that is capable of operating at low wafer temperatures. Work below 0°C with C1, in a 13.56 MHz magnetron showed that the low temperature assisted SiCl, etch product deposition on the exposed SiO, surface and protected it from the etch: this resulted in a temperature-sensitive selectivity between doped poly and SiO, (Sekine et al., 1988). Similar work by Tsujimoto et al. (1988) supports their claim that the low temperatures used inhibit radical reactions and help keep reaction products from leaving the sidewalls (preventing undercut). They worked between - 150 'C and 30 "C and etched single crystal silicon, polysilicon, WSi, and tungsten. Nakamura et al. (1988) used temperatures in the 0 to 90°C range to control taper angles of polysilicon using HBr in an RIE tool.

In summary, polysilicon etch requirements can be discussed in terms of (i) what can be measured with a SEM (sidewall profile, residues), (ii) what can be measured electrically (I,,, distribution, gate oxide integrity) and (iii) in terms of the post-etch processing results required to prepare the wafer for the LDD implant step. The high selectivity-to-oxide requirement has led many processes into operating conditions that result in an oxide-like deposit on the resist sidewalls and the poly sidewalls. This deposit must be completely removed prior to implant and spacer oxide deposition but the clean step must preserve the thin gate oxide that the etch step worked so hard to protect.

6.4.3 Silicides The use of silicides to reduce the RC time delay in polysilicon interconnects is generally accepted as the technology of choice for 4 Mb production. The typical silicides will decrease sheet resistances from about 20 R/O to about 5 R/O. Early discussion of silicide etching focused on effects of film stoichiometry and

6 . 4 Process Discussion: General Considerations

phosphorous levels (Coe and Rogers, 3 982). Early reviews of silicide properties (Murarka, 1980, 1983, 1995; Sinha et al., 1980; Geipel et al., 1980; Mohammadi, 1981) discuss why silicides are preferred over refractory metals and present processing considerations for most of the specific silicides and salicides that can be used. d’Heurle and Gas (1986) provide a detailed review of the kinetics of silicide formation reactions. General requirements for silicide stack etching are similar to the etching of polysilicon gates: i.e., the ability to etch the silicide with high selectivity to oxide (rarely obtained), to etch with vertical sidewalls, to etch with high selectivity to polysilicon (possibly), and that the subsequent poly etch step does not undercut, notch, or degrade the silicide sidewall in any way. A typical result is shown in Fig. 6-15 which shows a tantalum silicide-polysilicon stack that crosses a 3000A vertical step: the overetch has removed the stringer without affecting the sidewall. This issue of etching the silicide with selectivity to oxide is an important limitation of many otherwise successful silicide etch processes. The low vapor pressure of the chlorides of most refractory metals requires that fluorine be used in the etch step. The fluorine chemis-

323

try in general etches the polysilicon that is under the silicon at a rate similar to the silicide etch rate. Thus, it is difficult to overetch the silicide by enough to clear the silicide stringers without exposing some gate oxide. Damage issues are quantified (typically) with test structures which are supposed to be more sensitive than actual devices to damage. The reason for this is that a very small yield loss can amount to substantial profit loss over the lifetime of an etch tool and that this small yield loss (less than 1%) may be impossible to measure on real product. Consequently, a more sensitive test vehicle is used. For gate etch, the two most common test vehicles are large capacitors (IO mmz area) over gate oxide and antenna structures with antenna ratios of 104: 1. Typical requirement for these structures is that no gate rupture can be made to occur under etch conditions (or under more “aggressive” etch conditions) than those needed for production.

6.4.4 Contact Etching Contact and via etching consist of etching high aspect ratio openings in dielectric films for the purpose of interconnecting layers of conducting materials. Typically, contact dimensions are smaller than the

LICoN ISOLATION

Figure 6-15. Tantalum silicide etch: 3000 A vertical step under silicide feature.

324

6 Etching Processes in Semiconductor Manufacturing

subsequent vias and contact etch steps stop on sourceldrain areas as well as poly lines. Thus, the dominant issues in contact etching are: -

electrical: control of crystal or gate damage and contact resistance selectivity to doped Si (including selectivity variation with feature size) profile control rate and uniformity (including rate variation with feature size) selectivity to mask particle contamination control

The drivers for hardware choice and for process development are slightly different in this etch process. Damage considerations tend to dominate the choice of the tool type whereas the process development focuses on the selectivity and profile results. For all applications except salicides (here the silicide is formed on the poly and source drain areas prior to oxide deposition), the etch stop is on silicon. Barrier metals are deposited during metal 1 deposition. Damage includes effects on gate oxide integrity, lattice damage, junction degradation, and contact resistance problems in subsequent processing. Gate oxide integrity can also be affected by electric fields which may occur across the gate dielectric during the etch steps. These fields can inject charge into the gate and reduce gate lifetime (at best) or actually cause gate rupture (at worst). Trap formation from this charge injection can leave gates with fixed charge that can shift threshold voltages. One might be surprised that gate damage is an issue in contact etching. The reason has to do with the physically dominated etch mechanism for SiO, etching. Throughput requirements result in high power density operation: the higher electric fields and ion currents that

come with high power operation make gate oxide integrity a potential problem. Typically, these electrostatic damage processes can be made unimportant by reducing the process power: unfortunately, this results in an unacceptably low throughput for the etch tool. The key is to find a tool as well as etch conditions which can give acceptable throughputs and acceptable damage control for the devices being manufactured. The silicon surface of the exposed contact has been characterized in detail by Oehrlein et al. (1985). They describe the etched surface in this way (see Fig. 6-16): the surface contains a deposited fluorocarbon polymeric film (a result of the selective etch), beneath which is an interfacial layer that is oxygen-rich and carbon-free. This is the transition between the polymer and a heavily damaged Si layer. Beneath the damaged layer is a hydrogen-rich crystalline Si layer which is the last damaged region. This structure can be used to explain the etch performance of most oxide etch processes as well as the clean steps required to obtain good contact performance after the contact etch. Mu et al. (1986) have studied structural damage on silicon with CF, and CFJH, RIE. They identified the increased structural damage on Si when hydrogen is present and discussed annealing procedures to remove it. Published measurements of dopant deactivation caused by RIE contact etching were consistent with the model of hydrogen passivation of the dopants. Wu et al. (1988) demonstrated that, for p'/n junctions, the leakage current increased strongly with silicon etch depth whereas for n'/p junctions, etching to 400 8, of the junction did not affect the leakage current. They used 1600-1800 8, junctions. Liu et al. (1988) studied mechanisms of junction leakage.

325

6.4 Process Discussion: General Considerations

Surface of contact exposed to etch

-50

-20A

30 A

Depth into silicon

300 A

Figure 6-16. Schematic view of damaged regions near Si surface exposed to dry etch process.

Perfect crystal Si

Table 6-6. Contact resistance B: 30 keV.

LOSS

(A)

0 50 100 200 Selective oxide process

- Si

clean up SIMS results (atoms/cm2). Dose initial

As 1.4 x 1014

(3-4)

1.7 x ioi4

(3-5) x i o i 4 11:l

The use of a cleanup step to remove the fluorocarbon surface film and the damaged Si layer has been studied by Hills et al. (1989). They etched contacts to doped silicon junctions and used an NF, low power cleanup step. Table 6-6 shows results of SIMS measurements made on the Si contacts after different exposures to the cleanup step removed different amounts of silicon. The SIMS analysis of the total dopant left

x 1014

1-1.5 1015/cm2;As: 180 keV;

3 x 1014 3 x 1014 3 x 1014

7 x 1014 8 1014 5 x 1014 2 1014

20:l

in the junctions showed that removal of up to 1008, of Si did not change the total arsenic or boron in the junctions. This evidence supports the use of cleanup steps to restore good contact performance after high selectivity contact etching. The relatively high aspect ratios encountered when etching contacts through planarized interlayer dielectric (ILD) layers constrain the allowable variation of etch

326

6 Etching Processes in Semiconductor Manufacturing

Silicon

Figure 6-17. Microloading efTect: the etch rate of the 0.5 pn feature is 5 % lower than that of a large feature.

1.501.cm

rate with feature size. This microloading effect (sometimes incorrectly called “proximity effect”) is illustrated in Fig. 6-17. In this figure, the scanning electron microscope (SEM) photo shows a 0.6 pm as well as a larger feature: the etch rate for the smaller feature is 95% of the large feature’s etch rate. Most dielectric etch processes show a decrease in the etch rate for feature sizes below 0.8 to 1 pm: this results in required overetches of larger sized features and can mean a lack of process control if feature sizes vary because of variations in the photolithographic process. True global planarization using C M P (Chemical Mechanical Polishing) of thick BPSG films has, for example, results in the need to etch 3 pm deep contacts that are 1 pm in diameter. The excessive oxide thickness can be required to planarize some topographies such as stacked capacitor structures. One final process issue with contact etching that can affect contact behavior is the flatness of the etch front as the underlying contact material is exposed. Ideally, a perfectly flat etch front should occur (indeed, this is desirable on all etch processes which stop on a different film). However, the actual etch front may be rounded (faster etch rate in the center) or “trenched”

(faster etch rate at the edge). Figure 6-18 shows such a trenched feature: the reason for this is an excess of physical sputtering and reflection of ions from the feature sidewalls which generate the “trenching” characteristic seen in the figure. The requirement for a flat etch profile guarantees that the fraction overetch is constant across the features as well as that the etch is uniform across the wafer.

6.4.5 Planarization Etch Steps The purposes of planarization of dielectrics are two: (i) to smooth surface topography for the metal deposition and metal etching steps, and (ii) to eliminate or reduce the magnitude of the variations in topography in order to ease the depth of focus requirements for photolithographic tools. The idea is simple but a number of details make planarization a difficult production process. Techniques that planarize surfaces can effect global or local planarization. A globally planarized surface is flat over all geometries whereas a locally planarized surface has different degrees of smoothness which depend on the topography being planarized. The cost of planarization is the

6.4 Process Discussion: General Considerations

327

Reslsl mask

Substrate "Trenching" \

Figure 6-18. "Trenching" occurs when the etch process has excess physical sputter component.

IDEALLY P L A N A R

OVERETCHED CONTACT

additional process complexity associated with it and, at the die level, the resultant variation in via depth between the top of the planar surface and the bottom of the non-planarized surface. The deep vias or contacts must be etched to completion: this makes endpoint more difficult to determine and means that the shallower vias or contacts receive very long overetches. Finally, fill problems will occur on structures that have both deep and relatively shallow holes on the same die or, for that matter, on the same cell. An example of this problem on a planarized contact etch is shown in Fig. 6-19: here is clear that the contact to the polysilicon line will be overetched if the contact to source/drain is opened.

Figure 6-19. The planarized ILD film requires that the contact be overetched substantially.

A relatively simply planarization technique is to use a spin-on sacrificial layer such as photoresist or SOG (spin on glass) to achieve a smooth surface and to then etch it back under conditions that give the same etch rate for the spin on layer and the underlying dielectric. One example is to etch back SOG and plasma oxide to planarize a surface: here the SOG is left in the gaps left by the deposited oxide. Resist spin etchback techniques are no longer popular because of the difficulty of matching the etch rates of the resist and the glass in the small features that are being planarized. Other planarization techniques use alternating deposit-sputter etch-deposit sequences to integrate the planarization process with the deposition. The sputter etch

328

6 Etching Processes in Semiconductor Manufacturing

1 Oxide Deposition

Ar Sputter Etch

Figure 6-20. Planarization with integrated dep-etch-dep processing.

3 Oxide Deposition

step achieves local planarization by faceting the dielectric at the edges of features: this decreases the gap filling problem for the next deposition step and results in a more planar dielectric that is void-free. Such an approach has been described in the literature and is commonly used in fabrication. Figure 6-20 shows such a “dep-etch” sequence: here the faceting which is characteristic of physically dominated etch (sputter) processes is utilized to taper the edges of deposited oxide and another CVD deposition step is used to provide both improved gap filling and planarization of the oxide film. The use of TEOS oxide films has increased the ability of dep-etch sequence to planarize small geometries easily (see Perchard et al., 1990). 6.4.6 Via Etching Most 4 Mb DRAMS currently in production use a single metal structure so no via etch is used. The discussion below is relevant to pad mask opening but is included because via etching is used in all multi technologies. Interconnect etching of the inter metal dielectric (IMD) layer is, in most respects, a simpler version of the contact (ILD) etch. The reasons for this are that the vias are

usually larger sized and that the selectivity to the underlayer (a metal or second poly) is less important than it is at the contact opening level. The major technical problems are not simple, however, because the subsequent process requirements depend on how the via etch is accomplished. Sputtering of the metal that is exposed by the via etch can strongly affect the cleaning steps required prior to subsequent metal deposition. The sputtering occurs during the via overetch and the sputtered material is deposited on the via sidewalls and on the resist mask sidewalls, especially if they are vertical. After resist ashing, a fence-like residue which defines where the resist sidewalls had been is the characteristic of excessive sputtering. Since long overetches are always required after the dielectric has been planarized, this sputtering is always a problem. Note that the sputtering threshold for aluminum is below 15 eV: since all RIE etch plasmas have plasma potentials higher than this value, some sputtering will always occur. The increase in sputter efficiency that accompanies increases in ion energy (see Vossen and Kern, 1978) results in excess sputtering in tools which etch with large ion energies. Successful operation of via etching requires that the sputtered metal not be redeposited on

6.4 Process Discussion: General Considerations

the resist sidewalls to the extent that its removal requires extra process steps. The etch requirements for via etch often include the need for tapered etching: the taper is meant to ease metal filling requirements. Typically, this is done with resist etchback or a wet-dry sequence. The resist etchback technique is not useful for most VLSI applications because a tapered resist profile is required. A tapered profile is difficult to generate with flow steps, and isotropic resist etch steps during the etch are cumbersome. An all-dry method has been reported for contact etching (Jillie et al., 1987) but this process uses resist erosion with the resultant variation in contact size with overetch. A wet-dry technique is often used: its chief problem in production is to be sure that 100% of the vias wet in the (first) wet etch step. Perfect wetting is not easy to obtain if via dimensions are below about 1.0 pm. 6.4.7 Metal Etching

Metal etching, until recently, commonly meant aluminum alloy etching using a photoresist mask and stopping on an oxide. The use of barrier metals and anti-reflection coatings has changed this working definition and has made the metal etch requirements more exacting because the pattern transfer must now occur through a stack of films. New metallurgies also generate new processing needs. For example, tungsten plus filling techniques can require a blanket etchback with uniformity and microloading requirements similar to poly etchback after trench fill. Patterned tungsten etching is also required if this material is used for the first layer conductor. The technical obstacles to achieving manufacturing-level control of aluminum alloy etch processes have been solved slowly and, often, incompletely. Briefly, the gas

329

chemistries have been limited to BCl, or SiC1, with chlorine and (often) fluorocarbons added to increase rate and sidewall profile control. RIE is required to remove residues, especially copper, and attempts to control corrosion with all dry processes have met with varying levels of success. The use of inorganic gas etch chemistries (instead of chlorocarbons like CCl, - see Hess and Bruce, 1984) and low pressure operation have also helped the particle control performance of metal etch tools. Bruce and Malafsky (1983) showed that chlorine etches aluminum spontaneously. Also, Smith and Bruce (1982) showed that the aluminum etch rate was not dependent on the ion bombardment energy. They plasma-etched in C1, gas at 500 mtorr pressure and also suggested that the primary etch product is AlCl, (or its dimer). The fact that chlorine can spontaneously etch aluminum once the surface oxide was removed led workers to focus on sidewall passivation and residue removal processes that were driven by the plasma. Finally, etching TiW, TiN and other barrier and anti-reflection coating layers was integrated into etch processing of metal lines. Typical process problems included notching at the anti-reflection coating-metal interface and a taper (or “foot”) in the barrier layer. The more recent availability of integrated systems which can combine the etch and strip processes has driven the development work to provide corrosion control and dry strippable masks. Corrosion prevention is still the dominant issue in metal etching. The other current etching issues in 4 MB production are particle performance, better rate uniformity, better photoresist selectivity, and profiles which are independent of local loading or spacing effects. Historically, the use of loadlocked systems gave control over the breakthrough step (Winkler et al., 1981; Donohoe, 1981):

330

6 Etching Processes in Semiconductor Manufacturing

this non-reproducible process initiation was one of the first processing obstacles to be overcome. The non-loadlocked batch reactor also eliminated the problem by using BCl, to get moisture. Early papers described metal etching using different etchants: CCl,. O,, BCl,, BC1,-O2, Cl,, SiCl,, CHCl, represent most of those used (see Coburn, 1982). These were mixed with C1, to increase etch rate and also mixed with various fluorocarbons to prevent undercut and help eliminate corrosion after etch. Etch conditions varied widely from 50 mtorr RIE tools (which worked well with Cu-containing films) to higher pressures, up to 1 torr, which were less useful in production applications of films with more than 0.5% Cu. Since aluminum etching in chlorine is spontaneous (Bruce and Malafsky, 1983), the role of the plasma is to control anisotropy, provide controllable initiation of the etch, and to assist in the removal of other elements from the etching film. Silicon and copper are the primary impurities and the copper removal causes most of the process optimization problems. Since copper must be removed with a physical process (copper chlorides are not very volatile at the temperatures achieved in etching, see the discussion by Broydo, 1983) the balance becomes a trade-off between physical and chemical etching, or, at the wafer level, between resist selectivity and residue control. Compounding this interaction is the need to continuously remove some resist to contribute to the sidewall formation: it is often observed that undercut occurs if the power density in the discharge is decreased, to increase resist selectivity (the same result is commonly seen if a hard mask is used: etching with an oxide hardmask will result in isotropic profiles under conditions which give good anisotropy with a resist mask).

Typically, process optimization occurs by increasing power (or decreasing pressure) until residue levels are acceptable, then varying chemistry (for example, the ratio of BCl, to C1, to CF, or N,) to finetune the results on the wafer with respect to profile control. Most production processes that etch Cu containing films operate under conditions that give an overall resist selectivity (resist loss/film thickness for the etch process) of 2 to 2.5 on large features: the true resist loss is larger because of faceting at the feature edge. The vertical distribution of copper (and other impurities) in the film can have a profound effect on how easy it is to etch without residues (see Hara et al., 1986, for a discussion of the distribution of impurities). Attempts to improve resist selectivity have focused on changing gas chemistry: SiC1, has been used to “cap” the resist and improve the selectivity. The cost of this improvement is a resist which is impossible to dry-strip and difficult to wet-strip in common organic acids. The addition of bromine-containing gases has shown dramatic increases in resist selectivity, including decreased faceting of feature edges (Nakamura et al., 1981; Levy and Donohoe, 1990; Krough, 1988). Figure 6-21 (Sawai et al., 1989) illustrates the effect of this process chemistry (and magnetic field) on the selectivity between photoresist and Al-Si-0.5% Cu: the bromine chemistry is clearly capable of high resist selectivity. One study describing BBr, addition to a hexode also reports good process results (Bell et al., 1988). Most metal etch production tools in 4 Mb lines use RIE or Microwave plasmas to perform the etch. Integrated etch-strip had not been made available by vendors until recently (1989) and is not yet in widespread use. It is clearly desired by the manufacturing community. The drive for integrated strip is caused by the need to

6.5 Etch Processing for 4 Mb DRAM

100

150

Magnetic Field (Gauss)

Figure 6-21. Metal etch resist selectivity for bromine and chlorine chemistries (after Sawai et al., 1989).

control post-etch corrosion of the metal lines: in general the tendency for corrosion increases as: 1) barriers such as TiW are used, 2) copper is added to the aluminum in increasing concentrations, 3) the line/ space pitch is decreased. It is generally believed that corrosion is caused by residual chlorine in the metal sidewalls: the lack of a protective oxide is certainly another issue to be dealt with in corrosion control [see Lee et al. (1981) for a detailed discussion of post-etch oxidation techniques and their effect on corrosion].

6.5 Etch Processing for 4 Mb DRAM This section describes the details of each important etch step used in IC processing. To give the discussion some structure, a process flowsheet for a 4 M b DRAM is used. Naturally, every manufacturer of

331

such devices uses different process steps and many of them are confidential. The flowsheet shown below is released by SEMATECH: the discussion will depart from this specific flow and generalize when appropriate. The equipment descriptions refer to the actual equipment used in the fab to run the process. The process flow is shown in Table 6-7. It describes a dual-well triple-polysilicon single-metal process using trench capacitors. The 164 process steps consist of 17 dry etch steps, 23 resist strip steps, and 21 wet clean/wet etch steps. We will focus on the etch processes by describing the pertinent processing issues for each as we go through the process.

6.5.1 Wafer Preparation Chemical cleaning is required to remove laser scribe residues from the wafers. The cleaning is performed in a wet sink followed by a standard spin rinseldry.

6.5.2 N-Well The anisotropic nitride etch which defines the N-well implant mask must stop on the 500 A pad oxide grown in step 2. In this line, a single wafer plasma etch tool is used for this step, employing a high pressure fluorine chemistry process. Endpoint is determined by emission. The CD (critical dimension) control is virtually perfect: this is simple to obtain when etching a 5008, film with an anisotropic etch process. The photoresist strip requires a plasma process since the implanted resist is difficult to wet strip. A downstream asher is used in the first step of the strip: this is followed by an H2S0,-H,0, sink clean and a rinse/dry step. Inspection (step 10) looks for problems in lithography as well as nitride residues.

332

6 Etching Processes in Semiconductor Manufacturing

Table 6-7. Sample process flow for 4 Mb DRAM

Table 6-7. Continued

Step

Stcp

Mask

Process equipment

Wafer preparation: 1 starting material p-type non-epi (100) 150 mm 2- I O fl cm grow initial oxide 500 8, nitride deposition 500 8, 4 laser scribe 5 chemical cleaning N-Well: 6 1 7 8 9 10

N-well mask N-well etch, nitride only N-well implant (phosphorus) [10(12) 150keVl photoresist strip inspection

P-well field implant: 11 megasonic clean 12 well oxidation 4000 8, 13 wet H F etch, pre-nitride strip 14 nitride strip 15 P-well implant (boron) [10(14)50 keV] 16 oxide removal (wet) 17 sulfuric clean N- and P-well implant drive 18 and grow buffer oxide 400 8, Is0 mask:

19 20 21 22 23 24

poly deposition loo0 8, nitride deposition 2500 8, isolation mask is0 mask etch (etch nitride. stop on poly) photoresist strip final inspection and CD

Connector mask: 25 3 P-well field implant mask 26 P-well field implant (boron) [10(13) 30 keV] 27 photoresist strip final inspection 28 29 sulfuric cleaning 30 field oxidation 4000 8, 31 oxide strip (wet) 32 nitride strip oxide strip (wet) 33 34 Koi oxidation 400 8, 35 oxide strip (wet) 36 screen oxidation 200 8,

37 38 39 40 41

Mask

Process equipment

connector mask connector mask implant (As) photoresist removal final check field implant drive and grow oxide 400 %,

Trench capacitor 42 nitride deposition 1000 %, 43 oxide deposition 4000 8, 44 5 trench capacitor mask 45 trench capacitor mask etch (etch oxide and nitride) 46 photoresist strip 37 ctch silicon trench 48 rounding wet etch silicon in trench 49 deposit arsenic glass 50 drive As 100cC 1 h 51 strip As glass (wet) 52 grow sacrificial “rounding oxide” 500 53 H F dip 54 strip nitride 55 strip sacrificial oxide (wet) 56 megasonic cleaning 51 trench oxidation 200 8, thin nitride deposition 200 8, 58 59 oxidation 50 8, 60 in situ poly 1 depo/dope 61 photoresist coat 62 backside etch 63 photoresist removal Cap plate mask: 64 6 trench cap plate mask 65 trench cap plate mask etch 66 photoresist strip 67 final inspect and CD check N-well threshold adjust: 68 grow thermal oxide 500 8, 69 7 Vt N-well mask Vt N-well implant (boron) 70 71 photoresist removal 72 final check P-well threshold adjust 13 blanket Vt p-well implant (boron) 14 megasonic cleaning 75 annealing

6.5 Etch Processing for 4 Mb DRAM

Table 6-7. Continued

Step

Mask

Process equipment

Inter poly oxide mask: 76 8 inter poly oxide mask 77 oxide etch 78 photoresist removal 79 final check and C D Gate mask: 80 81 82 83 83 85 86 87 9 88 89 90

megasonic cleaning gate oxide grow 200 8, poly 2 deposition 3500 8, photoresist coat backside etch photoresist removal poly 2 dope (POCI,) poly 2 mask poly 2 mask etch photoresist removal final check and C D

N-channel S/D 1: 91 light poly oxidation 10 N-channel S/D mask 1 92 93 N-implant (phosphorus) [low lO(13) low energy] 94 photoresist removal 95 final check P-channel S/D 1: 96 11 P-channel S/D mask 1 97 P-implant (boron) [10(15) low energy] 98 photoresist removal 99 final check N-channel S/D 2: 3 00 megasonic cleaning 101 L D D spacer oxide deposition 2500 8, 102 densification 103 LDD spacer oxide etch 104 reoxidation 100 8, 105 12 N-channel S/D mask N' implant (arsenic) 106 [10(15) low energy] 107 photoresist removal 108 final check P-channel S/D 2: 109 13 P-channel S/D mask 2 110 P + implant (BF2) 111 photoresist removal

Mask

333

Process equipment

Contact mask 1: final check 112 S/D activation drive and oxidation 113 500 8, undoped CVD oxide depo 114 BPSG ILD deposition 115 densification and reflow 116 contact mask 1 117 14 contact mask 1 etch 118 photoresist removal 119 final check and C D 120

Poly 3 mask: 121 122 123 124 125 126 15 127 128 129 130 131 132

sulfuric cleaning poly 3 deposition poly 3 implant [10(14)] implant anneal deposit MoSi, poly 3 mask etch MoSi, lines photoresist removal final check and C D photoresist coating backside etch photoresist removal

Contact mask 2: oxidize poly in wet O 21500 8, SiO, 133 134 undoped VCD oxide deposition 135 BPSG via deposition (1) 136 PSG deposition 137 reflow 138 etch back 139 16 contact mask2 contact mask 2 etch (wetidry) 140 141 photoresist removal 142 final check and C D Metal 1 mask: 143 144 145 146 147

Pad mask: 148 149 150

metal 1 deposition (TiN/AI-Cu OS%/TiN) Metal 1 mask metal 1 mask etch photoresist removal final check and C D

LTO deposition silicon nitride deposition alloy

334

6 Etching Processes in Semiconductor Manufacturing

Table 6-7. Continued

Stcp

Mask

Process cquipment

I51 152

pad mask pad mask etch photoresist removal final check

I53 154 Polyimide mask: 155 19 156 157 158 159

polyimide deposition polyimide mask polyimide mask etch photoresist removal final check

E test: 160 161 162 163 164

parametric test E test 1 and redundancy repair photoresist coating backside grinding photoresist removal

6.5.3 P-Well Field Implant This implant defines the N-channel regions of the circuit. The first etch step in this section is an H F dip to remove oxide from the nitride surface and prepare the wafers for nitride strip in hot phosphoric acid. This nitride strip step is highly selective to oxide because the oxide thickness controls the C D variation of the P-well implant boundaries.

6.5.4 Is0 Mask This module defines the isolation areas on the wafer. Poly buffered LOCOS is used here to decrease the size of the bird’s beak. In this technology, the pad oxide-nitride stack is replaced with a pad oxide-polynitride stack. The use of poly buffered LOCOS generates the advantage of a smaller bird’s beak since a thinner pad oxide is used: see Ghezzo et al. (1989) for discussion of poly pad use for LOCOS improvement.

The etch tool used for is0 mask definition must perform an anisotropic etch that stops on the thin (10008,) poly. An RIE etch tool is used to etch the nitride and stop on poly. The key control issues with this etch are to control the uniformity of the poly loss and the C D control. Variations in the poly thickness will result in a variation in the effect of the poly to decrease the bird’s beak size.

6.5.5 Connector Mask This section of the process includes the P-well field implant, the field oxidation, the strip of the isolation mask that defined the field areas and the connector mask etch. This is a relatively simple etch through 200 8, of oxide. All of the steps in this section are performed with wet chemistry in sinks except for resist ashing in the downstream microwave etcher. 6.5.6 Trench Capacitor

Trench storage capacitors are formed in this step. The etch sequence is to open a hard mask for the trench etch, perform the trench etch itself, a wet rounding step and some dips to further improve the trench profile and clean up the silicon surface. The hard mask open step is done in a single wafer plasma etcher: this step is similar to a contact etch except that high resist selectivity is not desired. Indeed, the possibility of black silicon formation requires that the exposed silicon be free of both residual oxide and of the polymer deposits typical of high selectivity oxide etching. This etch through 4000 8, of CVD oxide and 1000 8, of nitride is not considered particularly demanding. Total etched area is typically larger than a few percent so optical emission can be routinely used to monitor endpoint. This is a higher etch rate process

6.5 Etch Processing for 4 Mb DRAM

(3000 Ajmin) and is operated at 15 : 1 selectivity to silicon. Resist selectivity is not an issue and runs in the 3 : l range. The resist strip is done in a downstream microwave stripper followed by a wet cleanup. This step (a downstream oxygen plasma that uses a small amount of nitrogen to increase strip rate) grows a thin oxide on the silicon surface. The wet clean removes residual contamination (for example, sodium from the resist) that remains after the resist ash step. Finally, the trench etch is performed using a MERIE single wafer tool. This etch uses a bromine-fluorine gas mixture (see Table 6-5) and requires a hard mask. Typical etch rates are 5000 8,/min with mask selectivity of 15 : 1, uniformity of trench depth is a few percent. Silicon damage (which could result in poor quality oxide in the capacitor) is minimized by the magnetic field enhanced RIE operation at relatively low ion energies. The sidewall passivation material deposited on the sidewall is a non-stoichiometric oxide (SiO, with x < 2) (Vasquez et al., 1989). The control issues with this etch step are black silicon formation (the breakthrough step prevents this from forming), etch depth control (surface profilometry of large features is used to monitor this) and trench profile control (monitored indirectly by measuring mask selectivity and directly with destructive and time consuming SEM evaluation). Typically, a plasma clean after every wafer is used to control particle contamination. The wet steps following the trench formation are aimed at rounding the trench bottom and removing any damaged layer from the sidewalls. They also round the top of the trench somewhat: this rounding improves the electrical integrity of the oxide/ nitride dielectric at the edge of the trench. A wet etch is used first to round the trench.

335

The sidewall is then As-doped, the As glass is stripped with HF and a final sacrificial oxide grown and stripped to prepare the silicon for final gate quality oxide growth. The formation of a gate oxide quality film of SiO, on the trench sidewalls is complicated by the need to remove the nitride from the silicon surface. The sacrificial oxide protects the silicon sidewalls from the downstream dry nitride strip: the strip uses a chemical dry etch (relatively damageand contamination-free) instead of a hot phosphoric acid wet nitride strip or a RIE etch which would bombard the trench bottom. The etch chemistry is fluorine-based and good selectivity to oxide is maintained by operating the downstream etcher with virtually zero ion energy at the wafer surface. This etch is a reasonably high throughput step since the nitride is only 10008, thick. The final etch step in this sequence is the removal of the doped poly (used to fill the trenches and form the counter electrode of the trench capacitor) from the wafer backside. This step also uses a downstream chemical dry etch (downstream microwave) process using fluorine chemistry to quickly remove the backside polysilicon (3500 8, thick). The wafer is processed upside down with a photoresist coating on the front side to protect it.

6.5.7 Inter-Polysilicon Oxide Mask This step opens the active regions that were covered to protect the silicon during the I:implant. It is a wet etch that stops on active silicon after etching the thin (500 %.) oxide.

6.5.8 Gate Mask The definition of the gate electrodes is one of the most demanding etch steps in

336

6 Etching Processes in Semiconductor Manufacturing

the process. The reasons are the C D control and sidewall profile requirements, the gate oxide selectivity requirements, and the sensitivity of the circuit to contamination and gate oxide damage at this stage in the manufacturing process. In the process under discussion, the gate oxide is relatively thick (2008,) and the gate electrode consists of polysilicon, not a polycide stack. This simplifies the etch requirements considerably. The poly is deposited, backside stripped using the downstream microwave chemical dry etch process discussed above, doped, patterned, and etched in a single wafer RIE etcher. The etch chemistry is HBr-Cl,. The resist strip after polysilicon etch requires that metal contaminants not be driven into the thin oxide protecting the source/drain regions and that the gate oxide itself not be damaged. Wafer temperature control is important here since excessive heating can drive sodium and other metals into the source drain. Reactor choice, and to a lesser extent, the choice of strip operating conditions dictate the success of this strip process. The downstream microwave stripper and a wet clean are used.

6.5.9 LDD Spacer Etch After separate N- and P-channel phosphorus and boron implants to define the lightly doped drain (LDD) regions, the LDD sidewall spacers are formed with a deposition-blanket etch sequence and the arsenic and boron source/drain implants are completed. The spacer etch is done on a 2500 8, densified CVD oxide in a single wafer RIE tool. This etch uses typical oxide etch fluorocarbon chemistry. The critical control issues are not to overetch the spacer since this will change the dimensions of the lightly doped drain itself and

expose the source drain regions to the plasma. In some salicide schemes, a spacer overetch may contribute to gate-drain shorts which form during the metal-silicon reaction that forms the silicide. This spacer etch is operated in a process regime similar to that required of blanket etchback for planarization, in that no resist is present and across the wafer uniformity is critical. Anisotropy is also a spacer etch requirement but this is not a problem with RIE or plasma etch tools.

6.5.10 Contact Etch The definition of contact holes in the inter level dielectric (ILD) has the general requirements of profile control, resist selectivity, and uniformity. Details of the isolation and ILD schemes used have a profound effect on the amount of etch required to cut through the relatively thin oxide covering gate electrodes and the thicker oxide covering the source drain. The situation (mentioned briefly above) is illustrated in Fig. 6-19. Here, the cost of ILD planarization is seen: the etch step must have high selectivity to the gate material that is located high on the isolation. Furthermore, the selectivity between oxide and source/drain silicon must be high because more overetching is required to guarantee that all the contacts are opened in the thicker glass. Here the ILD layer consists of sandwiched thin thermal oxide, undoped CVD oxide, and densified boron-phosphorussilicate-glass (BPSG) which is planarized by reflow prior to contact etch. The contact etch is performed in a batch RIE tool (see Fig. 6-3 c) using fluorocarbon chemistry. The required selectivity to silicon is 1 2 : l to protect the junctions. Refer to the discussion above about dopant loss in the source/drain areas if the contact is

6.5 Etch Processing for 4 Mb DRAM

overetched. The difficult sustaining issues for this process are endpoint (time is used), and chamber cleanliness because the etch is operated at relatively high selectivity to silicon.

6.5.11 Poly 3 Polycide Etch The third layer of polysilicon is used as an interconnect and uses MoSi, to decrease the resistance of the interconnect lines. The BPSG reflow prior to contact etch results in a locally planarized surface so the topography for this etch is not severe. 6.5.12 Contact Mask 2

This section contains some planarization steps which impact the subsequent etch step requirements. The dielectric film to be etched is a stack of a barrier oxide (undoped CVD oxide), a BPSG and a PSG film which are reflowed to planarize. The etch back is a blanket etchback performed in a single wafer plasma etch tool to reduce the thickness of the oxide stack over features. The contact etch itself is a wet/dry combination which generates a tapered profile that is easier to fill than an isotropic etch. The wet etch is followed by an anisotropic dry etch using fluorine chemistry in a batch RIE tool. Finally, the resist strip is performed in a wet/dry (microwave) strip sequence. Possible contact damage is controlled by operating the etch and strip tools under controlled power density and chamber cleanliness. 6.5.13 Metal 1 Mask

The metal etch is performed in a batch RIE tool using BCl,/Cl, chemistry: this chemistry is used to etch the TiN anti-re-

337

flective coating (ARC) and the TIN barrier as well (actually, it is impossible to stop on this barrier using metal etch chemistries). The endpoint is determined by optical emission with substantial overetch of 30%. This overetch is used for a number of reasons: the topography demands that some overetch be used; the across-the-wafer and across-the-batch etch rate uniformity requires another 10-15%; and the relatively high selectivity to oxide (8 : 1) permits long overetches. Indeed, resist loss is the limiting factor that controls overetch. The generally accepted desire to overetch at metal etch is driven in part by the relative ease of inspection: it is easy to see etch residues after metal etch. Furthermore, residues can cause shorts if they are metals and can nucleate the subsequent CVD oxide film if they are silicon or copper nodules. The photoresist strip is important in metal etch because it helps eliminate postetch corrosion. In general, no single process step has been found to eliminate corrosion for all metal films for all metal etch processes. Here, the RIE etch includes an anti-corrosion step that consists of using CF, in the main etch and running a fluorinated post-etch step prior to breaking vacuum. The strip chemistry for metal mask resist cannot contain sulfuric acid, and so organic acids are typically used to remove both the resist residues and oxidized (from the resist ash step) aluminum-containing residues present on the sidewalls. 6.5.14 Pad Mask/Polyimide Mask

This etch opens the pads in the passivation nitride and is relatively simple: the pads are large compared to the nitride thickness. Neither C D nor particle control is critical. Some problems can occur from this step however: most have to do with

338

6 Etching Processes in Semiconductor Manufacturing

obtaining good adhesion between the bond pad and the wires used to connect the chip to the carrier. The polyimide mask is used to improve the sealing of the passivation: this mask is aligned to the bond pad holes just etched in the nitride but the openings are smaller, so that the polyimide, not the nitride, interfaces with the bond pad.

6.6 Summary The types of plasma etch equipment that are commonly used in wafer fabrication has been described in detail: the most important difference between the different etch tools that are currently in use is their relative control of physical and chemical etch processes. The most accurate pattern transfer processes require low pressure RIE hardware to control profiles and critical dimensions of etched features. The important interactions between different processing steps have also been discussed when appropriate as has the metrology and process control relevant to current manufacturing requirements. The important etch steps used in VLSI production have been discussed using a 4 Mb DRAM as an example of a process flow.

6.7 References Bell. H . B.. Anderson, H . M., Light, R. W. (1988). J. Elec,trocIier?i.Soc. 135, 1184. Rondur. J.. Turner, T. R. (Eds.) (1991). Advanced TechniyueJ ,for Inregrated Circuit Processing, Proc. S P I E , p, 1392. Brassington. M.. Razouk. R.. Hu. C. (1988), IEEE Tram. Electron Dell'ices 35, 96. Broydo. S . (1983). Solid State Technol. 26, 159. Bruce. R . H.. Malafsky. G . P. (1983). J. Electrochem. Soc. 130. 1369. Buchanan. D. A , . Fortuno-Wiltshire. G. (1991). J. C ~ K . Sci. Tec.Iino1. A 9 . 804.

Chapman. B.. private conversation on Lucas Labs Vacuum Diagnostic System. Coburn. J. W. (1982). Plasma Chem. Processing 2, 1. Coburn. J. W.. Kay, E. (1972). J. Appl. Phys. 43,4965. Coburn. J. W.. Gottscho, R. A,, Hess, D. W. (1986), Plasma Processing. Mater. Res. Soc. Symp. Proc., Palo Alto. CA. Coe. M.. Rogers, S. H. (1982). SolidState Technol. 25, 79. 97. Cook. J. (1991). private communication. Current. M.. Donohoe, K., Hanley, P. R. (1989), " A n Overt'ien of Damage Resulting f r o m Ion Etching and Ion Implantation". Semicon Mtg., Osaka, Japan. d'Heurle. F. M., Gas, P. (1986), J. Mater. Res. 1, 205. Deal. B.. McNeilly, A.. KO, D. B., delaurios, J. (1990). Solid State Technol. 33, 73. Donnelly. V. M. (1989), in: Plasma Diagnostics, Vol. 1. London: Academic Press, pp. 36-37. Donohoe. K. G. (1981), Single Wafer Plasma Symp. Plasma Chem., Edinburgh, Scotland, pp. 310-317. Flamm. D.. Herb. G . K. (1989) in: Plasma Etching. London: Academic Press, pp. 2-87. Fonash, S. J. (1985). Solid State Technol. 28, 150. Geipel. H., Hsieh, N., Ishaq, M., Koburger, C.. White. F. (1980). IEEE Trans. Electron Devices ED-27. 1417. Ghezzo. M., Kaminsky, Y., Nissan-Cohen, Y,Frank, P.. Saia. R. (1989). J. Electrochem. Soc. 136, 1992. Hara. T.. Ohtsuka, N., Takeda, T., Yoshimi, T. (1986), J. Electrocheni. Sco. 133, 1489. Hess. D. W.. Bruce, R. H. (1984), Plasma Assisted Etching of Aluminum and Aluminum Alloys in Dry Etching f o r Microelectronics: Powell, R. A. (Ed.). Amsterdam: North-Holland. Hills. G., Jha, N., van den Hoeg. W. (1989), unpublished results. Hirobe, K.. Nojiri, K . (1987) J. Vac. Sci. Technol. B 5 , 594. Irving, S. (1971). Solid State Technol. 14, 47. Jillie. D., Freiberger, P., Blaisdell, T., Multani, J. (1987), J. Electrochem. Soc. 134, 1988. Kalter, H., Van de Ven, E. P. G. T. (1979), "Plasma Etching in IC Technology", Phillips Tech. Rev. 38 17/81. 200. Kern, W. (1990). J. Electrochem. Soc. 137, 1887. Kohler, K.. Coburn. J. W., Kay, E., Keller, J. H. (1985). J. Appl. Phys. 57, 59. Krough, 0. (1988). "Bromine Based Aluminum Etching", Semiconductor Int. 276. Langmuir, I. (1929). Phqs. Rev. 33, 954. Langmuir. I., Blodgett, K . B. (1923). Ph,rs. Rei'. 22. 347. Langmuir, I., Blodgett, K. B. (1924), P h j ~ Rev. . 24, 49. Langmuir, I., Mott-Smith, H. M. (1923), Gen. Electric Rev. 26, 731. Langmuir, I., Mott-Smith, H. M. (1924), Gen. Electric Rev. 27, 449, 583, 616, 726, 810.

6.7 References

Langmuir, I., Mott-Smith, H. M. (1926), Phys. Rev. 28, 727. Lee, W.-Y., Eldridge, J. M., Schwartz, G. C. (1981), J. Appl. Phys. 52, 2994. Levy, K. L., Donohoe, K. G. (1990), "Magnetically Enhanced Reactive Ion Etch Characterization of Aluminum Alloys Using Bromine and Chlorine Chemistries", Proc. ECS Symp., Montreal, Vol. 901, pp. 188-189. Liu, R. D., Williams, S., Lynch, W. (1988), Appl. Phys. Lett. 63, 1990. Manos, D. M., Dylla, H. F. (1989a) in: Plasma Etching. London: Academic Press, pp. 261 -272. Manos, D. M., Dylla, H. E (1989b) in: Plasma Etching. London: Academic Press, pp. 305-312. Miki, N., Kikuyama, H., Kawanabe, I., Miyash*ta, M., Ohmi, T. (1990), IEEE Trans. Electron Devices 37, 107. Mohammadi, E (1981), Solid State Technol. 24, 65, 92. Mu, X. C., Fonash, S. J., Rohatgi, A,, Rieger, J. (1986), Appl. Phys. Lett. 48, 1147. Murarka, S. P. (1980), J. Vac. Sci. Technol. 17. 775. Murarka, S . P. (1983), Silicide for V L S I Applications. New York: Academic Press. Murarka, S. P. (1995), Intermetallics 3 , 173. Nakamura, M, Itoga, M., Ban, Y (1981), "Investigation of Aluminum Plasma Etching by Some Halogenated Gases", Proc. Symp. Plasma Etching and Deposition, Vol. 81-1: Frieser, R., Mogab, C. (Eds.). Pennington, NJ: Electrochemical Society. Nakamura, M., Iizuka, K., Yano, H. (1988), "Variable Profile Poly-Si Etching with Low Temperature KIE and HBr Gas", Proc. Symp. Dry Process, Tokyo, Japan, pp. 58-63. Oehrlein, G., Tromp, R., Tsang, J., Lee, Y., Petrillo, E. (1985), J. Electrochem. Soc. 132, 1441. Oehrlein, G. S., Rembetski, J. F., Payne, E. H. (1990), J. Vac. Sci. Technol. B 8, 1199. Parillo, L. C. (1986), Tech. Digit I E D M , 244. Perchard, J., Smith, H., O'Connor, R., Olsen, J., Law, K. (1990), Characterization o f a Multi-Step In-Situ Plasma Enhanced Chemical Vapor Deposition ( P E C V D ) Tetraethylorthosilicate i T E O S ) Planarization Scheme for Submicron Manufacturing lllulti Chamber and In-Situ Processing of Electronic illaterials: Freund, R. (Ed.), Proc. S P I E 1188, pp. 75-85. Phelps, A. V., Van Brunt, R. J. (1988), J. Appl. Phys. 6 4 , 4269. Powell, R. A,, Downey, D. F. (1984), in: Dry Etching f h r Microelectronics: Powell, R. A. (Ed.). Amsterdam: North Holland Physics Publ., p. 113.

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Sato, M., Arita, Y (1984), Proc. D r j Process S,j.nip., Tokyo, Japan, pp. 109-1 14. Sawai, H., Fujiwara, N., Ogawa, T.. Yoneda. M.. Nishioka, K. (1989), "Reaction Mechanism of' Highly Selective Etching of AlSiCu Using Brominated Gas Plasma, Proc. Drj' Process S j m p . " , Tokyo, Japan, pp. 45-50. Sekine, M., Horioka, K., Arikado, T., Maraguchi. Y . Okano, H. (1988), "Highly Selective Etching of' Phosphorous Doped Polycrystalline Silicon at Lon, Wafer Temperature Employing Magnetron Plasma". Proc. Dry Process Symp., Tokyo, Japan, pp. 5457. Silvestri, V. J. (1986), J. Electrochem. Soc. 133, 2374. Sinha, A., Lindenberger, S., Fraser, D., Murarka, S.. Fuls, E. N. (1980), IEEE Trans. Electron Devices, ED-271'8), 1425. Smith, D., Bruce, R. H. (1982). J. Electrochem. SOC. 129, 2045. Smits, C. G. (Ed.) (1960-62), The Collected Works of Irving Langmuir. New York: Pergamon Press. Tachi, S., Okudaira, S. (1986). J. Vac. Sci. Technol. B 4 ( 2 ) , 459. Tsujimoto, K, Tachi, S., Arai, S., Kawakami, H., Okudaira, S. (1988), "Low-Temperature Microwave Plasma Etching", Proc. Dry Process Symp., Tokyo, Japan, pp. 42-49. Turner, T. R. (1991a), "Correlations of Real Time Monitored Process Module Parameters and Wafer Results", Proc. SPIE. p. 1392. Turner, T. R. (1991 b), Sensor Feasibilitj' Stud),, SEMATECH Technology Transfer Document. Turner, T. R. (1991 c), PRSC Final Report, SEMATECH Technology Transfer Document. Van den Meerakker, J., Van den Straten, (1990). J. Electrochem. Soc. 137, 679. Vasile, M. J., Dylla, H. E (1989), in: Plasma Diagnostics, Vol. 1. London: Academic Press, pp. 185-232. Vasquez, B., Tompkins, H., Fejes, P., Lee, T., Smith, L. (1989), "Characterizations of Sidewall Passivation Material Deposited During Trench Etch", S P I E Conf., Santa Clara, CA, paper 1185-14. Vossen, J., Kern, W. (Eds.) (1978), Thin Film Processes. New York: Academic Press, Secs. V-1, V-2. Winkler, U., Schmidt, E, Hoffman, N . (1981). The Influence of Humidity on the Reproducibility of Aluminum Etching in Plasma Processing: Frieser. R. G., Mogab, C. J. (Eds.). Pennington, NJ: Electrochemical Society, pp. 253-255. Wu, I., Street, R., Mikkelsen, J., Jr. (1988). Appl. Phys. Lett. 63, 1628.

7 Silicon Device Structures Chun-Yen Chang and Simon M . Sze

National Chiao Tung University. Hsinchu. Taiwan. R.O.C.

List of 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.4.1 7.3.4.2 7.3.4.3 7.3.4.4 7.3.5 7.3.6 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.6 7.7 7.8

Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Potential-Effect Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nC-i-n+ Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Planar Doped Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p-n Junction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Heterojunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Heterojunction Bipolar Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thyristors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hot Electron Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field-Effect Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metal-Silicon Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . hom*ogeneous Field-Effect Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M O S Structure and Charge-Coupled Devices . . . . . . . . . . . . . . . . . . . . . . . . . MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Submicrometer MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silicon-on-Insulator Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thin-Film Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microvacuum Field Emitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quantum-Effect Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quantum Wells, Wires, and Dots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resonant-Tunneling Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Quantum Well Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resonant-Tunneling Hot-Electron Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . Microwave and Photonic Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMPATT Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BARITT Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Photodetectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Solar Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

342 345 346 346 347 348 350 352 353 355 357 358 358 360 360 362 362 366 367 368 370 371 373 373 373 375 377 377 380 380

382 382 385 387 389 389

342

7 Silicon Device Structures

List of Symbols and Abbreviations cross-sectional area doping region thickness capacitance thickness; dimensionality diffusion constant energy electric field bandgap difference between emitter and base valence band offset Fermi energy frequency maximum frequency of oscillation cutoff frequency transconductance Planck constant (h = h/(2 T I ) ] current gain current generation current recombination current current density Boltzmann constant wave vector length z-component of the angular momentum effective mass concentration doping concentration momentum charge charge surface density junction depth resistance subthreshold slope depleted silicon film thickness absolute temperature; transmission coefficient voltage breakdown voltage volume in k-space surface depletion width W,, W,, Wsub depletion layer width of source, drain, supporting silicon substrate Z total number of states x i

sum of current gain lifetime width of resonant state

List of Symbols and Abbreviations

BARITT BICFET BICMOS CCD CMOS CTE CVD

DBQW DBRTD 2 DEG 2DHG DOS EEPROM EPROM FAMOS FIPOS HBT HET HIPOX IBT IGBT IMPATT JFET LDD LRP LT MBE

infinitesimal thickness permittivity dielectric permittivities in silicon, metal emission efficiency wavelength; penetration depth cutoff wavelength electron mobility valley degeneracy charge density lifetime barrier lowering metal work function change in electrostatic potential heterojunction barrier barrier height for electrons in the metal; Schottky barrier electron affinity barrier injection transit time bipolar inversion-channel field-effect transistor bipolar complementary metal-oxide semiconductor charge-coupled device complementary metal-oxide semiconductor charge-transfer efficiency chemical vapor deposition continuous wave double-barrier quantum well double-barrier resonant-tunneling diode two-dimensional electron gas two-dimensional hole gas density of states electrically erasable programmable read-only memory erasable programmable read-only memory floating gate avalanche injection metal-oxide semiconductor full isolation by porous oxidized silicon heterojunction bipolar transistor hot-electron transistor high-pressure oxidation induced base transistor insulated-gate bipolar thyristor impact ionization avalanche transit time junction field-effect transistor lightly doped drain limited reaction process low temperature molecular-beam epitaxy

343

344

MESFET MIOS MOCVD MODFET MOS MOSFET MQW NDR PBT PDB PECVD QW RTA SIMOX so1 TFT UHV ULSI VLSI ZMR

7 Silicon Device Structures

metal-semiconductor field-effect transistor metal- insulator - oxide- semiconductor metal-organic chemical vapor deposition modulation-doped field-effect transistor metal-oxide semiconductor metal-oxide semiconductor field-effect transistor multiple quantum well negative differential resistance permeable-base transistor planar-doped barrier plasma-enhanced chemical vapor deposition quantum well rapid thermal annealing separation by implanted oxygen silicon-on-insulator thin-film transistor ultra-high vacuum ultra-large-scale integration very-large-scale integration zone melting recrystallization

7.1 Introduction

7.1 Introduction Silicon is the most important semiconductor for the electronics industry. At present, silicon-based devices constitute over 95% of all semiconductor devices sold worldwide. Silicon’s dominance is the result of its bandgap, its superb natural oxide, its outstanding mechanical properties, and its abundance in nature. Silicon’s bandgap of 1.12 eV at room temperature is large enough to give relatively low leakage current from thermally generated carriers. Silicon is unique in that it possesses the most outstanding natural dielectric, silicon dioxide (SO,), which has high breakdown strength (- 10 MV/cm) and low interface trap density ( - io9 traps/cm2). Silicon is an extremely hard, unyielding semiconductor with a Knoop hardness of 1150 kg/mm2 (twice that of stainless steel) and a yield strength of 7 x lolo dyn/cm2 (a factor of 1.8 larger than tungsten). Silicon in the form of silica and silicates makes up 28% of the Earth’s crust, and silicon is second only to oxygen in abundance. Figure 7-1 shows the world production of polished single-crystal Si wafers and 111-V compound semiconductor wafers. It is apparent that silicon has much higher production volume due to its pre-eminent position in very-large-scale integrated (VLSI) circuits as well as numerous discrete-device applications. We anticipate that this production trend will continue. By the year 2000, silicon wafer area will reach 10 square kilometers (or about 200 million wafers with a 250 mm diameter) while the 111-V compound wafer area will be about two orders of magnitude lower (Pearce, 1988; Meindl, 1984). Semiconductor devices can be broadly divided into three groups: potential-effect

345

-1 1

1960

1980 YEAR

2000

Figure 7-1. World production of single-crystal silicon and I11 -V compound semiconductors (after Pearce, 1988; Meindl, 1984).

devices, field-effect devices, and quantumeffect devices. Potential-effect devices, considered in Sect. 7.2, are current controlled, with the control electrode resistively coupled to the active device region, and the charge carriers separated energetically by an energy barrier. Potential-effect devices include the classic bipolar transistor and the heterojunction bipolar transistor. Fieldeffect devices, considered in Sect. 7.3, are voltage controlled, with the control electrode capacitively coupled to the active region of the device and the charge carriers separated by an insulator or a depletion layer. Field-effect devices include the MOSFET, MESFET, and MODFET. Quantum-effect devices, presented in Sect. 7.4, use resonant tunneling to provide controlled transport. In such devices, the operational distance is comparable to the de Broglie wavelength (2 = h / p , where h is Planck’s constant and p is the momentum), which is about 200 8, at room temperature.

346

7 Silicon Device Structures

Quantum-effect devices can increase the operational speed above that achievable by the conventional potential-effect or fieldeffect devices. In addition, many quantumeffect devices are functional devices, i.e., they can perform a given electronic function with a minimum number of electronic components. Silicon microwave and photonic diodes are covered in Sect. 7.5. The operation of most of these devices is based on the potential-effect principle. Microwave diodes are two-terminal devices that can generate, amplify, or detect signals at microwave frequencies (1 to 1000 GHz). The silicon microwave diodes to be considered are the IMPATT diode and the BARITT diode. Silicon photonic devices include the photodetector, which can detect optical signals through electronic processes, and the solar cell, which can convert optical radiation into electrical energy. We expect that silicon-based devices will remain the dominant devices for electronic applications in the foreseeable future. An outlook for advanced silicon-device structures is presented in Sect. 7.6.

7.2 Potential-Effect Devices

v=0

100

10-210-1 100 10' i o 2 l o 3 i o 4 APPLIED B l A S ( P V )

(b)

In Fig. 7-2a, the n+-i-n+ diode is a majority-carrier device (electron conduction in n f - n - - n + and hole conduction in p + i-p+) in which a semicircular potential is formed between these two heavily doped electrodes. The formation of the barrier is due to the electron concentration n

(

7.2.1 n + - i - n + Diode

n = Ncexp - Ed.;,

(7-1)

in the i-layer, which constitutes a charge density e in the Poisson equation.

Figure 7-2. Illustration of the n-i n diode under applied bias. (a) Schematic profiles of the electric field and the electrostatic potential energy. The energy diagram also shows the quasi-Fermi level E F ( x )(dashed line). (b) Calculated current-voltage characteristics (Luryi, 1990).

The I - V characteristic is shown in Fig. 7-2b, which can be expressed at high voltage as (7-2)

7.2 Potential-Effect Devices

where j is the current density, L the i-layer thickness, E , the permeability, and p the electron mobility. Equation (7-2) is identical to the classical Mott-Gurney law (Luryi, 1990) for space-charge-limited current, and at low voltage the I- V characteristic becomes

347

I - L I t L2-+ n

I n 1

-&-\NEGATIVE

(7-3) which represents a linear law. n(0) is the carrier concentration at x = 0. The n+-i-n+ or p+-i-p+ diode is one of the building blocks for various kinds of novel electron devices.

7.2.2 Planar Doped Barrier The planar-doped-barrier (PDB) rectifying structure was first demonstrated in GaAs molecular-beam-epitaxy (MBE) grown samples (Malik et al., 1980). It represents an extension (the limiting case) of the camel-diode structure. We begin by reviewing the theory of rectification and charge injection in this important structure (Kazarinov and Luryi, 1982). A PDB [n-i-6 (p’)-i-n] structure, as shown in Fig. 7-3 a, has a nearly intrinsic (i) layer of thickness L sandwiched between two n-type layers of low resistivity. In the process of epitaxial growth, a p+-doped layer of (infinitesimal) thickness 6 << L with a doping of NA is built into the i region. Acceptors in the p + layer are completely ionized, that is, completely depleted of holes. A negative charge sheet of surface density Q = q NA 6 gives rise to a triangular potential barrier with shoulders L , and L , and a height 4 given approximately by

(7-4) This expression corresponds to a “capacitor” model in which the fixed charge Q

I-

102

a a

FORWARD 10-2 10-4

+ :0.68eV

0 6 0.5 1 1.5 2 APPLIED VOLTAGE ( V )

(b) Figure 7-3. (a) Schematic illustration of the planardoped triangular barrier. (b) Calculated I -- V characteristics for a Si PDB diode with the following parameters: L , = 250 A, L , = 2000A, ND= 10’’ ~ m - ~ , Q / q = 2 x 10” (after Luryi, 1990).

induces charges only in an infinitesimally thin layer of the doped contacts at the boundaries of the i layers. In equilibrium, the barrier height is the same on both sides if the doping in both contact layers is identical. Under an applied bias r! the height of the emitter (“uphill”) barrier will decrease by the amount V L , / L (without loss of generality, we can assume that the emitter barrier corresponds to the shoulder L,) giving

348

7 Silicon Device Structures

rise to an exponentially increasing current I ^x e P V L l L 2 (7-5) where fl q,’(k T ) . The band diagram of the planar-doped diode is shown in Fig. 7-3 a under equilibrium ( V = 0) and nonequilibrium conditions [V(F) for forward bias and V(R) for reverse bias]. As can be seen from the figure, the barrier at the left is lowered (forward bias) by V, while the barrier at the right is increased by V, in a reverse-bias sense, which is similar to the emitter-base and the base-collector harriers in an npn transistor, respectively. Figure 7-3 b shows I - V characteristics of a Si PDB with different lengths for L , and L,, ( L , / L , = 8), and indicates that the device acts as a rectifier. The planar-doped barrier is another name for the “trinangular barrier”. I t can also be built by grading the bandgap to make a triangular shape in the conduction or valence band, by using graded compositions of Si:Ge, Si,’SiC (Jwo and Chang, 1986), and GaAsIAlGaAs (Allyn et al., 1980), etc. The planar-doped barrier is akin to a Schottky diode, with the advantage that the barrier height can be modified by the composition, doping or by controlling L , and L,. 7.2.3 p-n Junction The most important characteristic of p-n junctions is their ability to rectify, that is, they allow current to flow easily in only one direction. When we apply a “forward bias” to the junction, the current increases rapidly as the voltage increases. However, when we apply a “reverse bias”, virtually no current flows initially. As the reverse bias is increased, the current remains very small until a critical voltage is reached, at

which point the current suddenly increases. This sudden increase in current is referred to as the junction breakdown. The applied forward voltage is usually less than 1 V, but the reverse critical voltage, or breakdown voltage, can vary from just a few volts to many thousands of volts depending on the doping concentration and other device parameters. The p-n junction is the basic building block of the bipolar transistor and thyristor, as well as of JFETs and MOSFETs. Given proper biasing conditions or exposure to light, the p-n junction also functions as either a microwave or photonic device. Figure 7-4a shows the p-n junction cross section, the minority-carrier concentration, and the current across the depletion layer. The depletion layer is developed in the vicinity of the metallurgical junction when a bias V is applied (forward bias on the left side of Fig. 7-4 a and reverse bias on the right side). The band diagram is shown in Fig. 7-4b. The quasi-Fermi levels E,, and E,, are split by an amount equal to T.: Therefore, the nonequilibrium minoritycarrier density at the depletion-layer edges are in accordance with the position of E,, in the p layer, and of EFpin the n layer. As shown, for example, under forward bias, n, (0) = npo exp [q V / ( kT)], while p , (0) = where npo’ P n o are the no exp [ q V / ( k minority carrier concentrations at equilibrium ( V = 0). The slopes of these carrier profiles represent the respective diffusion current by the equation

where i = n or p, i.e., C, = n, C, = p , Di the diffusion constant, Li the diffusion length = v&, and si the carrier lifetime. The

7.2 Potential-Effect Devices

FORWARD

349

REVERSE

Ln W Lp

+.l-i-l 4

E FP

\ \ I

\ EFn

E Fn

Figure 7-4. (a) Injected minority carrier distribution and electron and hole diffusion currents of a pn junction under forward and reverse bias. (b) Band diagram and quasi-Fermi levels E,,, EFp.

total diffusion current becomes

while the generation current is

where A is the junction cross-sectional area. Another current comes from the recombination-generation process in the depletion layer. Under forward bias the net rate is due to recombination, while under reverse bias it is due to generation (Sze, 1981, 1985). The recombination current is

where W is the depletion layer width. Figure 7-5 shows the I-V curves for a typical Si p-n junction under forward (a) and reverse (b) conditions, respectively. At low bias, the factor exp[q V/(2k T ) ]is dominant while at high bias exp [q V / ( kT ) ]predominates. The increase of I , versus V is mainly due to an increase in the depletionlayer width W The breakdown voltage V, for a given background concentration can be ob-

(7-8)

350

7 Silicon D e v i c e Structures

l,11111,

l1,1,,1,

I I11111,

io7

I I,(I

ONE- SIDED ABRUPT JUNCTION

.\"

-> E

-1

W -I

10-6

10'~

1 015

10'6

BACKGROUND DOPING NB ( ~ r n - ~ )

Figure 7-6. Depletion-layer width ( Wm), maximum field at breakdown (8,)and breakdown voltage (V,) for one-sided abrupt Si pn junctions (after Sze and Gibbons, 1966).

10-8

10-12 10-3

10-2

10-1100 101

plotted in Fig. 7-6 for a one-sided abrupt Si p-n junction at 300 K.

102

vR(v)

7.2.4 Bipolar Transistor

(b) Figure 7-5. The current-voltage characteristics of a Si pn diode at various temperatures. (a) Forward bias. (b) Rekerse bias.

tained from the maximum depletion-layer width W, and the maximum critical field 6,, 6 , = q NBW,/E,. The breakdown voltage V, is 2

, 6, v, = E__ NB-

(7-10)

The breakdown voltage, the maximum field e,, and the maximum depletion-layer width at breakdown W, versus NB are

The bipolar transistor is an active threeterminal device that combines an n-p junction and a p-n junction by means of a common middle p layer (base) which is very narrow. This is the npn bipolar transistor. Its complementary type is the pnp bipolar transistor. The band diagram of an npn bipolar transistor is shown in Fig. 7-7a. The solid lines are for the normal bias condition (i.e., emitter-base forward biased and the base-collector reverse biased) and the dotted lines for the equilibrium condition. Figure 7-7 b shows the minority carrier distribution profiles. Note that due

7.2 Potential-Effect Devices

EMITTER

BASE

COLLECTOR

VF: *0.6V E

E Fn

(a) REVERSE

FORWARD

- -

EMITTER

BASE

I R

COLLECTOR

bJLL I LUX

35 1

tion current I , in the E-B junction and a generation current I, in the C-B junction as shown in Fig. 7-7 b. In Fig. 7-7c, the electron current In, is emitted from the E-B junction and diffuses through the base with partial leakage to the base due to electron-hole recombination InB.The remainder In, is collected by the collector electrode. Hole-diffusion current IpEand I, is injected from the base to the emitter. This current makes no contribution to the collector current. Therefore, to achieve a high current gain, the hole-diffusion current should be minimized. I , and I , are the leakage currents due to diffusion and generation, respectively, under a C-B reverse bias condition. The inverse of current gain h;' can be expressed (Yang, 1988) as

NdC

Applying the p-n junction current theory,

0.6V

(C)

Figure 7-7. An npn transistor in equilibrium and in nonequilibrium. (a) Band diagram and quasi-Fermi levels under bias compared to a no-bias condition. (b) Minority-carrier concentrations under normal active bias. (c) Carrier flows in the respective regions.

to a reverse bias applied to the collectorbase (C-B) junction, nP(xB)% 0 while n, (0) = npoexp [q V&/k T ) ]due to forward bias in the emitter-base (E-B) junction. It is easy to apply the same principle, discussed in the previous section (7.2.3), to derive the current flows in the respective regions. In addition, there is a recombina-

NA 'B

'dE

e - e V e / ( 2 kT )

(7-12)

DnB ni ' 0

Subscripts E, B, C refer to the emitter, base, and collector respectively. From Eq. (7-12), hfe increases with decreasing base doping concentration NAB. This, in turn, decreases the high-frequency performance due to a large base spreading resistance R B B . The maximum unity-power-gain frequency f,,, is (Sze, 1990) (7-13) where f is the cutoff frequency at unity current iain due to total delay and transit time from E to C. A heterojunction bipolar

352

7 Silicon Device Structures

transistor can meet the requirements of both high gain and high-frequency response by having wider bandgap material in the emitter. This will be discussed in the following two sections. A modern high-frequency, doped polycrystalline emitter, bipolar transistor is shown in Fig. 7-8. The device was fabricated in a double-polysilicon self-aligned bipolar process (Chen et al., 1989). A schematic cross section is shown in Fig. 7-8 a. A p - substrate with an n+/n-epitaxial layer was used. Then, the device fabrication follows the polysilicon refilled-trench isolation process. An epitaxial p-type layer was grown on top of n-collector and isolationE

oxide layer. After p+-polysilicon delineation, oxidation, and n f -polydeposition at the emitter window, a thermal furnace and rapid thermal annealing were used to provide a shallow emitter-base junction. A representative device profile is shown in Fig. 7-8b. The estimated base widths range from 63 to 95 nm with an emitterbase junction depth of about 25 nm. Such devices exhibit gains ranging from around 100 to 200, depending on the base implant dose and the resulting base Gummel number. The cutoff frequency f, reaches 51 GHz at a current density of more than 1.0 mA/pm2 while maintaining an emittercollector breakdown of 3 V. The total transit time is less than 3.0 ps.

C 7.2.5 Heterojunction

n' - EPI

-.P

10'8

i J

0.0

0.1

0.2 0.3 DEPTH ( p m )

0.4

0.5

(b)

Figure 7-8. The self-aligned poly-Si emitter npn bipolar transistor. ( a ) Schematic device cross section. (b) Representative secondary ion mass spectrometry (SIMS) profile of a device obtained from a monitor wafer (after Chen ct ai.. 1989).

In the early 1980s, a new unorthodox player emerged on the heterostructure scene, Ge,Si, - x on Si (Kasper and Bean, 1989).The lattice constant of germanium is about 4% larger than that of silicon. For a strained, but not relaxed, overgrowth layer that obeys a rule of equilibrium, the overgrowth thickness should not exceed a critical thickness L , as is shown in Fig. 7-9 with different germanium fractions x. The bandgap versus x is also shown and decreases with increasing x values. The epitaxial growth techniques involve the molecular beam epitaxy (People, 1985), UHV/CVD (Meyerson, 1986), limited reaction process (Gibbons et al., 1985), etc. The band alignment of Ge,Si ,on Si substrates for different x values is shown in Fig. 7-10. The bandgap discontinuity in the conduction band is always smaller than that in the valence band, e.g., AE, = 0.020 eV while AEv = 0.15 eV for x = 0.2, as shown in Fig. 7-loa. For x = 0.5, A E , = 0.15 eV and AEv = 0.30 eV on an unstrained (001) Geo,25Sio,,5buffer layer

353

7.2 Potential-Effect Devices

(not shown), as illustrated in Fig. 7-lob. Figure 7-1Oc shows the band alignment of the Ge,,,5Sio,5/Si heterostructure on a (001) Si substrate (People and Bean, 1986). The heterostructure is the building block for various kinds of novel GeSi/Si devices such as the heterojunction bipolar transistor, MODFET, and resonant-tunneling devices, which will be discussed in more detail in the following sections.

7.2.6 Heterojunction Bipolar Transistor The heterojunction bipolar transistor (HBT) offers numerous advantages over conventional hom*ojunction bipolar transistors for high-frequency and high-speed applications. The advantage is due to the HBT's higher emitter injection efficiency as a result of the bandgap of its emitter being larger than that of its base. Thus, higher base doping and lower emitter doping can be used to reduce the emitter-base delay time. The use of a graded base can further reduce the base transit time.

A E c = 0.020eV

STRAINED Eg (Geo.zSio.8 ) = l.OeV

CUBIC E9 (Si)=1.17eV

A Ev = 0.15 eV

'-7-

(a)

AEc= 0.150eV EC

t STRAINED

STRAINED Eg (Geo.sSio.5

089eV

Eg (SiI = 1.04eV AEv

- -

= 0.30eV

(b)

AEc= 0.020eV --E-

CUBIC

STRAINED Ep (Geo.sSi0.s

= 0.78eV

E g ( S i ) = 1.17eV

I (C)

GexSi,., ON SI

1.3

SUBSTRATE

Figure 7-10. Band alignments for (a) Ge,,,Si,,,/Si heterostructures on (001) Si substrates, (b) Ge,,,Si,,,/Si heterostructures on an unstrained (001) G e o , 2 ~ S i o , , ~ buffer layer, and (c) Ge,,,Si,,,/Si heterostructures on (001)Si substrates (after People and Bean, 1986).

1.2

1.1

Figure 7-11 a shows the band diagram of an HBT. Following the analysis of Eq. (7-12), the current gain, limited by emitter injection efficiency, is

1.0

0.9

w 0.8 0.7

0 Si

0.4 0.6 0.8 1.0 Ge FRACTION , x Ge

0.2

Figure 7-9. The critical thickness and bandgap energy versus Ge fraction of strained GeSi on a Si substrate (Bean, 1978).

where A E g is the bandgap difference of the emitter and the base. Representative doping concentrations in state-of-the-art HBTs fabricated in the Si/GeSi system are shown in Fig. 7-1 1 b,

354

7 Silicon Device Structures

-5 SiGe

B (a)

IO2'

(550 "C) epitaxial silicon deposition process known as ultra-high vacuum chemical-vapor deposition (UHV/CVD). Demonstrated in this work are the excellent quality of Si/GeSi junctions formed using this method, the advantages of GeSi for bipolar device design, and the integration of this technology into a polyemitter bipolar process. Figure 7-12 a shows the polyemitter bipolar structure with emitter dimensions of only 1.2 x 2.4 pm', that was used in this work. An example of the final doping profile of a GeSi-base device is shown in Fig. 7-12b. In the GeSi-base transistors, the Ge content was graded from 0 to 14% across the base (roughly 6 to 13% across

P EPI BASE 'N

I 1

0 0.2

0,4

0.6

0.8

5 1.0

EPI

P - SUBSTRATE

(a)

DEPTH (urn) (b)

Figure 7-11. (a) Representative band diagram and (b) doping profile of an HBT.

which should be compared with those of Fig. 7-8 b for the hom*ojunction transistor. In HBTs, doping levels of lo2' cm-3 have been used in the base. As a result, base sheet resistance can be greatly decreased, even with ultra-narrow base regions, and transistor f,,, can be greatly increased, (Eq. (7-12)). In recent work (Meyerson et al., 1990), Si and graded-GeSi-base bipolar transistors were fabricated in a standard polyemitter bipolar process using the low-temperature

DEPTH ( n m )

(b)

Figure 7-12. (a) Schematic cross section of the nonself-aligned bipolar structure with a base formed by UHV'CVD low-temperature epitaxy. (b) SIMS impurity profile of a 75 GHz (GeSi-base transistor (poly-Si emitter contact not shown) (after Meyerson et al., 1990).

7.2 Potential-Effect Devices

the neutral base region), with the highest Ge percentage (largest bandgap reduction) occurring at the base-collector junction. The smaller bandgap in the base reduces the barrier for electron injection into that region, while the bandgap grading introduces a drift field (over 15 kV/cm) to aid the transport of electrons across the neutral base. The maximum cutoff frequency of the GeSi transistor increases from 75GHz at 298 K to 94 GHz at 85 K at a collector current of 28 mA. Equally significant, the peak cutoff frequency of the hom*ojunction Si device increases from 52 to 57 GHz for a doubling of collector current, as illustrated in Fig. 7-13. The larger relative improvement for the graded-GeSi base transistor results from the quasi-field created by the bandgap grading in the base. This field is more effective at low temperatures, and it compensates the degradation in diffusivity of the base (Grabbe et al., 1990). A combination of the high density of ULSI and the high speed capability of GeSi-based HBT technology will have dramatic impact on future electronics system applications.

7.2.7 Thyristors The thyristor is a four-layer device that has an npnp or a pnpn structure. It can be treated as two transistors, one an npn and the other a pnp, connected in series. A schematic diagram of a thyristor is shown in Fig. 7-14a. Under forward conducting conditions, both p l -pl and n2-p2 are reverse biased while nl -p2 is forward biased. When the sum of current gains zl,a2 of the two transistors becomes unity, the device is turned on to a high-conduction state. The doping profile and the currentvoltage characteristics are shown in Fig. 7 -14 b and c, respectively (Yang, 1988). The

TEMPERATURE

0.004

0.006

0.008 1/T

(

355

0.01

0.012

(K-')

Figure 7-13. Collector current dependence of iT at 298 K and 85 K for Si and SiGe devices. In both cases, the peak fT and the associated collector current increase at lower temperature (after Grabbe et al., 1990).

basis current-voltage characteristic of a p-n-p-n diode exhibits five distinct regions: 0 -+ 1: The device is in the forward-blocking or off state and has a very high impedance. Forward breakover (or switching) occurs where dVdZ = 0; at point 1 we define a forwardbreakover voltage V , and a switching current I,.

356

7 Silicon Device Structures

’A

REV

/\i~:c

B~EAKDOW~N/

;;R:;S.

(3)

FORWARD C0,NDUCTING

1 FORWARD BLCCK~NG WITH Ig TRIGGERING

(C)

Figure 7-14. (a) Planar three-terminal thyristor (b) Doping profile (c) I’V characteristics with I , (gate bias current) trigger

2: The device is in a negative-resistance region, that is, the current increases as the voltage decreases sharply. 2 + 3: The device is in the forward-conducting or on state and has a low impedance. A t point 2, where dV/dl = 0. we define the holding current I , and holding voltage V,. 0 + 4: The device is in the reverse-blocking state. 4 + 5: The device is in the reverse-breakdown region. Thus, a p-n-p-n diode operated in the forward region is a bistable device that can 1

switch from a high-impedance, low-current off state to a low-impedance, high-current on state, or vice versa. The device can be operated in a threeterminal mode. The turn-on behavior can be modified by increasing the gate bias current I , turning on the device at a lower breakover voltage. Another type of thyristor, called the insulated-gate bipolar thyristor (IGBT), can handle power up to 1 MW and can be turned on and off quickly. Figure 7-15 shows the structure of the IGBT. The IGBT is composed of an npnp thyristor and a MOSFET that acts as a gate to control the device’s on/off mode. When a positive bias is applied to th gate, the p base is inverted into the n channel along the Si0,-Si interface, which turns the device on immediately. The device can sustain a voltage of 2000 V and can be turned on in microseconds. Turning off is faster and happens within 0.2 ps. The devices were processed on 90 R cm bulk silicon material with a thickness of 350 pm.The back side emitter was formed by a shallow backside boron implantation. No lifetime-killing steps were used. The result is a 2000 V IGBT on an area of 6.5 x 6.5 mm2 with an on-state voltage of 4.5 V at 15 A. To get the high blocking voltage, two factors have to G

t n-

Figure 7-15. 2000 V insulated-gate bipolar thyristor (IGBT). The gate (G) inverts p- into n-channel and switches the device to a high conduction state (Laska and Miller, 1990).

357

7.2 Potential-Effect Devices

be considered: a suitable junction termination using a poly-Si/Al field plate and a substrate with a width of 550 pm, which can sustain 2000 V. The device exhibited a turn-off time of 200ns. It can switch a shorted load up to 1800 V with a gate voltage of 20V. The current is limited to 160 A (570 A/cm2) by the device itself (Laska and Miller, 1990).

7.2.8 Hot Electron Transistor Basically, a hot electron transistor consists of an emitter that ejects electrons by a thermionic process, a base that controls the ejected current, and a collector that collects the current ejected ballistically from the base. In this section, two types of hot electron transistors are presented, namely the bipolar inversion-channel field effect transistor (BICFET) and the induced base transistor (IBT). Both of them can be built on a Si substrate with epitaxially grown SiGe/Si layers. The Ge,Si, -,/Si system is ideally suited for a silicon-based implementation of the p-channel BICFET because of the band lineup between unstrained silicon and commensurately strained Ge,Si, -,. Almost all of the band offset lies in the valence band, leading to a AEv = 0.37 eV for x = 0.5. Figures 7-16a and b show the charge distribution and the vertical cross section of the silicon-based BICFET band structure, respectively (Taft et al., 1989). The transistor is doped n-type, except for a very narrow region that is doped p-type. This p-type region is so narrow that there is insufficient band bending to produce a charge-neutral region of holes. However, the negative-acceptor charge sheet sets up a thermionic barrier that prevents electron flow even when a positive bias is applied to

‘0.0

0.5

1.0

1.5

APPLIED COLLECTOR VOLTAGE ( V 1

(C)

Figure 7-16. Bipolar inversion-channel field effect transistor (BICFET). (a) Charge distribution. (b) Band diagram under bias. (c) l / V characteristics. The common-emitter characteristics are for a single-basecontact, 4 pmm BICFET (Taft et al., 1989).

the collector. The collector current is controlled by the hole quasi-Fermi level of the base region, or equivalently, the concentration of holes in the inversion channel, which can act directly to lower the barrier. The doping profile and the composition profile are also indicated in Fig. 7-16 b. Before forming a two-dimensional hole gas (2DHG) in the narrow (5OA-lOOA) GeSi layer, the n+-i-6p-i-nf structure forms a triangular barrier shown in Fig.

358

7 Silicon Device Structures

7-16a. When a positive bias is applied to the collector with respect to the emitter, a 2 DHG is formed that reduces the effect of A p (depleted negative delta charges). The reduced effect of A p causes a barrier lowering A 4 which, in turn, increases the electron emission from the emitter. The amount of barrier lowering is

NA-

(7-15) where A p is the 2DHG concentration induced by VEB.The current

I at A* T2e-40'(kT)eA4'/kT)

-SlGe

I-SI

OEPLETED CHARGE SHEETS 20 HOLE GAS

(7-16)

The current-voltage characteristics are shown in Fig. 7-16c. The effect of V,, which induces A$ is obvious. Because of the high conductance of the 2 DHG in the base, the device can operate at high speed and has high current handling capability. The implementation of an inducedbased transistor (IBT) ion a Ge/Si heterosystem is desirable (provided, of course, that one can achieve a high-quality interface of these lattice-mismatched materials). It makes sense to use the injection of hot holes because, unlike the conduction-band minima, the valence-band maxima are located at the same k = 0 point in both semiconductors. For a discussion of other exotic possibilities related to the IBT concept, see Luryi (1990) and Chang et al. (1986). The proposed induced-base transistor layer structure and band diagram is shown in Fig. 7-1 7. Layers 1 -4 are GeSi, and layer 5 is undoped Si. In GeSi, the p+-i - 6n'-i2DHG forms a triangular barrier. At the GeSi-Si interface, there is a band discontinuity AEv, Holes are injected from emitter to base and traverse ballistically to the collector. The 2 DHG produces a barrier lowering, which enhances the hole emission.

(a)

'--3 LLECTOR

GclSi A L i o r / UNDOPED

UNDOFED

AEv

(b)

Figure 7-17. Proposed induced-base transistor (IBT). (a) Charge distribution. (b) Band diagram (after Luryi, 1990).

7.3 Field-Effect Devices 7.3.1 Metal-Silicon Contact The first systematically studied semiconductor device was the metal-semiconductor contact (by Braun in 1874), which also happened to be the first practical semiconductor device (in the form of a point contact rectifier in 1904). In 1938, Schottky suggested that the rectifying behavior could arise from a potential barrier as a result of a stable space charge in the semiconductor. The model arising from his consideration is known as the Schottky barrier. Metal-semiconductor contacts

' For a collection of pioneering papers in metal-semiconductor contacts and other semiconductor devices see Sze (1991).

7.3 Field-Effect Devices

can also be nonrectifying; that is, the contact has a negligible resistance regardless of the polarity of the applied voltage. Such a contact is called an ohmic contact. All semiconductor devices as well as integrated circuits need ohmic contacts to make connections to other devices in an electronic system. The metal-silicon contact is the most extensively studied among all metal-semiconductor systems because of its importance in silicon-based devices and VLSI (very-large-scale integration) circuits. For high-barrier contacts operated at room temperature, the current transport is due mainly to thermoionic emission of majority carriers (e.g., electrons in an n-type Si) across the Schottky barrier. For lower temperatures or high doping concentrations ( > loL8 impurity atoms/cm3), field emission becomes dominant. For the classical metal-silicon contacts (e.g., Al), metals are deposited physically (e.g.,by evaporation) or chemically (e.g., by chemical vapor deposition) onto a silicon surface. One potential problem is the possible contamination of the interface between the metal layer and the silicon surface. Recently, there has been a significant emphasis on the use of silicide-silicon contacts instead of the classical metal-silicon contacts. The new contacts are of interest because (1) many silicides have relatively low resistivities and, (2) silicide is formed underneath the original silicon surface and the silicide-silicon interface is generally free of oxides, impurities, or defects. Therefore, the silicide-silicon contacts are more reproducible and highly reliable. A new model for the silicide-silicon intimate contacts has been proposed based on microphysical investigations that show the existence of an interphase layer between the silicide and the silicon surface. This transition layer is responsible for the grad-

359

ual shift from silicon to metal silicide. The equilibrium band diagram of the silicide/ transition layer/silicon is shown in Fig. 7-18. The barrier height for the electrons in the metal, 4n, is the Schottky barrier. From Fig. 7-18, we obtain

where 4Mis the metal work function, x is the electron affinity, (A4)M is the change in electrostatic potential at the metal surface, and p is given by (7-18) where d is the transition-layer thickness (about 30 8, for a CrSi,/n-Si contact), A is the penetration depth in silicide (0.5 8, for CrSi,), and E , and E , are the dielectric permittivities in silicon and metal, respectively. The new model can explain the bias and temperature dependence of the current-voltage characteristics using a fielddependent barrier height as given by Eq. (7-17) (Sze, 1991).

x:O

\SILICIDEON TII;:::\

x:d

n-Si

Figure 7-18. Thermal equilibrium energy diagram for the silicide/transition layer/n-Si system (after Sze, 1991).

360

7 Silicon Device Structures

7.3.2 hom*ogeneous Field-Effect Transistors

hom*ogeneous field-effect transistors include the JFET (junction FET), the MESFET (metal-semiconductor FET), and the PBT (permeable-base transistor). They employ hom*ogeneous semiconductor materials instead of heterojunctions to offer greater simplicity and ease of fabrication, because they do not depend critically on the precise control of layer thicknesses and sharp interfaces. The JFET consists of a conductive channel for current flow and two ohmic contacts. It uses the depletion region of a reverse-biased p-n junction as the gate electrode to modulate the crosssectional area of the conductive channel. The operation of a MESFET is identical to that of a JFET. The MESFET, however, has a metal-semiconductor rectifying contact instead of a p-n junction for the gate electrode. Silicon JFETs have been used extensively in many discrete and IC applications. Si MESFETs are more difficult to make than Si MOSFETs due to the great care needed to prevent native oxide formation at the metal-silicon interface. Furthermore, Si MESFETs are relatively unpopular, because they are outperformed by Si MOSFET and bipolar transistors. The Si permeable-base transistor (PBT) is a high-speed device that can be used in analog applications at microwave frequencies. I n contrast to the planar hom*ogeneous FETs such as JFET and MESFET, the PBT is a vertical device in which the current flow is normal to the Si waver surface rather than parallel to the surface. Because of lower effective electron velocity in Si, the frequency capabilities of the Si PBT are below that of its GaAs counterpart. However, the Si PBT provides a practical, high-performance microwave device that

Figure 7-19. Cutaway diagram of a Si permeablebase transistor (after Rathman and Niblack, 1988).

has advanced fabrication technology and superior thermal conductivity. A schematic diagram of a Si PBT is shown in Fig. 7-19. Grooves are etched into an n-type Si layer, a metal (e.g., Pt) is deposited on top of the ridges and in the bottom of the grooves and then sintered to form silicide (e.g., PtSi) emitter and base contacts. Selective ion implantation is used to dope the active region and to obtain device isolation. Si PBTs with a grating periodicity of 0.32 pm have demonstrated a maximum frequency of oscillation (fmax) of 30GHz and a cutoff frequency (f,) of 22 GHz. Si PBT has very low llfnoise and excellent performance in low-noise oscillators (Rathman and Niblack, 1988). 7.3.3 MOS Structure and Charge-Coupled Devices The MOS diode is the heart of the most important device for very-large-scale integration the MOSFET. It is also of paramount importance in semiconductor device physics. In recent years, MOS structures have been adopted for even wider applications. One example is the tactile imager for use in precision robotics applications where high packaging density and high resolution are required.

7.3 Field-Effect D e v i c e s

THIN SILICON SUPPORT BEAM

361

DEEP BORON DIFFUSION

GLASS SUBSTRATE

Si02

,< + -+ -A -,

........ ............................. .......... .......... ........ .......

Figure 7-20 shows the MOS structure of the imaging cell. The force-sensitive capacitor is formed between the lower metallic plate on the glass substrate and a thick Si center plate that is supported by two thinner Si beams. When a force is applied to the top surface of the center plate, it deflects the thin beams to change the capacitive gap and hence the cell capacitance. The dielectric film over the center plate prevents electric shorts and provides buildin over-range protection when excessive force causes the plates to touch. The fabrication sequence of the tactile imager is shown in Figs. 7-20b-e. The process starts with a p-type (100) Si wafer. The wafer is oxidized and oxide mask patterns aligned to (1 10) are formed by HF etching. The Si islands are then created by

Figure 7-20. Fabrication of an MOS tactile imaging cell: (a) device cross section, (b) KOH etch, (c) deep boron diffusion, (d) shallow boron diffusion and dielectric deposition, (e) electrostatic bonding and final wafer etching (after Suzuki et al., 1990).

anisotropic etching in KOH, Fig. 7-20 b. Next, a thick oxide is thermally grown and patterned, followed by a deep boron diffusion, which defines the thickness of the center plate and the bonding islands, Fig. 7-2Oc. All oxide is removed and a third oxide is grown and patterned, followed by a shallow boron diffusion to define the supporting beams. Finally, a thin oxide and a thin nitride layer are deposited and patterned to form the protective dielectric, Fig. 7-20d. A glass substrate is metallized and patterned. The Si structure is fused to the glass substrate by electrostatic bonding. The device is placed in an EDP (ethylene diamine-pyrocatechol-water) etchant, which etches the lightly doped silicon wafer and stops at the boron p t layer, Fig. 7-20e.

362

7 Silicon Device Structures

This MOS structure is rugged and has a high damage threshold against excessive force. It operates over a wide temperature range and has a low temperature sensitivity ( < 30 ppm/-C). A 32 x 32-element, capacitive Si tactile imager has been made; it can be read at a rate of 15 ps/element offering an effective frame rate of 5.1 ms (Suzuki et al., 1990). A charge-coupled device (CCD) is basically an array of closely spaced MOS diodes. Under the application of a proper sequence of clock-voltage pulses, the MOS diode array is biased into the deep surface depletion. By changing the potential across the array, the charge packet (representing the information) can be stored and transferred in a controlled manner across the Si substrate. To increase the clock rate and to reduce the clock voltage, an ultrafast, buriedchannel CCD with built-in drift field has been designed and fabricated. A schematic diagram of the C C D and the calculated

2.5

15.01 0

DISTANCE ( W r n )

Figure 7-21. Step-doped, charge-coupled device with the calculated potential distribution. The barrier gate is 4 prn and the storage gate is 7 pm (after Lattes et al., 1991).

potential profile are shown in Fig. 7-21. It has 4 pm barrier gates and 7 pm storage gates. The potential gradient is permanently built into the storage gate by a step implant to improve the charge-transfer efficiency (CTE) at high clock rates. The buried channel is defined by a uniform phosphorus implant, a second phosphorus implant is added to create the storage wells. The delay lines are operated with 5 V two-phase clocks. The CCD has been tested up to 325 MHz with no degradation in CTE ( > 0.99996). The equivalent C C D with uniformly doped storage wells degrades rapidly above 240 MHz (Lattes et al., 1991).

7.3.4 MOSFET 7.3.4.1 Submicrometer MOSFET The metal-oxide semiconductor fieldeffect transistor (MOSFET) is the most important device for very-large-scale integrated circuits ( > IO5 components/cm*) and ultra-large-scale integrated circuits ( > 10’ components/cm2). It is a four-terminal device as shown in Fig. 7-22a, consisting of a p-type Si substrate into which two n + regions, the source and drain, are formed. (This is called an n-channel device. One may consider a p-channel device by exchanging p for n.) The top metal contact is called the gate. Heavily-doped polysilicon or a combination of silicide and polysilicon can also be used as the gate electrode. Because the gate electrode is used as a mask to implant the source/drain regions, it self-aligns the source/drain with respect to the gate to minimize parasitic capacitance. The sidewall oxide spacer is used to bring the source/drain ohmic contacts as close as possible to the channel without shorting the source/drain to the gate electrode.

7.3 Field-Effect Devices GATE

n’

SIDEWALL OXIDE

n’

-1

p- Si

b SUBSTRATE (a1

SHALLOW n D- S i

SIDEWALL OXIDE

(b) Figure 7-22. (a) MOSFET with sidewall spacer. (b) MOSFET with sidewall spacer and lightly doped drain structure.

The basic device parameters are the channel length L, the oxide thickness d, the p-n junction depth rj, and the substrate doping N . To reduce the channel length to the submircometer ( < 1 pm) region, various approaches have been proposed. An empirical formula has been obtained to serve as a guide for MOSFET miniaturization:

Lmin= 0.4 [rj d (W, + WJ2]’I3 (pm) (7-19) where Lminis the minimum channel length to maintain proper device behavior, W, and W, are the depletion widths of source and drain, with rj, W,, W, in micrometers and d in angstroms. It is apparent that in order to reduce channel length, one must reduce rj, d, and the depletion widths (Sze, 1981). As the channel length moves into the submicrometer region, one key concern is

363

the hot-electron effect, i.e., the high-energy electrons near the drain can cause threshold-voltage shift and degradation of transconductance. To minimize the hot-electron effect, “drain engineering” has been proposed. One approach is the lightly doped drain (LDD) as shown in Fig. 7-22 b. The drain consists of a shallow lightly doped n region followed by a deeper n + region. By proper design of the doping and the extension of the shallow n region, one can substantially reduce the peak field near the drain, thus reducing the generation of hot carriers there (Brews, 1990). To place millions of devices in an IC package, we must reduce power dissipation. Because of its low power dissipation, CMOS (complementary MOS) technology becomes the dominant technology in which both n-channel and p-channel devices are constructed simultaneously on the same substrate. Two examples of submicrometer CMOS devices are shown in Fig. 7-23. The device shown in Fig. 7-23 a has twin wells on a p- substrate. Each well is 2 pm deep and of retrograde type formed by high-energy ion implantation. The 2.2 pm deep trenches isolate the wells. The wells are 1 pm wide and are filled with chemicalvapor-deposited SiO, on top of a 200A thick thermal oxidation layer of the trench surface. The active regions of each device are delineated with the LOCOS (local oxidation of silicon) process. The gate-oxide thickness is 35 A. Surface-channel nMOS and buried-channel PMOS are employed so that a phosphorus-doped n + single-gate process can be used. The use of retrograde wells and trench isolation gives the devices a high latch-up immunity. The transconductance of the 0.22 pm gate-length n- and p-MOSFETs are 450 and 330 mS/mm, and unloaded ring-oscillator delays are 36 ps at 2 V (Okazaki et al., 1990).

364

7 Silicon Device Structures P DOPED

J:-s:ocos

SI02 \

P-

(a)

PMOS

nMOS

LOW-IMPURITY-CHANNEL

EPITAXIALLY GROWN FILV

\t HIGHLY DOPED W E L L

(b) Figure 7-23. (a) Cross section of sub-0.25 pm CMOS device (after Oka7aki et al., 1990). (b) 0.1 pm CMOS device using low-impurity-channel transistors (after Aoki et al.. 1990).

improved by increasing the hole mobility. One novel approach is to place a buried Ge,Si, - - x layer under the gate of a pMOSFET as shown in Fig. 7-24a where a 100 8, Ge,Si - ,layer is grown on a Si substrate, followed by the growth of a Si spacer layer of 30-90 A, both by chemical vapor deposition. Figure 7-24b shows the band diagram at the flatband condition for a structure with a 75 8, Si spacer and a 100 8, Geo.4Sio,6 well. The quantum well for holes is created because the bandgap discontinuity between Si and Ge,Sil -,occurs predominantly in the valence band. When a negative gate voltage is applied, an inversion layer is formed in the Ge,Si, -,well as shown in Fig. 7-24c. Numerical simulations have indicated that it is desirable to employ a minium Si spacer thickness and a maximum Ge fraction to maximize the number of holes confined in the Ge,Si, -, well. Since the hole mobility in Ge,Si, -, is higher than that in Si, this MOS-gated Ge,Si -./Si heterostructure is expected to have higher transconductance, improving CMOS performance (Garone et al., 1990). A novel combination of CMOS and bipolar technology has recently been considered. This BiCMOS approach can combine the advantages of both technologies the speed and power-handling capability of bipolar devices with the ease of fabrication and high density of MOS devices. Figure 7-25 shows the cross section of a nonoverlapping, super self-aligned BiCMOS structure. The active areas of the bipolar transistor and MOSFETs are virtually identical. The structure allows complete silicidation of active polysilicon electrodes, reducing the parasitic resistances of the source, drain, and extrinsic base. The gate and emitter regions are protected from exposure and damage from reactive ion etching. All shallow p n junctions are con-

Figure 7-23 b shows a 0.1 pm CMOS using low-impurity channel transistors. The impurity concentrations in the low-impu~ , rity channels are 1016-1017~ m - which are about two orders of magnitude lower than those of the highly doped wells. The gate-oxide thickness is 50 8,. Ultra-shallow junctions are formed at 9W'C with rapid thermal annealing to give junctions of 500 8, for nMOS and 1000 8, for PMOS. By proper choice of the thickness of the low-impurity layer, we obtain low threshold voltage (due to low-impurity concentration in the channels) and high punchthrough voltage (due to the highly doped wells). The device shows a subthreshold swing of 40 m V at 77 K (Aoki et al., 1990). The performance of CMOS circuits is limited by the low transconductance of pMOSFET. This transconductance can be

7.3 Field-Effect D e v i c e s

365

ALUMINUM GATE p' BORON IMPLANT

-r

p + BORON IMPLANT

n - S i SUBSTRATE

I EC EF

Gex Sii-x WELL S i BUFFER

BULK Si

GexSii.x WELL Si BUFFER

BULK S i

(C) Figure7-24. (a) Cross section of an MOS-gated Ge,Si, - x device. (b) Thermal equilibrium band diagram of the device with a 75 8, Si buffer and a 100 8, Ge,,,Sio,, well. (c) Band diagram of the device when the Ge,,,Si,,, well is inverted (after Garone et al., 1990).

GATE

NMOS

0 Si02 POLY

S/D

tacted by polysilicon electrodes that minimize silicide-induced leakage. An arsenic buried-collector layer minimizes collector resistance. Fully recessed oxide with a polysilicon buffer layer is used to achieve low defect-density isolation. CMOS with a channel length of 1.1 pm and a width of 10 pm exhibits ring oscillator delays of 128 ps/stage. The corresponding n-p-n transistor has a cutoff frequency of 14 GHz and a ring oscillator delay of 87 ps/stage. This BiCMOS structure is suitable for gigabits per second, digital VLSI applications. By scaling down the device dimensions, even higher speed operation is anticipated (Chiu et al., 1991). Another novel combination is the integration of Si devices with compound-semiconductor devices using heteroepitaxial technology. However, there are many difficulties in Si heteroepitaxy. These include lattice mismatch (the lattice of GaAs is 4% larger than that of Si), mismatch in thermal

GATE BASE EMITTER COLLECTOR

PMOS

ALUMINUM SILICIDE

BIPOLAR

N * - REGION P * - REGION

Figure 7-25. Cross-sectional view of a nonoverlapping, super self-aligned BiCMOS structure (after Chiu et al., 1991).

366

7 Silicon Device Structures

expansion coefficient (2.6 times larger for GaAs), and antiphase disorder due to single atomic layer steps on a Si surface. Various approaches have been investigated to grow compound semiconductors heteroepitaxially on a Si substrate, and the viability of GaAs-based millimeter-wave integrated circuits on Si substrates has been established. Figure 7-26 depicts a cross section of a Si wafer showing GaAs MESFETs integrated with Si CMOS devices. The Si devices are fabricated first because they require higher temperatures for their formation than do the GaAs devices (Shichijo et al., 1988). It is conceivable that a monolithic integration of digital and analog devices, Si and non-Si devices, and electronic and photonic devices can be built on a Si substrate using heteroepitaxial technology. This technology will create novel system architectures and enhance overall system performance.

7.3.4.2 Silicon-on-Insulator Devices When devices are scaled down to submicron dimensions, they are also pushed closer together to increase the packing density. But close packing of devices places severe demands on isolation between devices. One solution to the isolation requirement is to build the circuit on an insulating substrate. A silicon-on-insulator (SOI) MOSFET is shown in Fig. 7-27 where a MOSFET is built on a silicon dioxide layer, so substrate isolation does not require buried n + regions as shown previously in Fig. 7-25. There are additional advantages of SO1 devices. Since there are no parasitic p-n-p-n's in SO1 devices, there is no latch-up in CMOS circuits. The volume of the p region under the gate is much smaller than that of the conventional device, there-

TiW/Au PLASMA LPCVD OXIDE NITRIDE

\ I

BORON lSOLATlON POLYSILICON 1

p-Si, 3' OFF

SCHOTTKY GATE

Figure7-26. Cross section of a Si wafer showing a GaAs MESFET integrated with Si CMOS devices (after Shichijo et al., 1988).

fore, only a limited number of electronhole pairs will be generated under radiation by high-energy particles. The SO1 devices can thus stand a much higher dose of radiation than a conventional MOSFET. When the silicon film (p region) is fully depleted, the device behavior will depend on both the top and bottom Si-SiO, interfaces. this two-sided behavior lowers the fields inside the device and tends to reduce hot-electron effects and short-channel effects. Furthermore, the subthreshold slope S can be improved in a fully depleted device. The slope S is proportioned to (1 + CJC,,), where C, is the capacitance between the silicon surface and ground and Coxis the gate-oxide capacitance, both per unit area. For a bulk or non-fully depleted MOSFET

c, = E,/W

(7-20)

,--SOURCE

TGATE

DRAIN

15,-02

SUB ST RATE

urn

db-0.6)~rn

Figure 7-27. A MOSFET built on an insulating substrate (after Brews, 1990).

7 . 3 Field-Effect Devices

where E , is the permittivity of Si and Wis the surface depletion width. For a fully depleted device, the capacitance C, is a series combination of the capacitances of three layers:

c,= -+-+: d b ('si

Lox

Kub\-' 6s

SILICON

367

SILICON

(7-21)

where tSi and d, are the depleted Si film thickness and the lower oxide-layer thickness, respectively (shown in Fig. 7-27), and Wsub is the depletion width in the supporting silicon substrate. If C, from eq. (7-21) is less than C, from Eq. (7-20), the SO1 device has a lower S than the bulk device for the same Cox(Brews, 1990). The major problem in SO1 technology is the relatively poor quality of the material, since it is difficult to produce a high-quality Si film on an insulating substrate. SO1 technologies include ZMR (zone-melting recrystallization of polysilicon by using a laser beam or a strip heater), FIPOS (full isolation by porous oxidized silicon), and SIMOX (separation by implanted oxygen, i.e., implantation of oxygen ions into Si followed by high-temperature annealing to form buried SiO,). These technologies are still evolving and their success depends on further improvements in the quality of Si film. A new SO1 method has been introduced to yield ultra-thin, defect-free silicon on silicon dioxide. This technique uses epitaxial okergrowth of Si and chemical-mechanical polishing. Figure 7-28 shows the fabrication sequence. A thermal oxide (0.3 pm) is grown and a polish-stop film is formed (Fig. 7-28a). Narrow lines are opened in the exposed oxide to act as a seed area for selective epitaxial silicon growth (Fig. 7-28 b). These lines are along (100) so that a defect-free film can be obtained by an epitaxial lateral overgrowth process, i.e., the growth initiates in the seed area and

(C)

(d 1

Figure 7-28. Fabrication sequence for producing Sion-insulator (SOI) structures using epitaxial lateral overgrowth and chemical-mechanical polishing (after Shahidi et al., 1990).

grows vertically and laterally over the oxide, as shown in Fig. 7-28c. Chemical-mechanical polishing is used to thin the film. The polishing process is stopped when the polish pad reaches the polish-stop film. This process produces a SO1 film thickness that is determined by the polish-stop film thickness (Fig. 7-28 d). The quality of the SO1 film is equivalent to bulk silicon, and the basic device characteristics are comparable to those resulting from fabrication on bulk. However, because SO1 devices have better isolation and lower parasitic capacitance, ring oscillator measurements on the SO1 film have shown significant speed improvement over the bulk devices (e.g., 30 ps versus 120 ps for 0.5 pm channel length devices operated at 2 V) (Shahidi et al., 1990).

7.3.4.3 Thin-Film Transistors Thin-film transistors (TFTs) are MOSFETs fabricated by depositing amorphous or polycrystalline semiconductors on largearea glass or other insulating substrates. Because of their lower costs, TFTs are potentially very useful for active-matrix liq-

368

7 Silicon D e v i c e S t r u c t u r e s

uid-crystal displays, printer heads, and image sensors. Figure 7-29a shows a cross section of a polysilicon TFT. The polysilicon films are deposited on an insulating substrate using standard low-pressure chemical vapor deposition techniques. Typically, they have a fine-grain structure of the order of 0.05 pm in diameter. To increase the grain size, lowtemperature seed selection is used by means of an ion-channeling technique. A Si ion implantation can make the deposited polysilicon film amorphous but a few (1 10) oriented grains survive the implant due to the ion channeling effect. When annealed at about 625 "C, the amorphized polysilicon film recrystallizes from the surviving grains via a solid-phase epitaxy process. Much larger grains, in excess of 1 pm, can be obtained. When the channel dimensions are reduced to the same size as the grain size, the TFT characteristics improve dramatically. A comparison of the mobilities for small and large grain sizes is shown in Fig. 7-29 b. Note the substantial increase in mobility for devices with large grains, especially with very small channel dimensions. Mobilities as high as 70 cm2 V - s and O N / O F F ratios larger than lo8 have been obtained in 2 pm devices (Yamauchi et al., 1991).

' '

7.3.4.4 Nonvolatile Memory

Nonvolatile memories are MOSFETs with modified gate electrodes to enable semipermanent charge storage inside the gate. At present, nonvolatile memories such as the EPROM (erasable programmable read-only memory) and the EEPROM (electrically erasable programmable read-only memory) constitute about 10% of all MOS IC scales. The first nonvolatile memory had a floating gate (not connected to external

AI-SI

n' POLY-Si

AI-Si

\ ' n' SPUTTERED Si02

LPCVD POLY-SI

VD = 0.5V

100

P + V

SMALL GRAIN

LL LL

0 -I

07 -

CHANNEL DIMENSION

-1-

15 W:L

(pm)

(b) Figure 7-29. (a) Cross section of a polysilicon thinfilm transistor. (b) Field-effect mobility in large and small grain polysilicon film as a function of channel dimensions (channel length = channel width) (after Yamauchi et al., 1991).

voltage) sandwiched between two insulating layers, Fig. 7-30a. When an appropriately high field is applied through the outer control gate, charge carriers transport through insulator 1 and charge the floating gate, giving rise to a threshold voltage shift. Such a device can function as a bistable, nonvolatile memory, because the charges are stored even after the charging field is removed due to a much lower probability of back-transport. If avalanche injection of electrons (near the drain) is used to charge the floating gate, we have a FAMOS (floating-gate

7.3 F i e l d - E f f e c t D e v i c e s INSULATOR 2

369

CONTROL GATE

(a) 9 VG

Si3N4

PoLYS'L'CoN sio2

n-Si

Figure 7-30. Nonvolatile memory devices. (a) Floating gate. (b) FAMOS. (c) MIOS. (d) Triple-dielectric structure (after Libsch and White, 1990).

(C)

avalanche injection MOS) nonvolatile memory (Fig. 7-30b). Since there is no outer gate electrode, the initial equilibrium condition can be restored by illuminating the device with ultraviolet light or exposing it to X-ray radiation. A MIOS (metal-insulator-oxide-semiconductor) memory device, shown in Fig. 7-3Oc, has a double-dielectric (AI-Si,N,Si0,-Si) structure. The charge carriers can tunnel through SiO, and are stored at the Si,N,-SiO, interface. Nonvolatile memories are now moving towards higher densities, faster access times, scaled-down cell sizes, lower power consumption, and lower voltage operation (e.g., 5 V for microcomputer systems). A triple-dielectric structure (Fig. 7-30d) has been proposed. Charge transport and storage can be modeled by using two-carrier (electrons and holes) injection simultaneously at both the Si-bulk and gate-electrode boundaries via Fowler-Nordheim or direct tunneling. In the case of low-voltage operations (f5 V), a projected 10 year lifespan and lo6 cycles are obtained for a device with dimensions of 20 8, for the tunnel oxide, 50 8, for the nitride, and 35 8, for the blocking oxide (Libsch and White, 1990).

A novel nonvolatile memory cell has been made based on microelectromechanics. A schematic diagram of the memory cell is shown in Fig. 7-31. The memory cell has a micromachined, conductive membrane in the form of a bridge. The bridge is longitudinally stressed so that it can buckle upward or downward and is therefore mechanically bistable. The cell is fabricated using a modified MOS process. Silicon substrate is covered with a thin, insulating thermal oxide and a spacer layer of 1.5 pm polysilicon. The polysilicon is selectively masked and the unmasked areas are implanted heavily with boron; the implanted

Figure 7-31. Schematic drawing of a rnicroelectromechanical, nonvolatile memory cell based on a bistable bridge (B), a spacer (S), and the substrate (SUB) with lateral electrodes (L) (after Holg, 1990).

370

7 Silicon Device Structures

areas are the etch-stop areas. The bridge material is a thermally grown SiO, layer covered by a 20 8, Cr layer, and the bridge is defined by photolithography and etching. The bridge is released by partly etching away the polysilicon spacer with EDP (ethylene diamine pyrocatechol solution). The etched channels are defined by the boron etch-stop mentioned above. The bistable bridge performs the memory function. The two logic levels are defined by the two stable states: the bridge bending upward or downward. The write function corresponds to the switching of the bridge between the two states. Switching to either state is done electrostatically by applying a voltage between the bridge and the substrate or the lateral electrodes. The read function is done by sensing the capacitance between bridge and substrate. Thus, the memory cell is nonvolatile and fully immune to an electromagnetic field, and the stored data can be retained permanently. Switching voltages around 30 V have been achieved; lower voltages are expected. Since the fabrication technology for the bridge is close to a standard MOS process, we expect that the microelectromechanical memory cells can be integrated monolithically with microelectronic read/ write circuits to form a full memory device (Holg, 1990).

We have used a Ge,Si - ,strained layer to fabricate the Si-based MODFET (modulation-doped FET) in which a two-dimensional electron gas is formed at the GeSi-Si heterojunction interface. The layers are grown at an epitaxy temperature of 600 "C on a (100) Si substrate using the Si MBE system. A schematic cross section of the layered structure is shown in Fig. 7-32a. A Geo,25Si,,,5 buffer layer is deposited on a high resistivity (IO4 cm) p-type Si substrate. The subsequent layers consist of an undoped Ge,Sil -,graded layer with x varying from 0.5 to 0 within the 100A width, and, finally, an undoped Si top layer of 100 8,. Source and drain ohmic contacts

SOURCE

DRAIN

Geo.sSio.slOOA

200A UNDOPED

Ge0.25S10.75

Sb DOPING SPIKE

0.2 bm

1 BUFFER LAYER

1OLn.crn

Sb DOPING SPIKE

7.3.5 MODFET In Sect. 7.2 we have considered the Ge,Si -,/Si system. A Ge,Si - ,layer can be grown epitaxially on a Si substrate as a strained layer without interfacial misfit dislocations as long as the thickness of the Ge,Si, -,layer is less than the critical thickness (e.g., for x = 0.2, the critical thickness L , is 1600 A, and for x = 0.5, L , is 140 A).

p o 8 +1ooA

--+-2oooA-

+1ooA+2ooA

I - S I Ge,SII.r G e d l a s GRADED LAYER

I-SI

Gea2sS10.75 BUFFER LAYER

(b) Figure 7-32. (a) Cross section of a GeSi/Si MODFET structure. (b) Band diagram of the n-channel MODFET at thermal equilibrium (after Daembkes et al., 1986).

7.3 Field-Effect Devices

are formed by thermal evaporation of AuSb. The gate is formed by electron-gun evaporation of a Pt/Ti/Au sandwich of 1000 A/IOOO A/1500 8, thickness. The gate length and width are 1.6 and 160 pm, respectively, and the drain-to-source spacing is 5 pm, A schematic band diagram of the nchannel MODFET is shown in Fig. 7-32 b. A 2 DEG is formed in the undoped Si layer adjacent to the Geo,,Sio,, layer. Because of the Ge,Si, --x graded layer we avoid the formation of a second quantum well near the surface. The device shows good FET characteristics with a transconductance of 70 mS/mm. The mobility is 1550 cm2 V - S- near the heterojunction interface. The cutoff frequency is 2.2 GHz. These values are all higher than those of a comparable Si MESFET, indicating the improved transport properties of electrons in the MODFET. Various device optimizations can be made so that the device can have substantially higher transconductance and higher cutoff frequencies. The Si n-channel MODFET can be combined with Si p-channel MODFET to form highperformance Si complementary-logic circuits (Daembkes et al., 1986). A MODFET consisting of p-Geo,,Sio,,/ Ge/Geo,,,Sio,2, with a strain-controlled Ge channel can be fabricated by MBE. A cross section of such a device is shown in Fig. 7-33. A 0.5 pm Geo,,5Sio,25buffer layer is grown on a (100) Ge substrate by MBE. A thin Ge film ( 2 0 0 4 and a thin Ge,,,Si,,, film (150 A) are commensurably grown on the buffer layer. For the doping, Ge atoms are adsorbed on the Geo,,Sio., surface. Finally, a Geo,,Sio., film (150 A) is deposited. The strain at the heterointerface between p-Geo,,Si,,, and Ge is controlled by the Ge,Si,-, buffer layer. By proper choice of x one can maximize the valence-band discontinuity at the heteroin-

' '

371

0.5 p m

Figure 7-33. Cross section of a strain-controlled Gechannel MODFET (after Murakami, 1991).

terface and enable sufficient confinement of the two-dimensional hole gas. The x value is chosen to be 0.75 to give maximum hole mobility. The p-channel MODFET has a ultra-high hole mobility of 9000cm2V-'s-' at 77 K (Murakami, 1991).

7.3.6 Microvacuum Field Emitter One of the major limitations of highspeed semiconductor devices is the carrier velocity saturation due to scattering effects. The carrier velocity in a vacuum, on the other hand, can be substantially higher and is only limited by relativistic effects. Therefore, a microvacuum devices become an important area of study. Figure 7-34a shows a microvacuum triode with molybdenum field-emission cathodes, and a close-spaced Si anode that is made by microfabrication technology. The anodes are fabricated from a (100) p + silicon wafer. A thermal oxide, 2 pm thick, is grown on the wafer. The oxide is then lithographically patterned with 1.25 mm wide lines on 2.5 mm centers parallel to the (1 11) plane. This pattern is transferred by anisotropic etching of Si using KOH to the depth required for emitter-to-anode spacing (up to 20 pm).After dicing, the silicon anode chip is positioned so that the SiO, straddles the emitting area. The anode is

372

7 Silicon Device Structures

- 0

100

200 IVOLTS)

(b) Figure 7-34. (a) Microvacuum triode with closespaced Si anode. (b) Current-voltage characteristics of the microvacuum triode (after Holland et al., 1990).

supported by a layer of SiO, resting on the gate electrode. Electrical contact is made to the back of the Si anode chip, which is coated with TiW. BUILT- ON -ANODE

n* C O N T A C ~ REGION

Figure 7-34b shows a set of currentvoltage characteristics for a triode that has an emitter-to-anode spacing of 8 pm. The measured transconductance is 1 pS for a cathode with 2500 emitters. The average tip current is 4 nA per emitter. The transit time is 4 x s at 60 V. The advantage of the Si anode is that much lower anode voltage is required due to the small anodeto-emitter spacing. However, additional studies are needed to improve the transconductance and the emitter current (Holland et al., 1990). Figure 7-35 shows the cross section of a Si avalanche cold cathode. The device is fabricated on a (100) p-type Si epitaxial wafer (4 Q cm) grown on a p + substrate. The emission current is measured with a stainless steel anode at a distance of 1 mm from the cathode. Standard IC processing, including implantation of B, As, and P, is used to fabricate the cold cathode. The As peak is located at a depth of 120 A, and the junction depth is 300 A. When the device is reverse-biased to avalanche breakdown, the reverse current I increases linearly. The emission current I , also increases approximately linearly with increasing I,. The emission efficiency q is defined as lE/(ID + IE). For a single cathode with a 40 ym diameter, a reverse bias of 6.2 V, and an anode voltage of ..

/ -- 1

:'SHALLOW

' CHANNEL

II II

I / -

p EPILAYER

p' SUBSTRATE

METAL

si02

0si

Figure 7-35. Cross section of a Si avalanche cold cathode device (after Ea, 1990).

7.4 Quantum-Effect Devices

500 V, is 2 x lo-’. The anode voltage can be lowered to 1 V and the emitter efficiency can be increased when the anode is replaced by cantilevered polysilicon beam to be constructed at a distance of 1-2 p from the emitting cathode as shown by the dashed line in Fig. 7.35. Because of the small area (2 x 20 pm2) of the proposed cantilevered polysilicon beam anode, the expected capacitance is a fraction of a picofarad, thus subpicosecond transit-time operation is posible (Ea, 1990).

7.4 Quantum-Effect Devices

well, quantum wire and even quantum dot. For example, a resonant tunneling device was fabricated (Takeda et al., 1990), and the multiple quantum-well structure revealed an excellent infrared detection capability (Kesan et al., 1990). A resonant hotelectron transistor has also been fabricated (Rhee et al, 1989). All these devices will be presented in the following sections.

7.4.2 Quantum Wells, Wires, and Dots In the three-dimensional case, the energy E versus wave vectors k , k can be expressed as

7.4.1 Introduction The quantization effect in field-effect transistors was first observed in a MOSFET in 1966 (Fowler et al., 1966). A twodimensional electron gas (2DEG) in nMOSFET and a two-dimensional hole gas (2DHG) in p-MOSFET are present in the triangular potential well right next to the SiO, -Si interface. Modern lithographic technology can fabricate a MOSFET with a channel length and width of 0.1 pm. For such a small channel, we can find only “one” interface state in the channel, if the interface state density is 10’’ states/cm2. Recently, single-electron trapping was observed. Employing the quantum wire as the channel of a MOSFET, e.g., a MOSFET with a channel length of 1 pm and a channel width of 10 nm, revealed many interesting physical insights (Pepper, 1990). In addition, using resonant tunneling phenomena, different kinds of structures can be made such as the effective-mass filter (Gennser et al., 1990), energy filter (Gennser et al., 1990), and the wave function filter (Rajakarunanayak, 1989), etc. Recent developments in GeSi technology can be employed to fabricate quantum

373

(7-22) where k is the wavevector perpendicular to k l l and m , and m i l are the effective masses in the corresponding directions. However, in a quantum well a standing electron wavefunction is formed. This implies a quantized energy in this direction ( z in real space and k l , in reciprocal space). The wavevector k l l is

kll

1l.t

1=1,2,3, ...

(7-23)

The E - k relation in a band (conduction or valence band) is given by

The low dimensionality can be further reduced to one dimension and to zero dimensions, in which the transverse wavevector k is further quantized. Generally, the density of states (DOS)in d dimensions can be found. The number of states per unit volume in k-space is ( 2 ~ ) ~ , where d = dimensionality. The total number of states 2 in volume I/k(d) in k-space is

(7-25)

374

7 Silicon Device Structures

In a multivalley semiconductor, using 5 , for the valley degeneracy,

The energy-k relation is given by E = -h2(k:- + ” +k “2 2 m, my

k 2 ) =-h 2 k 2 m, 2m

for isotropic effective mass m. Therefore, the DOS per energy E to E+dEis d Z d Z IdE Q ( E )= - = - / dE d k / dk states/( V d *)energy) (7-26)

= 1.587 x

10l1( i ) ( S ) / ( c m ’ m e V )

for (100) Si z 2.8 x 1010/(cm2meV) for GaAs

In a one-dimensional system

For example, in a three-dimensional (3 D) system, a free-electron-like gas has spin

dZ 8nk2 dk ( 2 ~ ) ~ dE h 2 k dk m (2 m E)” h 21Zm32 E12 e 3 D (E) = h3

4 dZ _ dk 5 (7-29)

(7-27)

In 3D, the DOS is proportional to the square root of energy. In a two-dimensional (2 D) system,

h2 kfi =Eo + A 2mll

nzI - -m l (7-28) h2 k x h2 The DOS is independent of energy. ~

In a zero-dimensional (OD) system, the DOS becomes a delta function located at each quantized state. The DOSs of 3D, 2D, 1 D, and OD systems are shown in Fig. 7-36. Realizations of a 2 DEG or 2 D H G in a Si system have been shown previously. However, a quantum-wire-channel MOSFET, shown in Fig. 7-37a, has also been fabricated (Takeda et al., 1990). There are two gates, the first and the second, fabricated by electron-beam lithography. Their widths were both varied from 0.1 pm to 1.0 pm. The channel length from source to drain is approximately 2 km. The second gate, which has a 10 nm gate oxide, creates the narrow conducting channel. In Fig. 7-37 b, the transconductance g,( = aZ,,/aV,,) is found to show oscillatory behavior and negative differential resistance, which implies a resonant transport.

375

7.4 Quantum-Effect Devices FIRST GATE

Q2D

4 i = l

QUANTUM WELL

E,Ei

VS G

-3

-4 v -5v

QUANTUM DOT

4.2 K

E, Ei

Figure 7-36. Density of states in (a) 3 D, (b) 2 D, (c) 1 D, and (d) OD systems.

Figure 7-37. Quantum wire channel MOSFET: (a) device structure; (b) transconductance oscillation in narrow Si inversion layers.

The quantum-dot structure can be fabricated by the following process steps. As shown in Fig. 7-38, thin layers of Si and GeSi are deposited on a Si substrate by MBE or a UHVjCVD process. After a mesa etching, an SiO, layer can be formed by a low-temperature oxidation step such as high-pressure oxidation (HIPOX) or plasma-enhanced chemical vapor deposition (PEVCD). Finally, a narrow metal gate strip is formed on the top oxide. If the dimensions L,, L,, L, are smaller than the

de Broglie wavelength (about 200 8, at 300 K), a quantum dot is formed.

7.4.3 Resonant-Tunneling Diode The quantized states in a double-barrier quantum well (DBQW) are shown at the left in Fig. 7-39. The resonant phenomenon is analogous to the resonant transmission of light through a Fabry-Perot etalon. In DBQW, an electron wave behaves like a light wave.

376

7 Silicon Device Structures

Figure 7-38. Structure of a quantum dot.

(QUANTUM W I R E S )

Consider an electron at energy E incident on the one-dimensional DBQW structure. When E matches one of the energy levels Ei in the QW, the amplitude of the electron de Broglie waves in the QW increases due to multiple scattering, and the waves leaking in both directions cancel the reflected waves and enhance the transmitted ones. Near resonance one has (Luryi, 1990) T ( E )%

.,2 4 TI T2 (7-1 TZ)’ ( E - E;)’

+ ;”

(7-30)

where Tl and T, are the transmission coefficients of the two barriers at the energy E = Ei and 7 z A/? is the lifetime width of the resonant state [quasi-classically, 7 z Ei

(Tl = T2)].In the absence of scattering, a system of two identical barriers ( Tl = T2)is completely transparent to electrons entering at resonant energies and the transmission coefficients, plotted against the incident energy, have a number of sharp peaks, as shown at the right in Fig. 7-39 b. A GeSi/Si double-barrier resonant-tunneling diode (DBRTD) was fabricated (Rhee et al., 1988). Figure 7-40a shows the energy barrier diagram in the valence band. Figure 7-40b is the current-voltage characteristic ( I - V ) in which a resonant tunneling peak can be clearly observed around 300 meV at both 4.2 K and 77 K. The peak is due to the transmission through the light-hole ground state Elhl (higher energy not shown).

0.8 0.6

0.4 w

z Y

c ---jp

t -I+

1ooA

t w

L : - y 5 + ) * 2

GerSi1.x

10-4

10-8

TRANSMISSION COEFFICIENT

5? u

Figure 7-39. Double-barrier resonant-tunneling diode (DBRID): (a) quantized states in the well; (b) transmission coefficient vs. energy E (after Luryi, 1990).

7 . 4 Quantum-Effect Devices

377

index confinement region that permits effective waveguiding in the silicon overlayer. A silicon ridge was used as the waveguide. A multiple quantum well (MQW)layer was imbedded in a p-i-n structure as shown in Fig. 7-41 a. The 40 8, Si,,,Ge,~,/210 8, Si, 28-period layer is equivalent to an average Ge composition of 10%. The response of the detector as a function of wavelength at 10 V reverse bias and at room temperature is shown in Fig. 7-41 b. A 50% internal quantum eficiency was obtained at 1.1 pm wavelength with an impulse response time of 100 ps (Kesan et al., 1990).

-U E

7.4.5 Resonant-Tunneling Hot-Electron Transistor V

DC VOLTAGE (mV)

(b) Figure 7-40. (a) Schematic band diagram of the double-barrier diode. For the structure used in this experiment, W, = W, = 50 A, W, = 40 A, and x = 0.4. (b) Observed current -voltage characteristics for the structure at three different temperatures (after Rhee et al., 1988).

The heavy-hole ground state Ehht can only be seen by dI/dV or d2Z/dV2 measurement because of the large tunneling effective mass. At higher bias a second peak occurred at 900meV in the dZ/dV measurement due to the first excited heavyhole state Ehhl(Rhee et al., 1988).

7.4.4 Multiple Quantum Well Detector The Si-Ge heterostructure makes the realization of a Si-based 1.3 pm long wavelength optoelectronic detector possible. Silicon-on-insulator (SOI) structures are used. The buried-oxide layer forms a low-

When a double-barrier resonant-tunneling diode (DBRTD) is imbedded in a structure, as in p + (Ge,,,Si,,,)-DBRTDP+ (Ge0.5Sio.A base-i (Ge,,,Si,, 8)p + (Geo.,Si0,,), a hot-electron transistor (HET) is formed. The HET exhibits negative differential resistance (NDR) in its current-voltage (I- V) characteristics (Rhee et al., 1989). Because of its high-speed tunneling capability and negative differential resistance, integration of such a device into Si-based circuits could find applications in high-speed digital circuits, frequency multipliers, multistate logic circuits and tunable oscillator/ amplifiers. The HET samples were grown on highly doped p-type (lO0)Si substrates in a Si MBE chamber. Detailed procedures for sample cleaning and growth can be found elsewhere (Rhee et al., 1990). Figure 7-42a shows the structure of the resonant-tunneling hot-electron transistor. A double-barrier structure, which consists of two 50 8, Si layers separated by a 43 8, Ge,,,Si,,, quantum well, is used as an emitter. A 1.2 pm Ge,,,Si,,, buffer layer acts as a collec-

378

7 Silicon Device Structures

UNDOPED Ge.2Si.g 100 nrn

P'-

Ge.4Si.s

1200 nm

COLLECTOR

DETECTOR RESPONSE ( LIGHT WAVEGUIDE) - l O V BIAS

--:: 50

VBC ( m V )

Figure 7-41. (a) Schematic view of a photodetector consisting of an M Q W absorber integrated into a rib waveguide--P--i - N structure showing both device geometry and epitaxial layer structure. (b) Internal quantum efficiency vs. well length for the structure in ( a ) (after Kesan et al.. 1990).

Figure 7-42. The resonant-tunneling hot-electron transistor: (a) cross-sectional view of the GeSi resonant-tunneling hot-hole transistor. (b) Schematic band diagram of the transistor under bias when resonant tunneling occurs through the light-hole ground state in the quantum well. (c) 1 V characteristics (after Rhee et al., 1989).

7.4 Quantum-Effect Devices

tor and the collector barrier consists of a 1000 8, Ge,,,Si,,, layer. A 1000 8, Ge,.,Si,,, base is inserted between the double-barrier quantum-well emitter and the collector barrier. The doping concentration is about 1 x lo1, cm-3 throughout the device except for the collector barrier and the double-barrier resonant-tunneling structure, which are undoped. Substrate temperature was held at about 530 "C during the growth. The emitter and base contacts were obtained using selective wet etching and standard photolithographic techniques. The valence-band offsets and boundstate energy of the light-hole ground state in the quantum well is shown schematically in Fig. 7-42 b. For convenience, the hole energy was taken to be positive. All the values are given with reference to the valence-band edge of the unstrained Ge,,,Si,,, layers. The collector barrier and the resonant-tunneling double barriers in the emitter are subjected to an in-plane tensile strain that causes the heavy-hole band edge to be above the light-hole band edge. In the base, the heavy-hole band edge is below the light-hole band edge due to the compressive strain. In the unstrained Ge,,,Si,., layers, the light-hole and heavyhole bands are degenerate. The light and heavy holes moving from the collector to the base have to overcome 106 meV and 155 meV barriers, respectively. On the other hand, the light and heavy holes see barrier heights of 137 meV and 208 meV, respectively, from the base to the collector. Due to the degenerate light- and heavyhole bands in the collector, the majority of the current from the collector to the base is from light holes because of the lower lighthole barrier height. The effective barrier height from the collector to the base is 106 meV as seen by the light hole and 208 meV from the base to

379

the collector as seen by the heavy hole. An asymmetric I - V characteristic between the base and the collector is evident as a result of the unequal barrier heights. In the double-barrier quantum-well emitter, the barrier heights for the light and heavy holes are 211 meV and 315 meV, respectively. There are three bound states for the heavy hole and one bound state for the light hole in the quantum well. The negative differential resistance of the device is due to the light-hole tunneling through the light-hole ground state located 61 meV from the bottom of the well. Figure 7-42 b shows the band diagram under an external bias. When the emitter is biased positively with respect to the base, holes are injected into the base through the double-barrier resonant-tunneling emitter with an excess hole energy relative to the valence-band maximum of the Ge,,,Si,,, base. The holes injected into the base are then transported near-ballistically to the collector. The 1000 8, Ge,,,Si,,, collector barrier prevents injection of the holes initiated from the valence band of the base to the collector when VB, is applied, but allows transport of the injected hot holes from the emitter to the collector if the hot holes have higher energies than the collector barrier height. In Fig. 7-42c, a set of collector currents (I,) is shown as a function of the base-collector voltage (V,,) at 77 K, with VEB as a parameter. The rightmost curve corresponds to V,, = 0 and the others are obtained for an incremental step of 0.2 V. At VEB= 0, no negative differential resistance (NDR) is observed because a large portion of the collector current comes from the base. As the emitter bias is increased, the injection current from the emitter becomes the dominant source of the collector current and he NDR increases with VEB.

380

7 Silicon Device Structures

7.5 Microwave and Photonic Diodes

ity of Si-based optical sources (Luryi and Sze, 1987). 7.5.1 IMPATT Diode

The most important Si microwave diodes are the IMPATT diode and the BARITT diode. They provide high-power, hight-efficiency, or low-noise operations from 1 GHz to the millimeter-wave band. Although Si tunnel diodes have been made, the device performance is inferior to that of GaAs tunnel diodes due to Si's relatively large effective mass for tunneling. There is no Si transferred-electron diode, because the satellite valley in the Si conduction band is located 1.1 eV above the bottom of the conduction band, too high for intervalley transfer of electrons. Si photonic devices include the Si photodetectors, which detect optical signals through electronic processes, and Si solar cells, which furnish the power for satellites and space vehicles as well as for terrestrial applications. No Si optical sources have been developed yet, because Si has an indirect bandgap. It is conceivable, however, that certain Si-based materials may have direct bandgaps, thus opening the possibil-

[-x

N, 0

The IMPATT (impact ionization avalanche transit time) diode is one of the most powerful solid state sources of microwave power. It can generate the highest CW (continuous wave) power at millimeter-wave frequencies, and is used most extensively in that frequency range (30 to 300 GHz). Si IMPATT diodes are superior to GaAs IMPATT diodes in the millimeterwave frequency range because Si has a smaller energy relaxation time, which results in faster response to impact ionization when an electric field is applied. In addition, Si has a higher thermal conductivity for better heat dissipation. The basic members of the IMPATT diode family are the single-drift devices and the double-drift devices. Figure 7-43 shows the single-drift IMPATT diodes in which only one type of charge carriers (ie., electrons) traverses the drift region. Figure 7-43a shows the doping profile and electric field distribution at the avalanche

b n : 2

o b

em^^^,,^ Em\".k: i:(; x,

(a)

0 XA

(b)

--c

0 XA

(C)

Figure 7-43. Doping profiles and electric-field distributions at the avalanche breakdown condition of three singledrift IMPATT diodes: (a) one-sided abrupt p-n junction, (b) hi- lo structure, and (c) lo-hi-lo structure (after Sze, 1990).

7.5 Microwave and Photonic Diodes

38 1

N. E

),,//IV

; /

W (C)

’ NA

Figure 7-44. Doping profiles and electricfield distribution of four double-drift IMPATT diodes: (a) flat profile, (b) hi-lo structure, (c) lo-hi-lo structure, and (d) hybrid structure (after Sze, 1990).

(d)

breakdown condition of a one-sided abrupt p -n junction. The avalanche multiplication process occurs in a narrow region near the highest field between 0 and x. Figure 7-43 b shows a hi-lo structure in which a high doping Nl region is followed by a lower doping N2 region. With proper choice of the doping Nl and its thickness b, the avalanche region can be confined within the Nl region. Figure 7-43c is the lo-hi-lo structure, in which a “clump” of donor atoms is located at x = b. Since a nearly uniform high-field region exists from x = 0 to x = b, the avalanche region is equal to b, and the maximum field can be much lower than that for the hi-lo structure. Figure 7-44 shows double-drift devices in which both electrons and holes participate in device operation over two separate drift regions. The double-drift devices have higher efficiency and higher output power than single-drift devices. Figure 7-44 a illustrates the doping profile and electricfield distribution of a two-sided abrupt p-n junction. The avalanche region is located near the center of the depletion layer. Fig-

ure 7-44 b shows a double-drift hi-lo structure that consists of a lo-hi structure on the p-side and a hi-lo structure on the n-side. Figure 7-44 c shows a double-drift lo-hi-lo structure, the avalanche region is given by the distance between the p + clump and the n + clump. Figure 7-44d shows the double-drift hybrid structure in which the p side has a flat doping profile but the n side has a hi-lo profile. The selection of a particular device structure depends on many factors, such as the operating frequency, the CD-to-AC conversion efficiency, power output, and ease of fabrication. The double-drift lo-hilo structure (Fig. 7-44c) is expected to have the highest efficiency, but it is also the most difficult to fabricate. The double-drift hybrid structure (Fig. 7-44d) is a good compromise, since it has good efficiency and is relatively easy to make. Of course, the simplest structure is the single-drift p-n junction (Fig. 7-43 a). For lower-frequency operation, Si IMPATT diodes are fabricated using diffusion, chemical vapor deposition, or ion implantation processes to form the n-type

382

7 Silicon Device Structures

and p-type layers. At higher frequencies, especially in the millimeter-wave region, the layer thickness becomes very small. At these frequencies, we must use molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) to control the doping and layer thickness precisely. State-of-the-art Si IMPATT diodes have CW power output of about 10 W at 10 GHz, 1 W at 100 GHz, and about 0.1 W at 200 GHz. The conversion efficiency is a constant value of 15% up to 100GHz, then it decreases to 1 % at 200 GHz (Sze, 1990).

7.5.2 BARITT Diode The BARITT (barrier injection transit time) diode is also capable of operating in the millimeter-wave frequency region with substantially lower noise, but also with lower power output than the IMPATT diode. BARITT diodes are particularly useful for applications in self-mixing oscillators where the minimum detectable signal power level can be 30 dB below that of IMPATT diodes. The BARITT diode is basically a backto-back pair of p-n junctions or metalsemiconductor diodes biased into a reachthrough condition. Figure 7-45 a shows a Si p+-n-p+ structure. When a voltage is applied to the device, one junction is forward biased and the other is reverse biased. When the voltage is above the reachthrough condition, the BARITT diode has the electric field profile shown in Fig. 7-45 b. The point x R corresponds to the potential maximum for minority-carrier (holes in this case) injection; the point x, separates the low-field drift region from the saturation-velocity drift region as shown in Fig. 7-45c.

ELECTRIC FIELD

INJECTION REGION

DRIFT REGION

--I

(b) DRIFT VELOCITY

t u

0 LOW- F IE LD REGION

X R XS

--I

SATURATED +VELOCITY REGION

(C)

Figure 7-45. Device cross section, field distribution, and carrier drift velocity of a BARITT diode (after Sze, 1990).

State-of-the-art Si BARITT diodes have CW power output of 100 mW at 10 GHz, and about 1 mW at 60 GHz. Typical efficiencies are in the range of 0.5 to 2 % (Sze, 1990).

7.5.3 Photodetectors Si photodetectors include the p-i-n photodiode and the avalanche photodiode (e.g., hi-lo or lo-hi-lo structures similar to those shown in Fig. 7-43 b and c). The conventional Si photodetectors are useful in the wavelength range from 0.6 to 0.9 pm, where nearly 100% quantum efficiency (i.e., number of electron-hole pairs generated per incident photon) has been ob-

7.5 Microwave a n d Photonic Diodes

tained from devices with antireflection coatings (Sze, 1981). Recently, many novel Si photodetectors have been designed exhibiting excellent photoresponse from the near-ultraviolet to the far-infrared region In addition, heteroepitaxial technology has been used to form Si-based, monolithic optoelectronic integrated circuits that combine 111-V compound photodetectors and MESFET with Si integrated circuits on a Si substrate. Figure 7-46 a shows a cross-sectional view of a single pixel of a 160 x 244-element focal plane array in which a frontilluminated PtSi Schottky-barrier photodetector is connected with a charge-coupled device (CCD). The photodetector is fabricated on a p-type (100) Si wafer using electron-beam evaporation to deposit a

383

10 8, thick Pt film in an ultrahigh vacuum system and subsequent annealing in situ at 400 "C to form a 20 8, PtSi (the barrier height of PtSi/p-Si is 0.18 eV). An n-type guard ring surrounding the periphery of the silicide is utilized to suppress edge leakage. Electrons generated by illumination are accumulated on the PtSi electrode and are subsequently transferred to the CCD channel. The quantum efficiency, as a function of wavelength, of a photodetector reversebiased to 5 0 V and at 50K is shown in Fig. 7-46 b. For wavelengths 2 1 pm, corresponding to photon energies below the bandgap of Si, the photodetector response is produced by carriers generated by absorption of light in the PtSi film. The quantum efficiency is 3% at 1.5 pm and de-

uv CCD TRANSFER GATE

GUARD RING

BURIED CCD CHANNEL

(a)

L >

100 10

u Z

L LL

0.1

0.01

0.001

2 3 4 5 WAVELENGTH (urn 1

(b)

Figure 7-46. (a) Schematic diagram of a single pixel of a 160 x 244-element PtSi focal-plane array operated in the frontillumination mode. (b) Quantum e n ciency as a function of wavelength (after Tsaur et al., 1990).

384

7 Silicon D e v i c e Structures

creases to 0.01% at 6.3 pm. For shorter wavelengths, the quantum efficiency increases drastically, because the radiation can transmit through the 20A PtSi film and is absorbed by the Si substrate to generate carriers that contribute to the photoresponse. The quantum efficiency is 60% at 0.8 pm, remains essentially constant down to 0.4 pm, and then decreases to 35% at 0.3 pm. Using this photodetector and CCD readout circuitry, very large, highly uniform focal-plane arrays have been demonstrated. Such an array is useful for remote sensing and imaging applications (Tsaur et al., 1990). A Ge,Si -./Si heterojunction internal photoemission detector has been investigated. This Si-based far-infrared photodetector has a quantum efficiency of 3 - 5 % in the 8- 12 pm region. Figure 7-47 a shows the structure of a p+-GeSi/p-Si detector. The device is fabricated on a p-type (100) Si substrate. The p'-GeSi layer is grown in a MBE system with a base pressure of 3 x lo-" Torr. The substrate is heated to 500-600°C and Ge and Si are coevaporated from two electron-gun sources. The GeSi layer thickness ranges from 100 to 4000 A, the Ge composition ranges from 0.2 to 0.4, and the boron doping concentration ranges from i o i 9 to 4 x lozocm-3. The energy band diagram is shown in Fig. 7-47 b. Infrared radiation is absorbed in the p +-GeSi layer, the photoexcited holes are emitted over the GeSi/Si heterojunction barrier into the Si by internal photoemission. Strong infrared absorption is achieved in the p t GeSi layer due to free carrier absorption and intra-valence-band transitions. The heterojunction band alignment for the GeSi/Si system is essentially of type 111, that is, most of the band-edge difference appears at the valence band. By decreasing the Ge composition, we can reduce the valence band offsets AEv, which,

G - e-5-i

i02

(a) Si GeSi VALENCE BAND ,jD IS CONT I NU I T Y

AB so R I N G LAYER

.mp

..................

PHOTO-EXC IT ED HOLES

(b)

400A

40008

-10' >. V

LL LL

lo-' r

f 0

8 1 0 1 2

WAVELENGTH ( p m )

(C)

Figure 7-47. Device structure of a p+-GeSi/p-Si photodetector. (b) Energy band diagram of the photodetector. (c) Quantum efficiency of two GeSi/Si photodetectors as a function of wavelength (after Lin and Maseyian, 1990).

in turn, reduces the heterojunction barrier q # B given by qdB= AEv - (E,, - E ) (in eV) (7-31) The cutoff wavelength iC [1.24/(q #B)] will therefore increase. Figure 7-47c shows the quantum efficiencies of two GeSi/Si photodetectors as a function of wavelength. For both detec-

7.5 Microwave a n d Photonic D i o d e s

tors, the GeSi layers have the same Ge content of 0.3 and the same total quantity of boron, but for detector A, the layer thickness is 400 A, and for detector B, the layer is 10 times thicker. The thinner layer of detector A allows more photoexcited holes to reach the interface before undergoing inelastic scattering, resulting in higher quantum efficiency. In addition, the higher doping concentration of detector A reduces the effective potential barrier because its Fermi level moves further below the valence band, and thus extends the photoresponse to 10 pm. By optimizing the thickness, composition, and doping concentration of the GeSi layer, significantly improved quantum efficiencies are expected (Lin and Maseyian, 1990). Another Si-based photodetector is the InGaAs/InP detector for the 0.9- 1.7 pm wavelength. The detector is fabricated on a Si substrate by a heteroepitaxial process. This approach allows monolithic integration of photonic and electronic devices on a single Si substrate. Figure 7-48 shows the cross section of the photodetector. A Si wafer (4" off (100) orientation) with a GaAs layer grown by the MOCVD process serves as the starting material. The hydride vapor-phase epitaxial technique is used to deposit seven 1 pmthick In,Ga, -,As layers with x ranging from 0.07 to 0.49 in equal steps to accommodate the 3.8% mismatch with GaAs. A final 5 pm thick Ino,53Gao.47As layer is

deposited to serve as the optical absorption layer, followed by a 1 pm thick InP layer, which serves as the high-bandgap passivation "window" layer. Planar p-i-n photodetectors with 75 pm diameter are then fabricated by conventional processes using Zn diffusion. For a reverse bias of 5 V, the quantum efficiency at 1.3 pm is 85% and the capacitance is 1.1 pF. The detectors have been life-tested at 125 "C and - 5 V. No increase in room temperature dark current has been observed after 2000 h, indicating that the detectors are quite reliable (Olsen, 1990). 7.5.4 Solar Cells

There have been dramatic increases in the Si solar cells' conversion efficiency in the past few years. Most of these increases have originated from improved cell structures and processing techniques, rather than improved Si quality. Figure 7-49a shows a schematic diagram of a passivated emitter and rear cell, which shows a high efficiency of 23.1 YOunder AM 1.5 spectrum (i,e., an air mass 1.5 condition with the sun at 45" above the horizon; these conditions are an energy-weighted average for terrestrial applications). We note that the cell structure is quite different from that of the conventional solar cell. The front side has an invertedpyramid surface texture to trap the incident light. A heavy n + diffusion under-

Si3Nq DIELECTRIC (0.10 urn) n- PASSIVATION LAYER(lnP-1.0~lrn) Zn DIFFUSION n-OPTICAL ABSORPTION LAYER (ln0.53Go0.47Ar-5.0~m) STEP GRADED REGION 7- 1 urn THICK- InxGol-x As LAYERS ( XI

n+ < l o o > S i SUBSTRATE

385

0.07-0.49)

n+- BUFFER LAYER (GaAs-2.01~rnI n-SEED LAYER (GoAs-6OAl

Figure 7-48. In,,,Ga,,,,As/ InP compositionally graded photodetector on a Si substrate (after Olsen, 1990).

386

7 Silicon Device Structures "I NVE RTED " PYRAMIDS

FINGER

REAR CONTACT

OXIDE

(a) METAL

INVERTED PYRAMIDS

(b)

Figure 7-49. (a) Schematic diagram of a passivated emitter and rear cell (after Green, 1990).(b) Schematic diagram of a solar cell with 26% efficiency at the 90 sun, AM 1.5 condition (after Cuevas et al., 1990).

neath the top metal contact helps to minimize series resistance and increase opencircuit voltage. The top surface oxide is 250 A thick, and a MgFJZnS double-layer antireflection coating (not shown) is applied. O n the bottom surface, a thermally grown oxide passivates most of the surface. Nonalloyed ohmic contact is made at isolated contact holes through the passivating oxide. In order to have a low contact resistance, relatively low-resistivity Si should be used (e.g., e = 0.2 R cm). The cell thus incorporates a highly reflective planar rear surface. The calculated reflectance of this layer is above 97% (Green, 1990). Figure 7-49 b shows a similar cell with efficieny of 21.7% at 1 sun (AM 1.5 condi-

tion) and 26% at 90 suns concentrated light, 25"C, AM 1.5 condition. The cell consists of an undoped (or moderately doped n-type) substrate with imbedded point p f and n + islands. The SiO, used to mask the boron and phosphorus diffusions passivates the undoped surface and also acts as an antireflection coating. The percentage of silicon area that is contacted is 1 YOfor the p + and 2 % for the n + materials. The metal grid is arranged in a chevron pattern that aligns on the triangular ridges (Cuevas et al., 1990). Progress has also been made on a polycrystalline Si solar cell. Efficiency as high as 17.8% has been obtained under a 1 sun AM 1.5 condition. A passivated-emitter solar cell is shown in Fig. 7-50. The cell incorporates two novel treatments. The first is the phosphorus pretreatment in which phosphorus is diffused into the polycrystalline silicon. The enhanced diffusion of phosphorus along the crystallographically poor regions (grain boundaries) converts areas which would otherwise be minority carrier sinks into useful collection regions. The second is the rear aluminum treatment. Aluminum, like phosphorus, is also found to exhibit enhanced diffusion D O U B L E LAYER AR COATING TOP CONTACT ( T i / P d / A g 1

'REAR CONTACT Figure 7-50. A passivated-emitter polysilicon solar cell with anti-reflection (AR) coating (after Narayanan et al., 1990).

387

7.6 Outlook

along grain boundaries. The aluminum treatment can increase both the open-circuit voltage and short-circuit current. These treatments in gettering the substrate and nullifying the deleterious effects of grain boundaries have improved the performance of the less expensive polysilicon solar cell to nearly match that of singlecrystal devices. Using a surface-texturing approach similar to that shown in Fig. 7-49 may further increase the efficiency (Narayanan et al., 1990).

7.6 Outlook As the technology of microelectronics advances, the feature size becomes smaller. Figure 7-51 shows that, in the year 2000, the MOSFET’s gate length may be reduced to 0.2 pm, gate-oxide thickness to 4nm, and junction depth to 0.04pm. Simultaneously, bipolar transistors that have a base width of 50 nm in 1990 may be reduced to 30 nm in the year 2000 by using a heterojunction GeSi approach. Consequently, cost and performance improvement will be tremendous. In 2000,256 Mbit (- 3 x lo8 components/chip) DRAM will be available with a gate delay of only 30 ps,

Table 7-1. Peformance projection. Year

Minimum feature length (P) Component density (devices/cm2) Gate delay (ns) Power-delay product (pJ) Wafer size (mm)

1960

1991

2000

0.7

0.2

500 loo00 25

8 x 1 0 6 0.03

0.1 0.01

200

0.03 0.0003 250

compared to 500 ns in 1960. Power-delay products will also profoundly improve from 10000 pJ in 1960 to 0.0003 pJ by the year 2000. These projections are summarized in Table 7-1. Figure 7-52 shows the evolution of circuit complexity versus year. MOSFET has the highest complexity. Bipolar still maintains its momentum but levels off after 1990. MESFETs and MODFETs are still in their development stage, however, their momenta are extremely high - high enough to challenge MOSFETs in the future. A combination of the high complexity of Si-based devices with the high-speed capability of GaAs devices will create new system applications for the future computer,

30 10

rn W

z s 0 I c-

’

1oooA

0.1

z z 5

0.01

-1 ( - 1 3 % R E DI U C T I O N

0.004 1960

1970

PER I 1980

YEAR

1008 L.-O 8

1990

2000

Figure 7-51. Dimension scaling of MOSFETs and bipolar junction transistors vs. time.

388

7 Silicon Device Structures

VLSI

BIPOLAR .... TRANSISTOR MESFET

MODFET U

10'

...:

1960

I 1970

I 1980

I 1990

2000

2010

YEAR Figure 7-52. Evolution of VLSI circuit complexity.

communication, and high-quality entertainment equipment such as high-definition television (HDTV), which may use heteroepitaxy of GaAs on Si technology. O n the other hand, work on GeSi strained layers on Si is attracting a lot of attention. Using narrower bandgap GeSi material for the base of bipolar transistors makes the device speed competitive with that of heteroepitaxy of GaAs on Si. A commensurate GeSi layer on Si is much more suitable to realize the heterojunction bipolar transistor, which will have an extraordinary impact on both Si and GaAs technologies. In order to mass produce these devices beyond the year 2000, low-temperature process technologies are required. Otherwise, the diffusion of the constituent materials will seriously affect device performance, especially when the channel length of MOSFETs is reduced to 0.1 pm and the base width of bipolar transistors is reduced to 30nm. The growth of Si or GeSi epitaxially at a temperature lower than 550 "C has already been achieved (Meyerson, 1986). Deposition temperatures for poly-Si or poly-SiGe,

oxide, nitride, and even the annealing temperature should be lowered accordingly, preferrably to below 800 "C. Table 7-2 presents the possible low-temperature processes for future ultra-large-scale integration (ULSI). Therefore, there are callenges to many professionals including the physicist, chemist, materials scientist, and electronics and device engineer to work together towards solutions. Advances in Si technology such as Si micromachining have created many new applications, which include microvacuum and micro-electromechanical systems (Fan et al., 1989). New sensors, transducers, actuators, and even new kinds of field-emission devices such as field-emission displays (Spindt, 1989) and high-power distributed microwave vacuum triode arrays using field-emission types have been developed (Kosmahl, 1989). We anticipate that Sibased devices will remain the dominant semiconductor devices in the foreseeable future.

Table 7-2. Possible low temperature technologies for future ULSI circuits.

Feature

Technology"

Epitaxial or poly Si. UHVjCVD, MBE, LRP, SiGe LPCVD Oxides and interfaces Plasma treatment, UV ozone, Hipox Nitrides CVD-PECVD, photo-CVD, LPCVD, Metals (and silicates) Sputtering CVD Contacts Non-alloy, LT-EPI, with RTA Junctions TRP, RTA, LT-EPI Abbreviations: UHV, ultra-high vacuum; CVD, chemical vapor deposition; MBE, molecular beam epitaxy; LPR, limited reaction process; LPCVD, low pressure chemical vapor deposition; UV, ultraviolet; HIPOX, high-pressure oxidation; PECVD, plasma-enhanced chemical vapor deposition; LT, low temperature; EPI, epitaxy; RTA, rapid thermal annealing; RTP, rapid thermal processing.

7.8 References

7.7 Acknowledgements This Chapter is dedicated to the memory of Mrs. Cheng-Hwei Wu Chang, C. Y. Chang's wife, who passed away during our writing of the manuscript. We wish to thank Mr. N. Erdos who did the technical editing of the Chapter, Ms. B. L. Huang who typed the initial draft and the final manuscript, and Mr. T. Z. Jung who furnished the technical illustrations.

7.8 References Allyn, C. L., Gossard, A. C., Bethea, C. G., Levine, B. E (1980), Appl. Phys. Lett. 36, 373. Aoki, M., Ishii, T., Yashimura, T. (1990), IEEE Int. Electron Device Mtg. Tech. Digest, pp. 939-941. Bean, J. C. (1978), Appl. Phys. Lett. 33, 654. Brews, J. R. (1990), in: High Speed Semiconductor Devices: Sze, S . M. (Ed.). New York: Wiley, pp. 139-210. Chang, C. Y, Luryi, S., Sze, S. M. (1986), IEEE Electron Device Lett. 7, 497. Chen, T. C., Toh, K. Y., Cressler, J. D. (1989), IEEE Electron Device Lett. 10, 344. Chiu, T. Y., Chin, G. M., Lan, M. Y (1991), IEEE Trans. Electron Devices 38, 141. Cuevas, A., Sinton, R. A., Midkiff, N. E. (1990), IEEE Electron Device Lett. 11, 6. Daembkes, H., Herzog, H. J., Jorke, H. (1986), IEEE Trans. Electron Devices 33, 633. Ea, J. Y (1990), IEEE Electron Device Lett. 11, 403. Fan, L. S . , Tai, Y. C., Muller, R. S. (1989), IEEE Trans. Electron Devices 35, 724. Fowler, A. B., Fang, E F., Howard, W. E., Stiles, P. J. (1966), Phys. Rev. Lett. 16, 901. Garone, P. M., Venkataraman, V., Sturm, J. C. (1990), IEEE Int. Electron Device Mtg Tech. Digest, pp. 383-386, 587-590. Gennser, U., Kesan, V. P., Iyer, S. S., Bucelot, T. J., Yang, E. S. (1990), .I Vac. Sci. Tech. B8, 210. Gibbons, J. F., Gronet, C. M., Williams, K. E. (1985), Appl. Phys. Lett. 47, 721. Grabbe, E. E, Patton, G. L., Stork, J. (1990), IEDM 17. Green, M. A. (1990), IEEE Trans. Electron Devices 37, 331. Grinberg, A. A., Luryi, S. (1981), Appl. Phys. Lett. 38, 810.

389

Holg, B. (1990), IEEE Trans. Electron Devices 37, 2230. Holland, C. E., Rosengreen, A., Spindt, C. A. (1990), IEEE Int. Electron Device Mtg. Tech. Digest, pp, 977-982. Jwo, S. C., Chang, C. Y (1986), IEEE Electron Device Lett. 7 , 689. Kasper, E. C., Bean, J. C. (1989), Silicon Molecular Beam Epitaxy. Boca Raton, FL: CRC Press, Chaps. 2, 4. Kazarinov, R. E, Luryi, S. (1982), Appl. Phys. A 38, 15. Kesan, V. P., May, P. G., Bassous, E., Iyer, S. S. (1990), IEDM. Kosmahl, H. G. (1989), IEEE Trans. Electron Devices 36, 2728. Laska, T., Miller, G. (1990), IEDM, 807. Lattes, A. L., Munroe, S. C., Seaver, M. M. (1991), IEEE Electron Device Lett. 12. 104. Libsch, E R., White M. H. (1990), Solid-State Electron 33, 105. Lin, T. L., Maseyian, J. (1990), Appl. Phys. Lett. 57, 1422. Liu, H. C., Landhear, M., Buchanan, M., Hougton, D. C. (1988), Appl. Phys. Lett. 52, 1809. Luryi, S. (1985), Physica 134B, 466. Luryi, S., (1990), in: High Speed Semiconductor Devices; Sze, S. M. (Ed.). New York: Wiley. Luryi, S., Sze, S. M. (1987), in: Silicon Molecular Beam Epitaxy: Kasper, E., Bean, J. C. (Eds.). CRC Uniscience, pp. 251 -288. Malik, R. J., Aucoin, T. R., Board, K., Wood, C. E. C., Eastman, L. E (1980), Electron. Lett. f0,836. Meindl, J. D. (1984), IEEE Trans. Electron Devices 31, 1555. Meyerson, B. S. (1986), Appl. Phys. Lett. 48, 797. Meyerson, B. S., et al. (1990), IEEE Int. Electron. Device Mtg. Tech. Digest. p. 21. Murakami, E. (1991), IEEE Electron Device Lett. 12, 71. Narayanan, S . , Wenham, S. R., Green, M . A. (1990), IEEE Trans. Electron Devices 37, 382. Okazaki, Y., Kobayashi, T., Miyake, M. ( I 990), IEEE Electron Device Lett. 11 ( 4 ) , 134. Olsen, G. H. (1990), IEEE Int. Electron. Device Mtg. Tech. Digest, pp. 145-147. Pearce, C. W. (1988), in: VLSI Technology: Sze, S. M. (Ed.). New York: McGraw-Hill, pp. 9-45. People, R (1985), Appl. Phys. Lett. 47, 322. People, R., Bean, J. C. (1986), Appl. Phys. Lett. 48, 538. Pepper, M. (1990), in: Proc. Int. Electron Devices Symp., EDMS '90. Hsinchu, Taiwan, R.O.C.: NCTU, p. 465. Rajakarunanayak, Y. (1989), Appl. Phys. Lett. 55, 1537. Rathman, D. D., Niblack, W. K. (1988), I E E E M T T S Intl. Microwave Symp. Digest, Vol. 1. Piscataway, NJ: IEEE, pp. 537-540.

390

7 Silicon Device Structures

Rhee. S. S., Park. J. S.. Karunasiri, R. P. G., Ye, Q., Wang. K . L. (1988). Appl. Phj,s. Lett. 53,204. Rhee. S. S.. Chang. G. K.. Carns. T. K., Wang, K. L. (1989). Int. Electron Deyice Mtg., p. 651. Rhee. S. S.. Chang. G. K.. Carns, T. K.. Wang, K. L. (1990). Appl. P/i.rs. Lett. 56. 1061. Shahidi. G.. Davari. B.. Taur. Y., Warnock, J. (1990), in: Proc. IEEE bit. Electron. Device Mtg. Shichijo. H.. Matyi. R. J.. Taddiken, A . H. (1988), IEEE Inrl. Electron Device Mtg. Tech. Digest, pp. 778 - 781. Smith, C. G., Pepper. M . (1989), J. Phys. Condens. Matter 1 , 9035. Spindt. C. A . (1989). IEEE Trans. Electron Devices 36, 225. Suzuki. K.. Najafi. K.. Wise, K . D. (1990). IEEE Truns. Electron. Deviws 37, 1852. Sze, S. M. (1981). Ph,rsics of Semiconductor Devices, 2nd ed.. New York: Wiley. Sze. S . M. (1985). Semiconductor Devices: Ph,rsics and Technologj~.New York: Wiley. Sze, S . M. (Ed.) (1990), High Speed Semiconductor Devices. New York: Wiley. p. 425, pp, 521-585. Sze. S. M . (Ed.) (1991). Semiconductor Devices: Pioneering Papers. Singapore: World Scientific. Sze. S . M.. Gibbons. G. (1966). Solid-State Electron, 9 , 831.

Taft. R. E., Plumer, J. D., Iyer, S. S. (1989), Int. Electron Dei'ice Mtg., p. 55. Takeda. E. (1990), IEEE Int. Electron. Device Mtg. Tech. Digest, p. 389. Tsaur. B. Y.. Chen, C . K., Mattia, J. P. (1990), IEEE Electron Dei,ice Lett. 11, 162. Turner,G. W.(1988). Proc. Mat. Res. Soc.Symp. 116. 179. Yamauchi. N., Hajjar, J. J., Reif, R. (1991), IEEE Truns. Electron Devices 38, 55. Yang. E. S. (1988), in: Microelectronic Devices. New York: McGraw-Hill.

General Reading Sze, S. M. (1981). Physics of Semiconductor Devices, 2nd ed. New York: Wiley Sze, S. M. (1985), Semiconductor Devices: Physics and Technology. New York: Wiley. Sze, S. M. (Ed.) (1990), High Speed Semiconductor Devices. New York: Wiley, p. 425, pp. 521-585. Sze, S. M. (Ed.) (1991), Semiconductor Devices: Pioneering Papers. Singapore: World Scientific. Yang, E. S. (1988), Microelectronic Devices. New York: McGraw-Hill.

8 Compound Semiconductor Device Structures William E. Stanchina and Juan E Lam Hughes Research Laboratories. Malibu. CA. U.S.A.

List of 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.5 8.6 8.6.1 8.6.2 8.6.3 8.7

Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Material Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Group 111-V Materials Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field-Effect Transistors (FETs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metal-Semiconductor FETs (MESFETs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Heterostructure FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Electron Mobility Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Heterojunction Bipolar Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Novel Semiconductor Laser Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Cascade Semiconductor Laser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Blue-Green Semiconductor Diode Laser . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

392 394 394 396 397 398 400 400 402 404 404 405 405 406

392

8 Compound Semiconductor Device Structures

List of Symbols and Abbreviations channel depth baseicollector junction capacitance drain-to-channel capacitance drain-to-gate capacitance drain-to-source capacitance emitter/base junction capacitance gate-to-source capacitance electron/minority carrier diffusion coefficient band gap energy difference between band gaps difference in valence band energies frequency unity gain cutoff frequency; current gain-bandwidth product minimum noise figure transconductance current drain current channel electron current saturated drain current collector current density Boltzmann constant position in Brillouin zone gate length heavy-hole mass free-electron mass electron mass in r valley n-type doping concentration n-type doping concentration in HBT emitter effective density of states in the conduction band doping concentration in channel sheet charge in 2-DEG effective density of states in the valence band pressure p-type doping concentration in the narrow band gap base electronic charge collector resistance drain resistance emitter resistance gate resistance intrinsic resistance source resistance drain-to-source resistance temperature

List of Symbols and Abbreviations

V VP us

vb e VdS, VDS

VGS vnb

‘pe

K Pmax

E EO

Pn ‘b ‘C ‘CC

‘e, ‘e,

BJT CW

2-DEG FET HB HBT HEMT HFET HIGFET IC JFET LEC LED LPE MBE MESFET M MIC MODFET MOVPE PHEMT rf SISFET

voltage pinch-off voltage saturated free carrier velocity base-to-emi tter voltage drain-to-source bias gate-to-source bias electron velocity across the base hole velocity across the emitter width of the channel base width space charge width in the collector maximum common emitter current gain center of Brillouin zone dielectric constant permittivity of free space free carrier mobility in the channel base transit time collector transit time collector charging time emitter-to-collector transit time emitter charging time bipolar junction transistor continuous wave two-dimensional electron gas field-effect transistor horizontal Bridgman heterojunction bipolar transistor high electron mobility transistor heterostructure FET heterostructure insulated gate FET integrated circuit junction field-effect transistor liquid encapsulated Czochralski light emitting diode liquid phase epitaxy molecular beam epitaxy metal-semiconductor field-effect transistor monolithic microwave-integrated circuit modulation-doped FET metal-organic vapor phase epitaxy pseudomorphic HEMT radiofrequency heterostructure FET

393

394

8 Compound Semiconductor Device Structures

8.1 Introduction The vision of a 21st century society based on an information superhighway infrastructure is synergistic with an extensive, worldwide R&D effort in optoelectronic devices and systems. The future needs of commercial and military services for real-time access to information at a high data rate ( > 10 Gbs- ’) have pushed the semiconductor technology frontier towards devices that can accommodate faster and faster processing rates without deterioration of the quality and quantity of information. In view of the timeliness of this research and technology upsurge, this chapter provides a description of up-todate optoelectronic and electronic devices which may be of practical interest to researchers and engineers in the fields of optical communication, satellite communication, wireless communication, and information systems. Due to the limited scope of this review article, we will concentrate on some of the most recent developments in the field at the expense of other equally important contributions in optoelectronics and semiconductor technology. Compound semiconductors, while covering a very broad range of binary, ternary, and quaternary materials, will be limited in this discussion to the group III-V semiconducting compounds. These refer more specifically, and for the most part, to GaAs and InP and those compounds that can be grown on these binary semiconductor substrates. Compound semiconductor device structures developed to date have generally been intended for application in very high speed electronic systems (taking advantage of the superior electronic transport properties of III-V semiconductors over Si) and in optical or optoelectronic systems (taking advantage of the direct band gaps of these

semiconductors over a wavelength range of 0.6-3.5 pm). These devices have begun to dispel the common notion among their detractors that “they are the materials of the future and always will be”. Probably the most ubiquitous of these is the AlGaAsIGaAs red light emitting diode (LED), which is widely used in displays; however, the semiconductor laser, currently being utilized in long haul fiber optic communication links, pump sources for solid-state lasers, and digital audio discs, is a close second. The GaAs metal-semiconductor field-effect transistor (MESFET) is also gaining acceptance through commercially built integrated circuits that act as improved performance replacement parts for selected Si integrated circuits (ICs), and they have long held a highly regarded position in hybrid and monolithic microwave integrated circuit applications. As these and other III-V devices build a history in terms of reliability and diminishing cost and new improved versions become available, III-V compound semiconductors will inevitably grow in use.

8.2 Key Material Properties Group III-V compound semiconductors have excellent transport and optical

properties, and they include a wide range of crystallographically lattice-matched and strained compounds which enable the development of improved and new device structures through “band gap engineering”. Many of these compounds are shown graphically in Fig. 8-1 in terms of their crystallographic lattice constant vs. the energy band gap. While only the binary compounds are labeled, ternary and quaternary compounds lie on the solid and dotted lines with compositions proportional to

395

8.2 Key Material Properties

Figure &1. Energy band gap vs. lattice constant for major 111-V compound semiconductors. Shaded vertical bands highlight groups of compound semiconductors with approximately the same lattice constant. 5.4

5.6

5.8 6.0 6.2 LATTICE CONSTANT (A)

6.4

their locations relative to the binary compounds terminating those line segments. The solid lines represent compounds with direct band gaps, while the dotted lines correspond to indirect band gap compositions. Shown in Table 8-1 is a selection of generally accepted physical constants for some of the more common direct band gap 111-V semiconductors. Not shown, but of equal importance, are the bulk resistivities in

6.6

excess of 1 x 10' a-cm for semi-insulating GaAs and InP substrates. This property has been a key factor in the rise of high speed 111-V ICs, since it enables devices to be electrically isolated from one another in a simple fashion and since it allows the substrate to serve as a dielectric for stripline waveguides at microwave frequencies. While each material's physical properties show distinctly advantageous features, 111-V devices can obtain enhanced perfor-

Table 8-1. Physical constants of group 111-V semiconductors. Properties

Units

GaAs

Al,,,Ga,,,As

InP

Gao,,,In,,,,As

Al~,481no,5zAsInAs

GaSb

~~~~

Energy gap (25 "C) Conduction band energy (T-L)difference Electron effective mass

eV eV

1.35

0.73

0.40

0.55

0.092

0.077

0.044

0.62

0.66

0.51

0.45

4.1

6.9

2.3

9.7

8.2

1.44 0.31

1.81

0.067

1.45

0.35

0.72

1.35 0.075

0.023

0.042

(mr /ma 1

Hole effective mass

0.32

(mhhim,)

Conduction band density of states Valence band density of states Electron saturation velocity at 100 kVcm-' (25 "Cj Peak electron velocity Electron mobility (25 "C) Hole mobility (25 "Cj Static dielectric constant Thermal conductivity

14 0.83

15 0.86

2.7

6.6

8500

3000

4500

12000

1500

33000

4ooo

450

100

150

450

400

650

12.6

Wcm-I K-'

1.1

2.2

6.6

0.46

11.8 0.70

12.4

14.6

0.26

15.7 0.35

396

8 Compound Semiconductor Device Structures

mance by combining two or more of these semiconductor compounds in the same device. This has led to the technique of “band gap engineering” - the utilization of two or more semiconductor materials (having different energy band gaps) in the same structure to create new devices, enhance, or adjust the performance of existing device types. The interface between any two differing semiconductors is called a heterointerface (or heterojunction if the interface also includes a change in the doping type). These multilayers are then called heterostrucrures.

8.3 Group 111-V Materials Preparation Heterostructure devices are possible due to the development and refinement over the past 20 years of various epitaxial growth techniques, which include molecular beam epitaxy (MBE), metal-organic vapor phase epitaxy (MOVPE), and liquid phase epitaxy (LPE). hom*ojunction devices, too, are quite often grown by these epitaxial techniques with the most notable exception being the ion-implanted metal-semiconductor field-effect transistor (MESFET). Epitaxial growth involves the deposition of semiconductor constituent atoms on a smooth, single crystal substrate under conditions such that the deposited material nucleates, coalesces, and grows into a smooth, single crystal layer lattice matched to the substrate. Semi-insulating substrates are commonly grown as bulk ingots by the liquid encapsulated Czochralski (LEC), horizontal Bridgman (HB), or gradient freeze techniques (AuCoin and Savage, 1985). The ingots are sawed, lapped, and polished to form 50mm, 75mm, 100mm, or even

150 mm diameter wafers with a final thickness of 400-700 pm. Molecular beam epitaxy (MBE) (Arthur, 1968) is a growth technique in an < 10-l’ Torr ultra-high vacuum [Pbackground (1.33 x Nm-2)andPg,o,,,<10-5Torr (1.33 x N m - 2 ) ] ; the source materials are held in high temperature crucibles with small orifices (Knudsen cells). This enables the source materials to form streams of atoms or molecules that effuse from the furnaces. With the furnaces pointed generally upward toward a hot, single crystal substrate, the atomic or molecular beams stream with very few collisions with one another or with the residual gases. Upon striking the hot substrate, the atoms nucleate, diffuse, and form epitaxial layers. (See also Chap. 3, Sec. 3.5 of this Volume.) Metal-organic vapor phase epitaxy (MOVPE) is significantly different from MBE in that the semiconductor constituents are delivered to a hot, single crystal substrate by metal-organic gases (containing group 111 elements and dopants) and arsine or phosphine in a hydrogen carrier gas to provide group V elements. The ambient may be at either atmospheric pressure or low pressure, such that the gases behave in the viscous flow regime over the substrate. The source gases decompose on contact with the hot substrate, leaving behind the group I11 and group V elements along with the dopant elements (generally Zn and Si). (See also Chap. 3, Sec. 3.6.4 of this Volume.) Liquid phase epitaxy (LPE) was the technique used for the first heterostructure lasers in 1970 (Shen and Hartman, 1985). As applied to GaAs, for example, a GaAs substrate covered by a bath of molten G a dissolves until the molten solution is saturated with GaAs and the necessary dopant at some high temperature, e.g., 750 ”C. This molten bath is then removed from the

8.4 Field-Effect Transistors (FETs)

“supply” wafer and placed over a second GaAs substrate wafer which will serve as the seed or nucleation wafer for the epitaxial layers. The temperature is then lowered (e.g., to 725 “C),so that the solution is now supersaturated. Under these conditions, the GaAs begins to precipitate out of the solution and nucleate and grow epitaxially on the substrate. (See also Chap. 3, Sec. 3.4 of this Volume.) Ion implantation is another material preparation technique. However, it is not used to grow single crystal epitaxial layers, but is used rather to implant high energy dopant ions into single crystal substrates. The transfer of energy from the incident ions to crystal atoms knocks the latter from their normal equilibrium crystalline lattice sites. Upon high temperature annealing, this lattice damage is removed and the implanted ions dope the semiconductor while residing as substitutional atoms. This process, when used with selective area patterning by photoresist, can create very localized regions with high or low doping levels or even p/n junctions surrounded by a sea of semi-insulating material.

8.4 Field-Effect Transistors (FETs) Group III-V compound semiconductors have utilized a wide variety of structures to fabricate lateral field-effect transistors (FETs), the most common being the metal-semiconductor FET or MESFET. This transistor, first proposed in 1966 (Mead, 1966) and demonstrated in 1967 (Hooper and Lehrer, 1967), utilizes a Schottky barrier surface potential (“gate”) to modulate the conductivity of a typically n-type “channel” near the semiconductor surface between the electron “source” and “drain” ohmic contacts. This structure was a modification to the basic junction field-

397

effect transistor (JFET) proposed earlier (Shockley, 1952), which uses a reversed biased pn junction formed between a p-type semiconductor gate region and the n-type semiconductor channel. The basic advantage offered by the MESFET was its simpler fabrication with a metal gate and a lower gate capacitance. Later attempts at metal-insulator-semiconductor FETs in III-V semiconductors have been largely unsuccessful owing to the lack of a stable insulator with a low surface state density at the insulator/semiconductor interface, analogous to SiO,/Si. Sophisticated epitaxial growth capabilities such as MBE and MOVPE have given rise to advanced FET structures beyond the MESFET. In heterostructure FETs known as HFETs, HIGFETs, or SISFETs, wider-band-gap lattice-matched semiconductors form the FET gate, which has a larger surface potential barrier than the MESFET. Another advanced structure, which is rapidly gaining broad acceptance and utilization, is the high electron mobility transistor (HEMT), which utilizes a quantum well to create a two-dimensional electron gas channel free of ionized dopant atoms. This transistor structure, also known as the modulation-doped field-effect transistor (MODFET), utilizes a wider band gap semiconductor to create the quantum well, fill the well with free carriers, and enhance the gate potential. The bulk of the following FET discussion will focus on the MESFET and HEMT structures owing to their apparent performance advantages and common use in today’s high speed electronics. Many electronics applications are involved with microwave frequency communications, such as wireless communications, satellite communications, millimeter-wave electronics for satellite communications, and automotive collision warning systems.

398

8 Compound Semiconductor Device Structures

8.4.1 Metal-Semiconductor FETs

(MESFETs) Metal-semiconductor field-effect transistors fabricated from GaAs led the way for 111-V semiconductors and varied applications for high speed electronics. One of the earliest applications of GaAs devices was the use of MESFETs as low noise amplifiers in microwave frequency receivers (Mendel, 1981).The very high electron mobility of GaAs was the key feature leading to the success of this device. The same high frequency capability of GaAs also led to the use of MESFETs as subnanosecond switches useful in monolithic digital ICs (van Tuyl and Liechti, 1977). Today, MESFETs form the core of high speed electronics used in monolithic microwave integrated circuits (MMICs) for radar systems (Brehm, 1990; Bahl et al., 1990) and wireless communication products, and are used in high speed digital circuits for high bit rate communication systems. The MESFET structure is quite simple in its basic form, as shown in Fig. 8-2. The semiconductor structure has usually been formed in the semi-insulating GaAs substrate by ion implantation of '*Si+ at an

Figure 8-2. Structure of a GaAs rnetal-semiconductor field-effect transistor (MESFET).

energy and dose sufficient to form a channel with an approximate depth (a) of 100200 nm from the substrate surface. Higher energy, higher dose implants have been used to form deeper, more heavily doped regions for the source and drain ohmic contacts. After implantation, these implants must be annealed at temperatures of 850°C and above in either a furnace or a rapid thermal annealing system, with either a dielectric encapsulant or arsenic overpressure to prevent the GaAs from decomposing. Source and drain ohmic contacts are typically made from AuGe/Ni formed by evaporation and lift off with subsequent alloying. At this stage the MESFET is ready for fine tuning to adjust the threshold voltage (V,) at which the channel electron current (IDs)would pinch off for a depletion-mode MESFET or turn on for an enhancement-mode MESFET. V, can be calculated from the simple relationship (Puce1 et al., 1975) 2E0

where q is the electronic charge (1.60 x lo-'' C), N D the doping concentration in the channel, c0 the permittivity of free F m - I ) , and E the space ( 8 . 8 5 lo-'' ~ dielectric constant for the channel semiconductor. V, is actually adjusted by etching a recess between the source and the drain. This varies the channel thickness, a (mentioned above and shown in the calculation for V,). Thus V, is a function of the fabrication variables, channel doping, and channel thickness. After the recess is completed, the gate metal is deposited by an evaporation and selective area photoresist lift off process. Generally, todays 111-V FETs utilize submicrometer gate length dimensions ( L J . These can vary from 0.7 pm for large digital ICs down to 0.1 pm for low noise devices. The larger dimensions are

399

8.4 Field-Effect Transistors (FETs) ,

0.6

VGS

-I

= 0.2

figures of merit for the MESFET. They are expressed as (Eden, 1982) Sm=

&Us w 7

(8-4)

when the carrier drift velocity is equal to the saturated velocity and

VDS (VOLTS)

Figure 8-3. Typical current-voltage (I- V )curves for a depletion mode GaAs MESFET.

formed by optical lithography, while dimensions below 0.5 pm are usually patterned by direct write electron beam lithography. Figure 8-3 shows a typical set of current-voltage curves for a depletion-mode GaAs MESFET where the Schottky barrier height is 0.8 eV. This should help to visualize the following MESFET parameters. I,, at a gate-to-source bias ( VGs)near V, is given by (Eden, 1982)

When V,, is nearer pinch-off, the respective equations are

(8-7) In this latter expression, C,, is the gate-tosource capacitance. Many of the above-mentioned physical and equivalent circuit parameters can been seen superimposed on an FET cross section in Fig. 8-4.Typical values for a low-noise GaAs MESFET are shown in Table 8-2. The noise figure is defined as the ratio of the available signal-to-noise ratio at the

where pn is the free carrier mobility in the channel, W the width of the channel, and L , the gate length (i.e., the short dimension of the gate measured in the direction of a vector from the source to the drain). With VGs=O, the drain current I , is known as the saturated drain current, ISAT, and is given by (Puce1 et al., 1975) I S A T = q v s ND

-t

Lg+

~OURCE

(8-3)

where v, is the saturated free carrier velocity. The transconductance (gm), defined as - 6 ZDS/8V,, at a fixed V,,, and the current gain-bandwidth product (fT) are common

SEMI-INSULATING SUBSTRATE

DRAIN^

II I/

Figure 8-4.Equivalent circuit model for a MESFET and the associated physical interpretation for each of the circuit elements.

400

8 Compound Semiconductor Device Structures

Table 8-2. Equivalent circuit parameters for a typical low noise GaAs FET”. Structure

Intrinsic circuit elements

Operating conditions

Extrinsic circuit elements

L, = 1 p n W=300pm

gm = 3 0 m S

= 3 ps

v,, = 0 v vgs= 0 v

C, C, C, R, R,,

= 0.4 p F

I,, = 50 rnA

= 0.01 p F = 0.015 p F

= 0.07 p F R, = 2 R R, = 5 R R, = 5 R

=3R = 500

Pengelly (1986).

input of a two-port network to that at the network’s output, and the minimum noise is commonly used to characterfigure (Fmin) ize the noise properties of FETs. A popular semi-empirical noise model first proposed by f*ckui (1979) describes the minimum noise figure as a function of the frequency f according to

where K , is a frequency-independent, emvs. f curve. pirical fitting factor for the Fmin For GaAs MESFETs, K , has a typical value of approximately 2.5.

8.4.2 Heterostructure FETs Heterostructure MESFETs are generally more sophisticated versions of MESFETs, where the heterostructure is intended to provide a larger potential barrier for the gate electrode of the FET. An example of this consists of a thin Al,.,Ga,,,As Schottky barrier layer on a GaAs channel layer, both grown by MBE or low pressure MOVPE. This structure, with the larger Schottky barrier to limit the gate current, allows digital circuits to operate with a larger logic voltage swing on the gate and hence a better noise margin and larger current drive than the conventional MESFET.

These structures are also called HIGFETs or heterostructure-insulated gate FETs. Because the gate and channel are separated by an insulating wide band gap semiconductor, the channel can be doped either n-type of p-type, thereby providing a capability for not only the typical n-channel devices but also p-channel devices, which then makes low power complementary MESFET ICs possible.

8.4.3 High Electron Mobility Transistors High electron mobility transistors (HEMTs) utilize wide band gap/narrow band gap heterostructures (grown by MBE or MOVPE) to create a quantum well channel that is free of ionized impurities so high mobility electrons can conduct current from the source to the drain contacts. The wide band gap material not only serves to enhance the Schottky barrier to the narrower band gap channel (as in the heterostructure MESFET), but, by doping a thin portion of it, it also serves as a source of electrons which then diffuse into the quantum well channel to dope it. This is called modulation doping and gives rise to the name MODFET, which is synonymous with HEMT for the case of a two-dimensional electron gas (2-DEG) channel. An example of this heterojunction interface

8.4 Field-Effect Transistors (FETs)

DEPLETED

, i

I I I I

4 A'0.35Ga065As

Figure 8-5. Energy band structure of the heterojunction interface of a HEMT showing the channel doped by modulation doping to create the two-dimensional electron gas (ZDEG).

in a HEMT is shown in Fig. 8-5. Because the channel is undoped and physically removed from the ionized donors, and because the electrons travel in the quantum well parallel to the heterointerface, the HEMT electron mobilities are more typical of ultra-pure bulk semiconductors. It should be noted that p-type modulation doping is also feasible. Excellent HEMTs have been fabricated using several 111-V heterostructure combinations. The basic transistor structure and material combinations are summarized in

GaAs MESFET N+ GaAs N GaAs

N+Alo,3Gao.7As

N+ GaAs

P- GaAs P- GaAs

CHANNEL BUFFER

Si GaAs

SUBSTRATE

P- GaAs Si GaAs

Fig. 8-6. These different structures have evolved over time, the GaAs MESFET (shown on the left side of Fig. 8-6) being the oldest device and the InP HEMT (shown on the right side of Fig. 8-6) being the most recent. Currently the most common HEMTs are the GaAs pseudomorphic HEMTS, called PHEMTs, (Le., a GaInAs channel in a structure of AlGaAs and GaAs on a GaAs substrate) or AlInAs/ GaInAs HEMTS grown lattice-matched on InP substrates). The GaAs-based PHEMTs are used extensively for solidstate power amplifier applications at microwave and millimeter-wave frequencies. The InP-based HEMT appears to be the clear winner for ultimate minimum noise figure in low noise amplifiers, particularly at millimeter-wave frequencies. In order to obtain the maximum speed performance from any type of HEMT, it is not sufficient to simply use higher mobility materials or structures. It is also necessary to minimize the parasitic resistances (gate resistance and source and drain ohmic contact resistances) and device capacitances if the full potential of the high speed performance and low minimum noise figure are to be obtained from the HEMTs (Feuer et al., 1984).To minimize these parameters, fabrication technology commonly uses electron beam photolithography with multi-layer resists in order to fabricate HEMTs with InGaAs PSEUDOMORPHIC HEMT Nf GaAs

AlGaAs HEM1 N+ GaAs

401

lsGaO

asAs

GalnAs HEMT

N* Ga0.471n00.53As A10.481n0.52As

15Ga0.85As N-Ga0.471n0,53As P- GaAs N-Ai0,481n0S2As Si GaAs Si InP

Figure 8-6. Basic structure for various forms of 111-V compound semiconductor field-effecttransistor structures. The sequence from left to right represents the chronological evolution of 111-V FETs from GaAs MESFETs to GaInAs HEMTs.

402

8 Compound Semiconductor Device Structures

L , as small as 50 nm (more typically 100250 nm), which in cross section appear to have a mushroom, “T”, or ccdy structure. More details on HEMT theory, fabrication, and performance can be found in three excellent reviews by Drummond et al. (1986), Mishra et al. (1989), and Morkoc (1991),and in a book edited by Ali and Gupta (1991). HEMTs can claim the title of the “fastest three-terminal semiconductor devices”. These AlInAs/GaInAs HEMTs have been fabricated with 50 nm long gates, and they have demonstrated peak values of transconductance (gm) of 1740 mS mm- and extrinsic current-gain cutoff frequency (fT) of 340 GHz (Nguyen et al., 1992).

’

8.5 Heterojunction Bipolar Tkansistors Heterojunction bipolar transistors (HBTs) are quite different from the various FET transistors in that the former are vertical minority carrier devices in contrast to the lateral majority carrier conduction FETs. A schematic cross section of an HBT is shown in Fig. 8-7. These devices are generally fabricated with a mesa type structure, as shown in the figure, in order to place electrodes on the buried base and subcollector layers. This is typical for HBTs regardless of their epitaxial strucINTERCONNECTMETAL

SUECOLLECTOR

S.I. SUBSTRATE

Fipre8-7. Cross section of an HBT showing the generic device structure. (S.I.:semi-insulating).

tures. The mesa structure allows each device to be fully isolated from all others on the semi-insulating GaAs or InP substrate. This device also has its base contacts self-aligned to the emitter in order to minimize base resistance and thus enhance its speed. These epitaxially stacked device structures are most often grown by MBE (solid source, gas source, or chemical beam epitaxy) and by MOVPE. MBE has generally provided the capability for higher p-type base doping for n/p/n HBTs, though. The most common 111-V material combinations used for HBTs are shown in Fig. 8-8. HBTs are very similar in operation to Si bipolar junction transistors (BJTs), with the exception that they structurally utilize a wider band gap material in their emitter than in their base. This feature enables HBTs to achieve high gain while also utilizing heavier doping in the base for faster operating speed (Kroemer, 1957, 1982). The wider band gap emitter creates an energy barrier to base carriers to prevent them from being injected into the emitter when the base/emitter junction is forwardbiased. In the case of an n/p/n HBT, electrons are emitted into the p-type base layer from the emitter, but holes from the base are blocked from back injection into the emitter. This feature improves the emitter injection efficiency of the transistor, and thus its current gain. Thus the gain is not merely set by the ratio of emitter to base doping, as in the Si BJT. The ideal maximum common emitter current gain, (i.e., the maximum ratio of collector current to base current), is given by the following equation (Kroemer, 1982) for an HBT having an abrupt n/p heterojunction at the emitter/base interface: (8-9)

8.5 Heterojunction Bipolar Transistors

403

Figure 8-8. 111-V compound semiconductor material combinations used to form the most common HBTs. E, B, and C represent the emitter, base, and collector layers, respectively.

where ne is the n-type doping concentration in the wide band gap emitter (e.g., A10.3Ga0.7As, A10.481n0,52As,Or InPh P b the p-type doping concentration in the narrow band gap base (e.g., GaAs, GaO.47InO.5 3AS, Or Ga0,471n0, 5 3AS,respectively, corresponding to the above emitter materials), the electron velocity across the base, upe the hole velocity across the emitter, A E v the difference in valence and energies between the wide band gap emitter and the narrow band gap base, k , the Boltzmann constant, and T the junction temperature. In the case where the emitter/ base junction is compositionally graded, the above relationship for,,3,/ is modified by substituting A E , for A E v . A E , is equal to the energy difference between the wide band gap emitter and the narrow band gap base. The emitter/base junction is sometimes compositionally graded in order to eliminate the conduction band spike that occurs at the abrupt heterojunction. This spike causes part of the emitter current to tunnel through the junction, thereby reducing the collector current. The overriding effect of the heterojunction energy band discontinuity at the emitter/base junction is to allow the base layer to be very heavily doped, typically in

the range of 1-10 x 10'' holes/cm-3 (Jalali et al., 1990). Thus in an npn HBT the base can be quite thin (e.g., 50-100 nm) to maintain high gain, but conductive enough (e.g., sheet resistance of 500-1000 f2 sq.-') to provide a low base resistance for high speed transistor operation. The fact that these epitaxial structures are grown by techniques that allow precise layer-by-layer control gives HBTs a strong advantage in applications where the turnon voltage must be very uniform, such as for analog-to-digital and digital-to-analog converters. This turn-on voltage can have a standard deviation across the wafer of only 1 mV, and is as stable as the grown heterojunction. For a given collector current density (J,) through an HBT, the turnon voltage, vb,, is only a function of the material properties of the emitter/base junction in the device. This can be seen through the following relationship:

(8-10)

Here E , is the band gap on the base side of the junction, w b is the base width, D, is the electron diffusion coefficient in the base

404

8 Compound Semiconductor Device Structures

layer, and N , and N , are the effective density of states in the conduction and valence bands, respectively. Also, q is the electronic charge. The electronic transport properties of GaAs and Ga,,,,In,,,,As grown lattice matched on semi-insulating substrates of GaAs and InP, respectively, enable the npn HBTs to have cut-off frequencies of up to 200 GHz. GaInAs has a higher electron mobility, and GaInAs and InP have higher peak electron velocities and saturated electron velocities than GaAs, giving the InPbased materials lower parasitic resistances and shorter transit times. These high carrier velocities available in the 111-V compound semiconductors are critical for the fabrication of common emitter transistors with high unity gain cutoff frequency (fT), as mentioned above, and as seen through the following well-known expression (Early, 1958) for the emitter-to-collector transit time (zec):

Here the base transit time (zb) is inversely proportional to the electron (minority carrier) mobility (,un), more commonly expressed in terms of the minority carrier diffusion coefficient (DJ, and it is directly proportional to the square of the base width (Wb)

collector ( W,) (8-14) Finally, the collector charging time (z,) is directly proportional to the sum of the emitter and collector resistances (Re+ R,) times the base/collector junction capacitance (Cbc) (8-15) and similar the emitter charging time (zee) is directly proportional to the sum of the junction capacitances ( c & + Cb,) times the emitter resistance Re (8-16) As an example of the magnitude of the above values, consider an HBT with an fT value of 60-70 GHz, which is typical of most baseline pilot line fabrication processes. This corresponds to an emitter-tocollector transit time of approximately 2.4 ps. In turn, the forward transit time (zb+ 7,) is approximately half of this value, with the sum of the two charging times comprising the other half. Excellent reviews of HBTs can be found in books edited by Ali and Gupta (1991) and by Jalali and Pearton (1995).

8.6 Novel Semiconductor Laser Diodes

(8-12)

8.6.1 Introduction

(8-13)

The collector transit time (7,) is inversely proportional to the effective saturated velocity in the collector (us) and directly proportional to the space charge width in the

Semiconductor lasers are increasingly important components in commercial and telecommunication electronics. These devices now play a part in our daily lives through their use in compact and laser disc entertainment systems, and their impact in long-haul trans-oceanic communication networks. With the recent adoption of dig-

8.6 Novel Semiconductor Laser Diodes

ita1 technology by the commercial cable industry, semiconductor laser diodes will no doubt play a dominant role in the upcoming interactive, multimedia entertainment world. With the advent of ultralow-loss fiber optic technology, the long haul transmission of information is achieved by means of optical radiation emitted by laser diodes operating in the 1.5 pm regime (Li, 1991). The potential advantages of using blue light for the optical storage of information have spurred recent advances in blue laser diodes (Neumark et al., 1994). 8.6.2 The Cascade Semiconductor Laser A completely different type of semiconductor laser, whose stimulated light emission takes place within the conduction band of a semiconductor superlattice structure, was predicted by Kazarinov and Suris (1971). It was only through the development of band gap engineering, 18 years afterwards, that the first demonstration of intersubband emission was observed in GaAs/Al,~,Ga,~,As (Helm, et al., 1989). Subsequently, electroluminescence and a lasing action were demonstrated in a similar structure (Faist et al., 1993, 1994a, b). The principle of operation of this novel laser system, named the cascade laser, relies on an electron tunneling transition between two adjacent quantum wells with different energy levels, followed by the emission of light with the appropriate frequency of oscillation.

8.6.3 The Blue-Green Semiconductor Diode Laser The world’s first blue-green laser diode was fabricated from a wide band gap ZnSe single quantum well structure (Haase et al.,

405

1991). The device emits coherent light at 490 nm under pulsed excitation at 77 K. This work represents a significant achievement in the field of material engineering. Prior to this demonstration, the practicality of fabricating short wavelength semiconductor lasers was hindered by the ability to insert n- and p-type dopants into wide band gap materials. Only recently have modern techniques for quantum engineering, such as molecular beam epitaxy (MBE), made it possible to obtain device quality n- and p-doped ZnSe. A measure of the material quality is the maximum net acceptor concentration that can be achieved. In the case of ZnSe, concentrations as high as lo1* cm-, were obtained using nitrogen-free radicals produced by an rf plasma source. The device is grown on an Si-doped n + GaAs substrate. The emitting layer is a Cd,,,Zn,,,Se quantum well of 100 A thickness, surrounded by 1 pm thick ZnSe layers. These layers confine the light to propagate along a waveguide mode. The cladding layers are ZnS,~,,Se,~,, , which is nearly lattice matched to the GaAs substrate. Gold was evaporated to form electrodes at the top and bottom of the device structure. The n-type layers are doped with C1 at a donor concentration of 10’’ cm-, for the guiding layer, and IO1, cm-, for the cladding layer. The p-type layers are doped with N with a net acceptor concentration of ioi7 ~ m - ~ . The measured laser performance at 77 K gives a threshold current of 74mA, a threshold voltage of 20V, an emission wavelength of 490 nm, a differential quantum efficiency in excess of 20% per facet, and pulsed output optical power of greater than 100 mW per facet. No lasing was observed for room temperature operation due to thermal loading problems associated with the metallic contacts.

406

8 Compound Semiconductor Device Structures

Since then, several groups have confirmed and improved the performance of the blue-green lasers by designing an appropriate quantum well structure made of wide band gap materials (Okuyama et al. 1994; Salokatve et al., 1993a). The first cw operation of the blue-green laser at room temperature was demonstrated in a ZnCdSe/ZnSSe/ZnMgSSe pseudomorphic separate confinement heterostructure (Nakayama et al., 1993a, b; Salokatve et al., 1993b). The lasers were operated at a much lower threshold (35 mA and 4.4 V) and an output optical power of up to 10 mW per facet. These results indicate that semiconductor lasers operating in the blue will significantly impact the commercial development of high density optical storage systems.

8.7 References Ali, F., Gupta, A. (Eds.) (1991), HEMTs&HBTs: Devices, Fabrication, and Circuits. Boston, MA: Artech House. Arthur, J. R. (1968), J. Appl. Phys. 39, 4032. AuCoin, T. R., Savage, R. 0. (1985), in: Gallium Arsenide Technology, Ferry, D. K. (Ed.). Indianapolis, IN: Howard W. Sams & Co., pp. 47-78 Bahl, I. J., Willems, D. A., Naber, J. F., Singh, H. P., Griffin, E. L., Pollman, M. D., Geissberger, A. E., Sadler, R. A. (1990), ZEEE Trans. Microwave Theory Technol. 38, 1232. Brehm, G. E. (1990), ZEEE Trans. Microwave Theory Tech. 38, 1164. Drummond, T. J., Masselink, W. T., Morkoc, H. (1986), Proc. ZEEE 74, 773. Early, J. M. (1958), Proc. IRE 46, 1924. Eden, R. C. (1982) Proc. ZEEE 70. Faist, J., Capasso, F., Sirtori, C., Sivco, D. L., Hutchinson, A. L., Chu, S. N. G., Cho, A. Y. (1993), Electron. Lett. 29. 2230. Faist, J., Capasso, F., Sivco, D. L., Sirtori, C., Hutchinson, A. L., Cho, A. Y (1994a), Science 264, 553. Faist, J., Capasso, F., Sivco, D. L., Sirtori, C., Hutchinson, A. L., Cho, A. Y. (1994b), Electron. Lett. 30, 865. Feuer, M. D., Hendel, R. H., Tu, C. W. (1984), ZEEE Trans. Electron Devices ED-31, 1967.

f*ckui, H. (1979), ZEEE Trans. Electron Devices ED-26, 1032. Haase, M. A., Qiu, J., DePuydt, J. M., Cheng, H. (1991), Appl. Phys. Lett. 59, 1272. Helm, M., England, P., Colas, P., DeRosa, F., Allen, S. J. (1989), Phys. Rev. Lett. 63, 74. Hooper, W. W., Lehrer, W. I. (1967), Proc. ZEEE 55, 1237. Jalali, B., Pearton, S. J. (1995), ZnP HBTs: Growth, Processing, and Applications. Boston, MA: Artech House. Jalali, B., Nottenburg, R. N., Levi, A. F. J., Hamm, R. A,, Panish, M. B., Sivco D., Cho, A. Y.(1990), Appl. Phys. Lett. 56, 1460. Kazarinov, R. F., Suris, R. A. (1971), Sov. Phys. Semicond. 797. Kroemer, H. (1957), Proc. IRE 45, 1535. Kroemer, H. (1982), Proc. ZEEE 70, 13. Li, T. (1991), Topics in Lightwave Transmission Systems. London Academic. Mead, C. A. (1966), Proc. ZEEE 54, 307. Mendel, J. T. (1981), Microwave J. 24. Mishra, U. K., Brown, A. S., Delaney, M. J., Greiling, P. T., Krumm, C. F. (1989), ZEEE Trans. Microwave Theory Tech. 37, 1279. Morkoc, H. (1991), ZEEE Circuits Devices 7, 14. Nakayama, N., Itoh, S., Ohata, T., Nakano, K., Okuyama, H., Ozawa, M., Ishibashi, A., Ikeda, M., Mori, Y. (1993a), Electron. Lett. 29, 1488. Nakayama, N., Itoh, S., Okuyama, H., Ozawa, M., Ohata, T., Nakano, K., Ikeda, M., Ishibashi, A., Mori, Y. (1993 b), Electron. Lett. 29, 2194. Neumark, G. F., Park, R. M., DePuydt, J. M. (1994), Phys. Today 47 ( 6 ) , 26. Nguyen, L. D., Brown, A. S., Thompson, M. A., Jellokin, L. M. (1992), ZEEE Trans. Electron Devices 39, 2007. Okuyama, H., Itoh, S., Kato, E., Ozawa, M., Nakayama, N., Nakano, K., Ikeda, M., Ishibashi, A., Mori, Y. (1994), Electron. Lett. 30, 415. Pengelly, R. S. (1986), Microwave Field-Effect Transistors - Theory, Design, and Applications, 2nd ed. Herts, UK: Research Studies Press, p. 32. Pucel, R., Hans, H., Statz, H. (1975), Adv. Electron. Electron Phys. 38, 195. Salokatve, A,, Jeon, H., Hovinen, M., Kelkar, P., Nurmikko, A. V., Grillo, D. C., He, L., Han, J., Fan, Y., Ringle, M., Gunshor, R. L. (1993 a), Electron. Lett. 29. Salokatve, A., Jeon, H., Ding, J., Hovinen, M., Nurmikko, A. V., Grillo, D. C., He, L., Han, J., Fan, Y., Ringle, M., Gunshor, R. L., Hua, G. C., Otsuka, N. (1993 b), Electron. Lett. 29, 2192. Shen, C. C., Hartman, D. H. (1985), in: Gallium Arsenide Technology, Ferry, D. K. (Ed.). Indianapolis, IN: Howard W. Sams & Co., pp. 409-422. Shockley, W. (1952), Proc. IRE 40, 1365. van Tuyl, R., Liechti, C. (1977) ZEEE Spectrum, 41.

9 Silicon Device Processing Dim-Lee Kwong Microelectronics Research Center. Department of Electrical and Computer Engineering. The University of Texas at Austin. Austin. TX. U.S.A.

List of 9.1 9.2 9.2.1 9.2.2 9.3 9.3.1 9.3.2 9.3.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.5 9.5.1 9.5.2 9.5.2.1 9.5.2.2 9.5.2.3 9.5.2.4 9.6 9.6.1 9.6.2 9.6.3 9.6.4 9.7 9.7.1 9.7.2 9.7.2.1 9.7.2.2 9.7.2.3 9.7.2.4 9.7.2.5

Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Gettering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 413 Intrinsic Gettering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 Gettering by Hydrogen Annealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 418 LOCOS-Based Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 Advanced Isolation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silicon-on-Insulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 Gate Dielectrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 430 Preoxidation Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Process Dependence of Gate Oxide Quality . . . . . . . . . . . . . . . . . . . . . . . . . . Chemically Modified Gate Oxides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 438 CVD and Stacked Oxides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shallow Junction Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 440 Ion Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Techniques for p+-n Junction Formation . . . . . . . . . . . . . . . . . . . 442 Diffusion from Doped Deposited Layers ............................ 443 Gas Immersion Laser Doping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 Gas Phase Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 448 Plasma Immersion Ion Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metallization .................................................... 448 449 Gate Electrodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 463 Planarization for Multilevel Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . Cluster Tool Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 471 Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 Rapid Thermal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . In Situ Dry Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Interface Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 Gate Stack of Nitride and Oxynitride . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 475 Deposition of DRAM Storage Dielectrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selective Deposition Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

408

9.7.2.6 9.7.2.7 9.7.2.8 9.7.3 9.8

9 Silicon Device Processing

Ultra-Shallow Junction Formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integrated CMOS Processing Based on RTP . . . . . . . . . . . . . . . . . . . . . . . . . Ge,Si, - Si Heteroepitaxy by RT-CVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Wafer Integrated Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

476 477 477 479 480

List of Symbols and Abbreviations

List of Symbols and Abbreviations C Dit

Dt Eeff

K Leff Nsurf

P Qbd

R drldt dsldt T t tbd f o x , eff

VT A&b

capacitance interface density of states diffusivity x time breakdown electric field effective electric field Preston coefficient effective length surface doping concentration pressure charge-to-breakdown resistance removal rate relative velocity temperature time time-to-breakdown effective oxide thickness threshold voltage flatband voltage shift junction depth

Peff

effective electron mobility

alc AHF APCVD ASIC BESOI Bi-CMOS BOX BPBL BPSG BSG CMOS CMP CVD CZ DCS DI DMAH DOF DZ ECR

amorphous/crystalline anhydrous HF atmospheric pressure chemical vapor deposition application specific integrated circuit bond and etch-back silicon-on-insulator bipolar complementary metal oxide semiconductor buried oxide bird’s beak controlled poly-buffered local oxidation of silicon boropolysilicate glass borosilicate glass complementary metal oxide semiconductor chemical-mechanical polishing chemical vapor deposition Czochralski (wafers) dichlorosilane distilled dimethylaluminum hydride depth of focus denuded zone electron cyclotron resonance

409

410

9 Silicon Device Processing

extrinsic gettering fabrication facility field effect transistor full isolation by porous oxidized silicon gate induced drain leakage gas immersion laser doping gate oxide integrity heterojunction bipolar transistor high temperature oxides HTO intrinsic gettering IG isopropyl alcohol IPA low-impurity-channel transistor LICT local oxidation of silicon LOCOS low pressure chemical vapor deposition LPCVD low temperature oxides LTO magnetic Cz MCZ metal oxide semiconductor MOS metal oxide semiconductor field effect transistor MOSFET multiple quantum well MQW nitride-clad local oxidation of silicon NCL oxidation induced stacking faults OISF oxideinitride ON oxide/nitride/oxide ON0 poly-buffer local oxidation of silicon PBL poly-buffer recessed PBR polysilicon encapsulated local oxidation PELOX plasma immersion ion implantation PI11 p-channel MOS PMOS polysilicon Poly polysilicate glass PSG random access memory RAM Radio Corporation of America RCA RESSFOX recessed sealed sidewall field oxidation reactive ion etching RIE reverse L-shaped sealed poly-buffer localoxidation of silicon RLS-PBL rapid thermal annealing RTA rapid thermal chemical vapor deposition RTCVD rapid thermal multiprocessing RTMP rapid thermal nitridation RTN rapid thermal oxidation RTO rapid thermal processing RTP subatmospheric pressure CVD SACVD silicon as diffusion source SADS SALICIDE self-aligned silicide SCVDW selective CVD tungsten

EG fab FET FIPOS GIDL GILD GO1 HBT

List of Symbols and Abbreviations

SEG SILO SIMOX SIMS SMD SOG

so1

SRAM SRO SST STI SWAMI TDDB TEOS TIBA ttv UHVCVD ULSI VLSI

selective epitaxial growth sealed interface local oxidation separation by implantation of oxygen separation by implantation of silicon surface micro-defects spin-on glass silicon-on-insulator static RAM stress relief oxide sealed sidewall trench shallow trench isolation sidewall mask isolation time-dependent dielectric breakdown tetraethyl orthosilicate triisobutyl aluminum total thickness variation ultra-high vacuum chemical vapor deposition ultra-large scale integration very-large scale integration

41 1

412

9 Silicon Device Processing

9.1 Introduction Demand for low cost, high speed integrated circuits with large on-chip functionality has necessitated the scaling down of device dimensions in MOS ICs. Reduction in channel length of a MOSFET increases its drive current capability, which is necessary for faster switching of capacitive loads. Moreover, scaling down of device dimensions is desirable in order to obtain higher levels of integration on a chip. Such high levels of integration can lead to a higher on-chip functionality in logic applications and a higher storage capacity in memory applications. Over the last ten years, silicon devices have progressed from micron into deep-submicrometer dimensions. As we begin the era of sub-0.5 pm fabrication, conventional device structures and fabrication techniques are reaching their physical limitations. Therefore, device and process designs, together with new materials must be developed to maximize the gain in performance, yet at the same time meet the increasingly stringent reliability requirements. This chapter covers semiconductor process technology for CMOS devices. It provides a comprehensive survey of some of the key process technologies involved in manufacturing state-of-the-art CMOS devices. These include device isolation, gate dielectrics, shallow junctions, and metallization. Emerging technologies in these areas that have received considerable attention in recent years from the research and development community are also included. Areas that will need significant improvement and changes for the future to comply with the device downscaling while maintaining reliability goals will be discussed. In addition, since dry etching and trench structures are increasingly being used in device fabrication, gettering tech-

niques which supply gettering sinks closer to the active device region are required to control and eliminate serious contamination problems. Furthermore, the use of larger size wafers and the more stringent requirements for process performance, reliability and cost have driven the move from batch processing to single wafer, integrated processing where large size single wafers are processed and sequential process steps can be “clustered’’ into multichambered in situ processing modules or into linked cells of independent modules. Finally, as we continue to reduce the thermal cycle, rapid thermal processing becomes an attractive direction in sub-0.5 pm processing.

9.2 Gettering Because of intense competition in manufacturing quality and cost, together with increasingly complex fabrication processes, ULSI manufacturing will require profound effort to cut down defect generation due to unintended contamination. By the year 2000, the number of discrete process steps in the manufacturing of advanced DRAM chips is expected to exceed 700. Significant efforts are required towards defect reduction of any given processes and equipment. Highly mobile transition metals have been identified as one of the main contaminations that degrade device yield and reliability. These fast-diffusing transition metals can nucleate or decorate extended crystalline defects (dislocations, stacking faults, precipitates, etc.) and form deep level defects, which generate leakage currents and lifetimekilling recombination, or silicide precipitates which cause junction shorts and oxide breakdown. The effects of Fe, Cu, Ni, and Cr impurities on junction leakage,

9.2 Gettering

SiO, film breakdown, and MOS C-t characteristics have been studied extensively (Ohsawa et al., 1990). In general, Fe increases the junction leakage current at the periphery isolated by LOCOS and causes the gate SiO, breakdown by lowering the potential barrier height at electrode-SiO, interfaces. Cu, Ni, and bulk Fe generate weak spots in the oxide in the form of crystal defects, causing gate oxides breakdown. In addition, these defects also degrade MOS C-t characteristics. Fe decreases the generation lifetime and increases the surface generation velocity at concentrations above 5 x 1011 cm-2, while Ni reduces generation lifetime even at concentrations as low as l ol o cm-2. Transition metal atoms in silicon generally occupy interstitial and substitutional lattice sites, and diffuse via predominantly interstitial diffusion through the open diamond lattice (Weber, 1988). This interstitial diffusion is very fast, as it does not depend on the presence of native lattice defects, and has typical activation energies of the order of 0.4-1.8 eV, as shown in Table 9-1 (Weber, 1990). Although precautions, such as wafer surface cleaning procedures, clean room conditions, and the purity of water and other chemicals, can reduce the level of contamination, they cannot exclude accidental metal contamination. Gettering is a technique which effectively removes heavy metals from the Table 9-1. Diffusion coefficients of 3d metals in intrinsic silicon.

Do (cm2/s) Ti Cr Fe

co Ni

1.45 x 1.0 x 1.3 x 9.0 x 2.0 x 4.7 x

10-2 10-3 10-4 10-3

io-’

AH,,, (eV)

T range (“C)

1.79 1.o 0.68 0.37 0.41 0.43

950- 1200 900 - 1250 30-1250 900- 1100 800-1300 400- 700

41 3

active device regions. It is a necessary insurance policy for high device yields, because it allows to considerably increase the level of accidental contamination which can be tolerated. Extrinsic gettering (EG) employs external treatments to create either extrinsic or intrinsic defects to getter metallic impurities. These include: phosphorus diffusion (Seidel, 1975), ion implantation (Seidel, 1975), mechanical damage (Mets, 1965), and polysilicon deposition (Chen, 1982). Both substitutional and interstitial impurities can be collected near the backside of the wafer and gettering occurs during high temperature annealing. In the case of intrinsic gettering (IG), extrinsic or intrinsic defects are already present in as-grown materials or are produced or activated by annealing. Because extrinsic gettering techniques have several limitations, such as lack of stability and gettering process induced side effects, more focus has been on intrinsic gettering.

9.2.1 Intrinsic Gettering The gettering process removes metal impurities from active device regions by (1) release of the impurities to be gettered; (2) diffusion of the impurities to the region where they are gettered; and (3) capture of the impurities by extended defects (stacking faults, dislocations or precipitates). The intrinsic material properties of Czochralski (Cz) grown wafers (e.g., interstitial oxygen, substitutional carbon, Si vacancies, Si interstitials, dopant point defects, as grown precipitates and stacking faults, etc.) are used to induce bulk oxygen precipitation by the formation of SiO, ( x x 2 ) complexes. Due to the lower density of Si in SiO, as compared to bulk silicon, these SiO, precipitates generate silicon lattice disorder and dislocations that act as gettering sites (traps) for unwanted impu-

414

9 Silicon Device Processing

rities (Tan, 1977). Also associated with the formation of SiO, precipitates is the ejection of silicon interstitials (SiI), which can enhance the migration/diffusion of the impurities to the gettering sites. For effective IG, both a denuded zone (defect-free area) in the device active region and gettering sites in the bulk of the wafer away from the active region must be formed. Intrinsic gettering of interstitial transition metals in silicon can be achieved using following sequence of heat treatments (Gupta and Swarroap, 1984): Step 1: Denudation: Annealing at a high temperature (above 1100°C) to form the denuded zone by out-diffusion of oxygen from the region near the wafer surface; Step 2: Nucleation: Annealing at a low temperature (below 700°C) to hom*ogeneously nucleate oxygen precipitates; Step 3 : Growth: Annealing at a high temperature (above 1000“C) to accelerate the growth of oxygen precipitates. The first high temperature annealing step causes interstitial oxygen to out-diffuse from the wafer surface. This reduces the oxygen concentration in a several tens of micrometers thick layer below the surface towards the solubility at this out-diffusion temperature. Heat treatments for a few hours at temperatures above 1100°C in inert or oxidizing ambients are very effective for denuding. A surface oxide cap is recommended at this step to protect the wafer surface from possible contamination and pitting. However, a pure oxidizing ambient is not recommended because, during high temperature oxidation, excess Si, is ejected at the oxidizing front, resulting in a supersaturation of Si, in the bulk. This makes the free energy of formation for

SiO, precipitates thermodynamically unfavorable, leading to oxidation induced stacking faults (OISF) and retardation of bulk SiOx precipitation (Hu, 1980). In the subsequent nucleation step the supersaturation of oxygen in this subsurface layer is no longer sufficient to form stable nuclei. However, nuclei will be formed in the interior of the crystal. These oxygen clusters, after reaching a critical size, will grow during the third annealing step. Gilles et al. (1990) have studied the lowtemperature Fe precipitation kinetics in Cz-Si. They proposed a mechanism for intrinsic gettering based on impurity saturation and precipitation during the gettering process. The model shows that the gettering efficiency depends on the difference between the precipitation kinetics of the impurity species in the denuded zone and in the bulk. This model allows optimization of the gettering temperature for a given impurity and contamination level. If there is a sufficient density of heterogeneous nucleation sites for impurity precipitation, the gettering process is uniquely determined by the diffusion coefficient of the interstitial impurity, the width of the denuded zone, and the cooling rate or temperature which is used for the gettering process. The relevance of oxygen to integrated circuit fabrication is primarily due to the ability of oxygen to form oxide precipitates and to generate lattice defects in a controlled manner for impurity gettering during device processing. In addition, the presence of interstitial oxygen in silicon gives an added strengthening effect to the silicon lattice, which can prevent plastic deformation and slip during wafer thermal processing. In precipitation gettering, care must be taken to avoid over-precipitation, which would “drain” interstitial oxygen from the silicon lattice. The reduction of

9.2 Gettering

interstitial oxygen lowers wafer’s yield strength and would make it more susceptible to plastic deformation when subjected to thermal gradients. The net results are wafer warpage, and generation of slip dislocations into active device regions. A wide range of oxygen concentrations have been applied in IC device processing (ASTM, 1988), depending on the nature of thermal processing and sensitivity of the device to gettering/defect generation. In general, for device processing technologies in which gettering by precipitates is essential, high or medium oxygen concentrations are needed. When the device performance is more sensitive to lattice defects, the oxygen related defect formation is intentionally avoided by using Si wafers such as magnetic CZ (MCZ) wafers with low oxygen and low microdefect density. In ULSI device manufacturing, it is essential to “engineer” oxygen precipitation to occur at the right locations and at the right time through tight control of wafer oxygen concentration and/or tailoring of thermal process strategically. Depending on oxygen level and thermal cycle sequence, the precipitate distribution in the wafer cross-section can be classified into four categories, as shown in Fig. 9-1 (Lin, 1990). Figure 9-1 a is an ideal configuration where a denuded zone in the device active region and gettering sites in the bulk of the wafer away from the active region are formed. Figure 9-1 b is a non-perfect denuded zone formation due to local precipitation enhancement. This effect is caused by grown-in microdefects or local oxygen concentration fluctuations. The configuration shown in Fig. 9-1 c corresponds to uniform oxygen precipitation with no oxygen out-diffusion during gettering, resulting in no denuded zone formation. This may be caused by using a mismatched thermal cycle. The precipi-

41 5

Figure 9-1. Schematic wafer cross-sections showing various denuded zone and precipitate zone distributions during IC processing.

tates and bulk stacking faults can intersect the device active surfaces and cause gate oxide integrity (GOI) degradation. Figure 9-1 d corresponds to situations where the oxygen precipitation is intentionally avoided by using wafers with oxygen concentration below the threshold of oxygen precipitation for the thermal cycle used. Therefore, when integrating I G into CMOS device process flow, it is important to understand how IG is to be activated in order to optimize and maintain I G effectiveness and durability through the numerous high temperature thermal cycles. In most CMOS device processing lines, process induced IG occurs naturally in the wafer because the processing thermal sequence is similar to the three-step thermal IG cycle. The high temperature (> 1100“C) N-well/P-well drive-in process also acts as an effective denudation step, causing oxygen out-diffusion. Following the well drive-in process is usually the field oxide isolation process at intermediate temperatures between 900 “C and 1000“C. This will also induce oxygen precipitation and growth in the bulk of the wafer, thereby

41 6

9 Silicon Device Processing

activating the IG process. For some other CMOS device processing lines, process induced IG may not be sufficient, so enhanced process induced IG is required. By adding a 700°C SiO, nucleation anneal step after the well drive-in step prior to the field oxide isolation step, one can increase the precipitate density and SiO, precipitation rate during the field oxidation step. In this way, the IG effectiveness is improved, especially for the critical gate oxidation step.

9.2.2 Gettering by Hydrogen Annealing As the design rules of MOS ULSI shrink to the quarter micron range, high quality and high reliable ultra-thin silicon oxides are required for gate oxide and tunnel oxide. In general, the failure of a thin oxide can be categorized by three modes (Yamabe, 1990): Mode A, Mode B, and Mode C. Mode C failures represent intrinsic oxide breakdown while mode A failures are related to surface foreign material such as unintentional contaminants. impurities and particles. Mode B failures on the other hand are related to silicon material crystallographic defects such as as-grown stacking faults and SiO, precipitates and process induced crystallographic defects. It has been shown that the crystal quality of the silicon wafer surface plays an important role for gate oxide integrity (GOI) (Yamabe et al., 1983; Ryuta et al., 1990; Yamagishi et al., 1992; Miyash*ta et al., 1991; Miyash*ta and Matsush*ta, 1993): crystal defects in the wafer surface region reduce the dielectric breakdown strength and long-term reliability of thin oxides (Miyash*ta and Matsush*ta, 1993). Silicon wafers typically used for ULSI fabrication are made of CZ grown crystal and have several types of as-grown defects, such as

oxygen precipitates and surface micro defects (SMD) (Yamabe, 1990; Yamabe et al., 1983; Ryuta et al., 1990; Yamagishi et al., 1992; Miyash*ta et al., 1991; Miyash*ta and Matsush*ta, 1993). To reduce these micro-defects near the silicon wafer surface extensive research has been done. One approach is to form a denuded zone (DZ) by annealing the silicon wafers at high temperatures in an oxygen-containing environment (Tsuya, 1991). Having a region free of defects and interstitial oxygen will result in the elimination of mode B failures. The use of an epitaxial layer as a DZ also significantly improves GOI. Another possibility to decrease the as-grown defects is to slowly grow the silicon crystal and control the thermal history of the crystal (Hizuki et al., 1990). These approaches have proved to be effective in reducing the as-grown defects to some extent, but insufficient for the improvement of time-dependent dielectric breakdown (TBBD) of oxides thinner than 10nm (Miyash*ta and Matsush*ta, 1993). Annealing of silicon wafers in a hydrogen environment at high temperatures to cause outward oxygen diffusion has been shown to be a very effective method to reduce the oxygen precipitates in the surface region. Improved GO1 has been reported in hydrogen annealed wafers (Matsush*ta et al., 1988; Adachi et al., 1992; Samato et al., 1993). A comparison of oxygen concentration and defect density for hydrogen-annealed CZ wafers, conventional CZ wafers, defect-free CZ wafers, and epitaxial wafers is shown in Fig. 9-2 (Nikkei, 1993). It is clearly seen that the hydrogen-annealed wafers are comparable to the more expensive epi wafers, but are superior to other wafers. On the other hand, however, Omar et al. (1992) observed a high density of micropits on the surface after annealing in H, at 1150 "C. Xu et al. (1993) also observed sur-

9.2 Gettering

41 7

Figure 9-2. Comparison of oxygen concentration and oxygen-extraction defects for hydrogen-annealed Cz wafers, conventional Cz wafers, defect-free Cz wafers and epi wafers.

face roughening during pre-annealing at 1050°C in H, which resulted in degraded dielectric breakdown. More fundamental understanding of the hydrogen annealing mechanism and process optimization is

needed before this technology can be incorporated in ULSI manufacturing. Deep submicrometer CMOS technology is switching from high-temperature diffused well to low-temperature MeV im-

41 8

9 Silicon Device Processing

plantation technology (Lee et al., 1993). A process sequence based on MeV implantation can eliminate two to three masking steps, eliminate up to 30 processing steps, improve surface topography, and reduce manufacturing cost by 5 to 15 YO,depending on the application. For MeV processing a denudation step must be added or incorporated into the process flow. An inert denuding environment is superior to an oxidizing environment and hydrogen has been reported to be the best (Borland and Koelsch, 1993; Borland, 1989). Recently a significant breakthrough in bulk Cz wafer quality was reported by using hydrogen annealing/denudation, resulting in the realization of surface properties similar to those on epi wafers without additional cost (Nikkei Microdevices, 1993). Under inert conditions such as hydrogen annealing at temperatures as high as 1200°C for 1 h, elimination of mode B failures has been reported (Samato et al., 1993). Gardner et al. (1994) reported significantly improved CMOS bulk Cz wafer quality on the use of hydrogen denudation processing (annealing). Superior device performance, thin tunnel/gate oxide quality and Cz wafer surface properties have been measured demonstrating the potential for epitaxial elimination. This is achieved by subjecting the wafers to a short hydrogen denudation pre-process between 1050“C and 1200“C for 15-30min. For thin oxides down to 8.2 nm up to 29% improvement was observed on two different QBD structures. Hydrogen denuding was also very effective in eliminating mode B oxide breakdown failures on bulk non-epitaxial Cz wafers, Additionally, an order of magnitude decrease in junction leakage was observed for the H 2 annealed wafers relative to the bulk non-epitaxial Cz wafers, resulting in bulk Cz wafers with surface properties similar to epi wafers without the added cost. These

results have immense potential cost savings for all CMOS fabrication areas today currently using epitaxial substrates, especially when applying MeV technology.

9.3 Device Isolation The electrical isolation of active devices in integrated circuit technology includes both general oxide isolation in the “field” regions between devices and special application structures. The most common isolation is the field region, which is typically implemented by partially or fully recessed thick oxide regions between active device regions. Complete oxide isolation with no parasitic leakage paths is possible only in silicon-on-insulator (SOI) technologies. Special isolation structures, such as deep trenches, have been developed to separate the n- and p-well regions of complementary MOS (CMOS). The basic desired properties for any isolation technology are: A small pattern transfer difference be-

tween mask layout dimensions and final device geometries. No downscaling of the field oxide thickness as other device geometries are scaled down. A planar surface topology. A defect-free process. 9.3.1 LOCOS-Based Isolation Almost all modern integrated circuits use LOCOS (local oxidation of silicon) for device isolation (Appels et al., 1970). A nitride/oxide stack is formed on the silicon substrate and is patterned and etched to remove the nitride layer in the field regions. Before the resist is stripped off, boron impurities are implanted into the field

9.3 Device Isolation

regions. The oxidation is then followed and the silicon is oxidized only locally in the field regions without nitride coverage. The thickness of the field oxide typically is between 700 and 1000 nm. A major drawback of LOCOS is the so-called “bird’s beak” transition between the field region and active device area (Bassous et al., 1976), caused by lateral diffusion of oxidizing species beneath the nitride oxidation mask. The transition length varies depending on the oxidation condition. This transition reduces the device packing density and, as the isolation area is scaled down for VLSI application, the problem becomes more serious. Scaling down the field oxide thickness can reduce the encroachment, but requires a heavier channel-stop implantation to maintain adequate isolation between the devices. The lateral diffusion of the channel-stop impurities during the oxidation and the subsequent high temperature processes can degrade junction capacitance, increase the junction leakage and reduce the “effective” electrical channel width associated with MOS current gain. An option in scaling LOCOS is a channel-stop implant done after the oxidation. This reduces the depletion of boron into the field oxide during the field oxidation, thus retains more boron impurities near the oxide/silicon interface in silicon. As a result, thinner oxide can be used to achieve appropriate isolation. However, the field oxide threshold voltage is very sensitive to the oxide thickness with through-field implant due to the variation of the field oxide thickness. Another problem associated with through-field implant is the increased junction capacitance and reduced junction breakdown voltage for N + / P junctions due to the increased substrate concentration under the junctions from the high energy, unmasked through-field implant.

41 9

Modifications of the LOCOS process have been investigated. SWAMI (sidewall mask isolation) is one of the best known LOCOS-based isolation techniques (Chiu et al., 1982) and was developed with the objective of retaining the advantages of LOCOS while drastically reducing the bird’s beak. Since the bird’s beak is due to oxygen lateral diffusion through thin oxide from the active area edges, an obvious solution is to block it with a nitride barrier (Teng et al., 1985). SILO’S (sealed-interface local oxidation) approach to bird’s beak reduction consists of reducing the thickness of the LOCOS pad oxide to zero in order to seal the silicon interface under the LOCOS stack (Hui et al., 1982). This eliminates the need for a perimeter nitride seal, as used in SWAMI, and allows for a simpler process. SILO uses an active area stack with two different nitride layers, one very thin ( x130 8, for interfacial seal) in direct contact to silicon and one much thicker (x1000 8, for oxidation mask) on top of the stack. Between them, the usual pad oxide is retained for stress relief purposes. The key to prevention of Si defects is the extremely small thickness of the sealing nitride, which limits the compressive stress induced in Si to values below the plastic deformation threshold (DerouxDauhphin et al., 1985). Another approach uses a stress relief poly-buffer layer between the nitride and the initial pad oxide (poly-buffer LOCOS, PBL), which absorbs stress produced during field oxidation (Nishihara et al., 1988; Havemann and Pollack). Although low bird’s beak was demonstrated, the resulting field oxide protrudes significantly above the original silicon surface, producing severe topography. Using the principle of a stress relief polysilicon layer and a reverse L-shaped sealed nitride spacer, the bird’s beak can be further reduced com-

420

9 Silicon Device Processing

pared to conventional PBL (Sung et al., 1990). The process flow for this reverse L-shape sealed poly-buffer LOCOS (RLSPBL) is shown in Fig. 9-3 (Sung et al., 1990). The pad oxide is selectively removed using the silicon nitride/polysilicon stack as a mask to form undercut portions. A new stress-buffer oxide film is then grown to cover the entire silicon surface. After LPCVD nitride deposition and RIE, a reverse L-shape sealed silicon nitride spacer is formed. Shimizu et al. (1992) developed a poly-buffer recessed LOCOS (PBR LOCOS) isolation for 256 Mbit DRAM cells. In this process, the low bird’s beak and defect-free isolation are achieved by using shallow silicon recess etch (25-200 nm), buffer polysilicon, and nitride sidewall sealing. The process flow of PBR LOCOS is shown in Fig. 9-4.

\PAD

OXIDE

(a)

(C)

Figure 9-3. Reverse L-shape sealed PBL process flow: (a) formation of side etched portions of pad oxide; (b) sealed nitride film deposition; and (c) RIE nitride etching. The pad oxide (100 A), polysilicon film (500 A), nitride cap (2000 A), and regrown oxide (60 A) are not drawn to scale.

9.3.2 Advanced Isolation Techniques The scalability of LOCOS to deep submicrometer dimensions has been difficult due to the conflicting requirements for a small bird’s beak profile, defect-free substrate and adequate field oxide thickness to ensure good electrical isolation. Several isolation techniques have been investigated as replacements for standard LOCOS. Non-planar techniques are not favored because of the patterning difficulties associated with subsequent levels such as interconnect. Those that are sufficiently planar can be divided into the following categories : Modified LOCOS that use improved nitridation masking Shallow Trench Isolation (STI) Selective Epitaxial Growth (SEG) Trench isolation Silicon on insulator (SOI)

Figure 9-4. PBR LOCOS process sequence: (a) after recess etching; (b) after nitride sidewall formation; and (c) field oxidation.

9.3 Device Isolation

Recessed sealed sidewall field oxidation (RESSFOX) (Lee et al., 1990) employs a consumable sidewall nitride to reduce bird’s beak. A thin consumable nitride film of about 200 8, thickness is deposited over a shallow trench (150 nm) in the Si substrate after the field implant. RIE is used to form the consumable nitride on the sidewall of the shallow trench prior to field oxide growth. This thin nitride must be thick enough to block the oxygen lateral diffusion, and thin enough not to add additional stress and to be consumed during field oxidation. This is the main difference between RESSFOX and SWAMI. The use of a self-aligned nitride-filled or polysilicon-filled cavity followed by nitride spacer formation to offset the bird’s beak from the nitride-1 edge has received much attention for 0.25 ym CMOS technology. Polysilicon encapsulated local oxidation (PELOX) controls the bird’s beak through the use of a polysilicon-filled cavity, selfaligned to the nitride edge (Roth et al., 1991). The process only involves simple modification of a standard LOCOS process flow. These modifications include an HF dip after nitride pattering to form a cavity self-aligned to the nitride edge, reoxidation of exposed silicon, and polysilicon deposition to fill the cavity, as shown in Fig. 9-5. Using nitride-filled cavity instead of polysilicon-filled cavity, Pfiester et al. (1993) have developed a ni tride-clad LOCOS (NCL) isolation which exhibits 600 A per side bird’s beak encroachment profiles with adequate field oxide thickness in narrow field regions. The process flow is shown in Fig. 9-6. A bird’s beak controlled poly-buffered LOCOS (BPBL) was developed by Huang et al. (1993). A schematic process sequence of BPBL isolation is shown in Fig. 9-7. The pad oxide was grown, followed by LPCVD polysilicon and nitride deposi-

42 1

tions. After nitride etching by RIE, isotropic plasma etching was used to partially remove the exposed polysilicon to form rounded thin polysilicon regions under the nitride layer. After nitride spacer formation, the remaining polysilicon is removed to increase the recess depth of a 4000 8, field oxide. The corner between the first nitride and polysilicon is rounded to diffuse stress impinging from the nitride spacer to the Si substrate during field oxide growth. The polysilicon is thinned to minimize the bird’s beak penetration. Results show that the surface morphology is quite planar, Le., the recessed portion of field oxide profile reaches almost 70% of total thickness. Isolation space up to 0.35 ,urn has been achieved with excellent junction characteristics and gate oxide integrity. For buried oxide (BOX) isolation (Kurosawa et al., 1981; Shibata et al., 1983) or shallow trench isolation (STI) (Fuse et al., 1987; Davari et al., 1988; Pierce et al., 1991; Yu et al., 1992; Shibahara et al., 1992; Fazan et al., 1993) shallow trench and advanced planarization techniques are used. For feature size of 0.25 ym or below, neither LOCOS nor its advanced modifications are expected to provide the required surface planarity, field-oxide thickness, edge contour, and channel-stop characteristics. On the other hand, BOX and STI isolations have the potential to fulfill these needs. Unlike the local oxidation process, in BOX a deposited oxide is used. Thermal oxidation depletes the channel stop boron impurities near the interface which degrade the isolation. Using deposited oxide can retain more boron under the field and can achieve sharper corners with more potential barrier enhancement. However, BOX isolation suffers from process control problems, such as field isolation uniformity at mesa corners, double-resist processing, and

422

9 Silicon Device Processing

Figure 9-5. PELOX process flow: (a) RIE nitride; (b) HF dip to undercut nitride and form cavity; (c) growth reoxidation; and (d) deposit polysilicon encapsulation layer.

Figure 9-6. NCL process flow: (a) HF etching of the first stress relief oxide (SRO-1) to form a 750 8, selfaligned cavity under Nitride-1; (b) a 5 5 8, thermal reoxidation (SRO-2) followed by a 100 8, Nitride-2 deposition; and (c) field oxidation.

Figure 9-7. Process flow of BPBL isolation.

9.3 Device Isolation

423

Figure 9-8. STI process flow summary: (a) mask and trench definition, (b) trench oxidation and B doping, (c) CVD oxide and CMP planarization, (d) oxide spacer formation, (e) pad oxide wet etching, (f) gate oxide growth and gate deposition.

registration of the first-resist pattern. Moreover, the adoption of sloped sidewalls contrasts with the trend toward higher resolution. STI provides a planar surface and a fully recessed field oxide; it does not suffer from field oxide thinning and can easily be scaled down. Fazan and co-workers (1993) proposed a simple STI process suitable for 256Mb to 4Gb DRAMS. The process flow is summarized in Fig. 9-8. The features of this STI process are tapered trench sidewalls, a slight trench reoxidation, a vertical boron field implant, a CMP-only planarization, and disposable oxide spacers to smooth the trench corners. In addition to device isolation, STI has been employed to fabricate 0.25 pm CMOS devices with buried trench gate structures, as shown in Fig. 9-9 (Wen et ai., 1991). The entire poly gate is buried in both active and isolation areas and a fully planarized structure is achieved. The electrical Junction depth with respect to the channel surface is

Figure 9-9. Process sequence of the fully planarized CMOS technology.

424

9 Silicon Device Processing

about 50nm, which is much shallower than the conventional junction due to the recessed poly gate. Excellent short channel effects and device characteristics are achieved using this fully planarized CMOS technology. The highly planar topography of this technology also forms an excellent base for future planarized multilevel interconnect structures. SEG is conceptually the simplest method for achieving fully recessed oxide isolation. Active silicon layers are grown epitaxially between columns of oxide that serve as device isolation. At the leading edge of this technology, SEG demonstrated an incredibly short active area spacing across the well of only 1/4 pm (Kasai et al., 1987; Kamins et al., 1985). The rapid progress experienced by SEG has resulted in a growing number of publications and improvements in SEG fabrication equipment. indicating that this technique will play a major role in CMOS submicrometer isolation at 0.25 pm and below. The other 1. Oxide

2. Etch N-well windows

advantage of SEG is that the n-well and p-well can be formed independently, as shown in Fig. 9-10 (Borland, 1987). Independent n-well and p-well CMOS structures with retrograde wells can be realized through graded epitaxial growth without the use of ion implantation and high temperature annealing. This advantage can also be found in bipolar and BiCMOS structures. The selective doping is also very attractive for other applications such as shallow junction formation and contact refill as well as planarization for interconnect. Remaining issues to be resolved in SEG include the faceting and the defect generation in epi near the epi/oxide interface. Although defect-free structures have been reported for patterns oriented parallel to the (100) direction, they have yet to be determined for other orientations. The major objective of trenches is to achieve high density without suffering an increase of isolation leakage or having to reduce the supply voltage. This is achieved

3. N-Type SEG epi for N-well formation

4. Thin thermal

oxide

I 5. Etch P-well

windows

6. P-type SEG epi for P-well formation

7. Strip thin oxide

Retrograde wells are possible by buried layer epitaxy or graded epitaxy techniques

Figure 9-10. Independent n-well and p-well formation by SEG.

9.3 Device Isolation

by folding the silicon surface across the isolation to form a deep, narrow barrier, which increases the current path many times with respect to the spacing. Moreover, by digging the trench so deep that its bottom lies in heavily doped silicon, such as the substrate of an epitaxial wafer, the isolation leakage suppression is virtually complete. Particularly for trench capacitors, the trench oxidation properties are important to ensure high dielectric strength, high breakdown voltage, and low leakage current of the capacitor dielectric. Fortunately, these properties were found to be only slightly inferior to those of planar surfaces (Baglee et al., 1985), with the weakest spot being at the corners, where the oxidation rate is smaller (Marcus and Sheng, 1982). However, using a sacrificial oxidation, these corners can be rounded off erasing any difference between the trench and the planar oxide properties (Yamabe and Imai, 1981). Conventional trench isolation results in stress induced defect generation. The problem can be overcome by a sealed sidewall trench (SST) process (Teng et al., 1984) containing an additional nitride layer in the trench, although this introduces process complexity. With the conventional trench process (either refilled with poly or deposited oxide), the leakage is about 2 to 3 orders of magnitude higher than without a trench (Teng et al., 1984). However, with SST the leakage is comparable. Although trench isolation can produce excellent lateral isolation, it does not address vertical isolation. The ideal situation for future isolation would be to suspend both device types in a dielectric layer (e.g., SiOJ. This would effectively eliminate latch-up and radiation induced error phenomena, as well as reduce performance limiting effects such as parasitic capacitnnmts. Furthermore, such a structure

425

would require less layout area for the same design rules than conventional, junctionisolated CMOS, because the deep p- and n-wells are eliminated and the area required to accommodate p-n junctions is significantly reduced.

9.3.3 Silicon-on-Insulator Silicon-on-insulator (SOI) technology is a major contender to provide the high performance, low voltage, low power capabilities required for future generations of integrated circuits. The performance advantages of this technology, as well as the potential yield advantages offered by the unique “all around” isolation in SO1 devices, have been discussed in several publications. During the past several years, unique problems in device performance in this technology have been identified and solved, but the long standing issues of quality, availability, and cost of SO1 substrates have prevented this technology from being commercial IC applications. FIPOS (full isolation by porous oxidized silicon) employs lateral anodic oxidation to form isolated silicon islands over a silicon substrate (Zorinsky et al., 1986; Kubota et al., 1986; Imai et al., 1984). In early developments, lateral oxidation could only be extended to a few micrometers without forming excessively thick porous oxide films, which would cause warpage and later interfere with the rest of the process. An improved FIPOS approach was developed. It is known as the ISLANDS method (Zorinsky et al., 1986) and its process sequence is illustrated in Fig. 9-11. A heavily doped n + layer is formed by epitaxy followed by a second n-epitaxial layer with the desired resistivity. Then, Si,N, and SiO, are deposited to form the masking stack. Trenches with a

426

9 Silicon Device Processing

F== EPI LAVER

(*)

OXIDIZED POROUS SILICON LAVER

THERMAL OXIDE

SUBSTRATE

ANODIZABLE LAVER

FORM N+ ANODIUBLE LAYER QROW EPITAXIAL “TUB” LAYER ANODIZABLE LAVER \

FORM (POROUS) ANODIZED LAYER I) (P = FI [HF], J. Nd..

GROW ISOLATION OXIDE

(B)

HARD MASK LAVERS PATTERN TRENCH MASKETCH STACK, ETCH TRENCH

- -

REFILL TRENCH DEPOSITED OXIDE PLANARlZE RESIST EROSION DENSIFY TRENCH OXIDE

few micrometers are formed along the active area edges. The porous oxide is formed preferentially along the n + epitaxial layer, electrically isolating the top n-silicon layer from the substrate. Finally, the trenches are refilled with oxide and planarized. The maximum size of an isolated feature is 42 l m in width and unlimited in length. The minimum pitch is 2.8 pm and consists of a 1-pm line and a 1.8-pm gap. The porous oxide thickness is uniformly controlled to 4900 -t 300 A. Measured electron mobilities are equivalent to those of BULK. The subthreshold leakage current is low (a0.1pA/pm width at 5 V), demonstrating complete elimination of the back channel. Several significant contributions have been made recently to the two primary SO1 technologies being considered for volume VLSI device applications: separation by implantation of oxygen (SIMOX) and wafer bonding (as used here, “wafer bonding” includes all of the thinning techniques for producing SO1 which use bonded wafers as a basis). The SIMOX process is illustrated in Fig. 9-12. This process uses a high dose oxygen implantation (10’ oxygen atoms/cm2)into a silicon substrate, followed by high tem-

~i~~~~ 9-11. The ISLANDS process flow.

perature annealing to form a buried oxide. The structure after the implantation is composed of the silicon substrate, a buried oxide, and a single-crystal silicon film. If necessary, the single-crystal silicon thickness can be increased by conventional epitaxy. During oxygen implantation, the wafer is kept at an elevated temperature ( >400°C) in order to minimize the damage to the surface layer. The growth characteristics and physical structure of the buried oxide and the single-crystal silicon produced by the SIMOX process has been studied extensively over the past several years. During the implantation, the oxygen concentration first forms a skewed Gaussian profile, but once the oxygen dose is sufficiently high the distribution becomes flat-topped, with a peak oxygen concentration corresponding to stoichiometric SiO,. It has been found that al-

Figure 9-12. Scheme of SIMOX process.

9.3 Device Isolation

though the SIMOX buried oxide is in many ways similar to thermal oxides, it differs significantly in both conduction characteristics and radiation response. High temperature annealing ( > 1300“C) is performed following the implantation to eliminate crystallographic damage in the surface silicon layer, and to allow oxygen from the tails of the implanted distribution to diffuse to and be incorporated in the SiO, layer. After annealing, the dislocation and stacking fault density in the top silicon layer was quite high, i.e., approximately IO4 to lo6 per cm’. Such high density of dislocations and stacking faults remaining in SIMOX wafers after annealing can cause emitter -collector shorts in bipolar devices, similar to the effects of these crystallographic defects on devices built in bulk material. As a result, SIMOX wafers cannot be used for ULSI bipolar applications. On the other hand, the effects of crystallographic defects in SIMOX material on CMOS devices can be minimized. The majority of applications of SIMOX SO1 technology are found in CMOS devices designed for operation in harsh environments. The typical SO1 materials needed for these applications have buried oxides with thicknesses in the range of 0.4 pm, and silicon layers with thicknesses of 0.3-0.5 pm. The SIMOX process is ideally suited to producing material with these layer thicknesses. Even with the device demonstrations, the major stumbling block for the use of SO1 technology in any large scale applications has been the credibility of supply of high quality SO1 at reasonable costs. A fundamental problem of buried oxide “pipes” are plagued SIMOX wafers. These buried oxide “pipes” are observed as conductive threads of silicon through the oxide. Measurements also showed that there are “partial pipes”, that is, areas which appear as thin oxide regions

427

in the SIMOX materials. The buried oxide pinhole problem has been correlated with particles on the wafers during the implantation step. The “pipes” are a result of the shadowing of specific areas from the oxygen implant by the particles. Eliminating these defects has not been a trivial task since particles can be generated in the clean-up before wafers are implanted as well as in the implanter itself. The wafer bonding process is illustrated in Fig. 9-13. In this process, two silicon wafers which have a very high degree of flatness are used. One, or both, of the wafers are oxidized. The surfaces are then mated, and the composite is annealed to form a single structure. One of the wafers is then used as a handle, and the other wafer is thinned from the back side until only a thin superficial silicon film is left. Several techniques for the thinning process have been used, including both physical and chemical techniques. In some methods, an etch stop is either implanted or diffused into the wafer to be thinned before the bonding process; initial thinning is accomplished by a mechanical process to produce a film in the range of several micrometers thickness. The final thinning is then accomplished by a chemical etch Two Flat Si Wafers

Wafer 1

Wafer 2

I Oxidize, Bond, Anneal

Oxide

Wafer 2

Grind, Polish or Preferential Etch

Wafer 2

Figure 9-13. Scheme of wafer bonding process.

428

9 Silicon Device Processing

back using a preferential etchant and an etch-stop layer. The structure of the superficial silicon films on bonded wafers are expected to be very similar to those of the bulk wafers used in the SO1 fabrication. This is generally found to be the case, at least for superficial silicon layers down to a thickness of a few micrometers. Typical crystal defect densities in bulk silicon are < 102/cm2. With the usual wafer grinding and polishing techniques used for silicon IC substrates, it is difficult to produce uniformities superior to f.0.5 pm. Although thinner superficial silicon layers can be produced with chemical etch stop techniques, this is at the expense of added process complexity and the possible introduction of defects due to the etch stop layer itself. Because it is relatively difficult to control the thickness of bonded wafers within very small ranges, these materials have been primarily applied to bipolar devices. In bipolar circuits, the superficial silicon layer must be essentially free of crystallographic defects, and is typically used to form a deep collector. This requires a thickness in the range of 2-4 pm, with tolerances of f0.5 pm. The wafer bonding approach is ideally suited for this application. Ultrathin bond and etch-back silicon on insulator (BESOI) in the thickness range of 75 to 100 nm offers the potential for performance enhancement in both CMOS and BiCMOS technology (Omura and Izumi, 1990; Shahidi et al., 1991). To be useful however, a very low total thickness variation (ttv) is desirable, typically below 10 nm. With the conventional grinding technology ttvs around 300 nm can be obtained, with ultra-precision grinders even better ttvs are possible (Abe et al., 1992). Nevertheless, conventional grinding technology may be incapable of achieving the ultra-low ttvs which are required by these

new applications. Recently, several polishing techniques have been reported that utilize polish stops to achieve high ttvs with selected patterns. While these techniques are useful, they are expensive and do not yield a generic wafer. A unique plasma thinning technology has been demonstrated to be able to thin the superficial silicon on bonded wafers to thicknesses of 0.3 pm or less, with thickness tolerances of less than fO.O1 pm (Mumola et al., 1992). This may allow bonded wafers to be used for both CMOS and bipolar devices. Bonding of an oxidized wafer to another wafer was proposed by Lasky and coworkers (1985). They developed an ion implanted etch stop technology to thin the device wafers. Mazara (1991) and Hunt et al. (1991) extended this technique to include a double etch stop. A potential high throughput BESOI process that is capable of achieving both intrinsic high quality (both silicon and oxide) and versatility as well as high uniformity was developed by Iyer et al. (1993) using a well-defined and highly uniform etch stop system. The Si-Ge etch stop layers are deposited by low temperature UHVCVD epitaxial techniques (Iyer et al., 1989). After a low temperature joining and bonding process, the device wafer is thinned by moderate ttv grinding, followed by a damage removal step. The device wafer is then selectively etched in high selectivity silicon etch with the etching stopping well within the etch stop system. The etch stop layers are then separately removed in another selective etch. After taking into consideration the uniformity of the epitaxial processes, grinding and etching processes, a ttv that is typically well below 10 nm is routinely achieved with minimal edge loss. Electrical characterization of SO1 films showed superior carrier lifetimes and FET devices characteristics.

429

9.4 Gate Dielectrics

The bonding interfaces must be free of bubbles. Bubbles are mainly caused by particles and adsorbed gases on silicon surfaces such as hydrocarbons. These particle-related bubbles can be eliminated by mating two wafers in an ultra-cleanroom (class 1 or better) or by using a micro-cleanroom set up (Mitani et al., 1991). Bubble generation caused by adsorbed gases can be prevented by degassing before wafer bonding (Mitani et al., 1991). Bonding strength is monotonically increased with increasing the annealing temperature due to atomic phase change at the bonding interface and the thermal flow of oxide at high temperature.

9.4 Gate Dielectrics

CMOS TECHNOLOGY TREND

-ol

0.25 I

As device dimensions continue to shrink, a commensurate reduction in the gate oxide thickness is required, as shown in Fig. 9-14 (Taur et al., 1993), primarily to prevent the short-channel effects. For example, an excessive reduction in channel length without an adequate thickness scaling can result in threshold voltage instabilities due to charge sharing effect as well as excessive subthreshold and off-state currents due to drain-induced barrier lowering and punchthrough. Thus, in order to minimize the undesirable short channel effects while ensuring high performance of the device, gate oxide thickness scaling is a very efficient approach. In other words, by scaling the oxide thickness, the behavior of a MOSFET can be made more long-channel-like. Thin gate oxides ( < l o 0 A) in ULSI MOS applications should meet the following crucial requirements : Low defect density Good barrier properties against impurity diffusion High quality Si/SiO, interface with low interface state density and fixed charge

0.5

0.1 1.0 MOSFET CHANNEL LENGTH (pm)

Figure 9-14. CMOS technology trend.

Stability under hot carrier stress and irradiation Low thermal budget processing Low defect density in the oxide ensures that the number of catastrophic oxide failures at low electric fields is minimum. One method to characterize oxide integrity is breakdown histograms. This well-established method categorizes failure modes as either mode A, B, or C (Sanchez et al., 1989). Mode C failures represent intrinsic oxide breakdown while mode A failures are related to surface foreign material such as unintentional contaminants, impurities and particles. Mode B failures on the other hand are largely related to silicon material crystallographic defects such as as-grown stacking faults and SiO, precipitates and process induced crystallographic defects. Other causes for Mode B failures are listed in Table 9-2.

430

9 Silicon Device Processing

Table 9-2. Causes for B-mode failures in oxide. 1 . Local electric field intensification a. Local oxide thinning b. Residual nitrogen at surface (Kooi effect) 2. Charge trapping of oxide a. Electron trapping water related traps non-bridging oxygen defects dopant impurities b. Hole trapping oxygen vacancy

3. Crystal quality a. Metallic contamination b. Surface roughness c. Oxygen precipitates 4. Process-induced damage a. Reactive ion-etching b. Photoresist ashing

Improved barrier properties are particularly important for p+-polysilicon gated p-MOSFETs. Low interface state density ensures a sharp switching characteristic in MOSFETs. High lateral electric fields in the channel in the downscaled MOSFETs lead to significant heating of channel carriers, resulting in hot carrier effects such as oxide charge trapping and interface state generation. The use of a gate dielectric which suffers minimum damage under hot carrier stress is a promising option in aggressively scaled MOSFETs. Processing techniques such as reactive ion etching (RIE) and some of the future tools such as X-ray lithography can expose gate oxides

to high energy plasma and radiation, which are known to reduce the quality of gate oxides. This imposes the requirement of the radiation “hardness” on thin gate oxides. Finally, low thermal budget is necessary in ULSI in order to minimize the redistribution of dopants by diffusion. The main thrust in the gate dielectric research in recent years has been addressed to the above mentioned issues. Numerous techniques have been suggested to solve one or more of these problems. These techniques can be broadly divided into four categories. The first approach involves variations of pre-oxidation cleaning procedures. The second approach involves process variations of the oxidation process. The third approach, which has received considerable attention over the past decade, is to chemically modify the properties of gate oxides. The final approach is deposition of oxides or formation of stacked layers as gate dielectrics.

9.4.1 Preoxidation Cleaning The fundamental role of a silicon cleaning procedure is to remove from the surface (a) organics, (b) transition metal and alkali ions and (c) particulates. These contaminants, if not removed from the wafers prior to oxidation, can affect the quality of the gate oxide. Common wet cleans and their application are listed below :

etching native SiO, layers

o HF/H,O

removing heavy organics

H,SO,/H,O,

NH,OH/H ,O,/H,O (1 : 1 :5 ) (SC-1)

HCI/H,O,/H,O (SC-2)

Effects of NH,OH/H,O,

(5:l)

removing light organic residue and particles removing metallic species

(1 : 1:5 ) ratio:

High: good for particle removal Low: less surface roughening

431

9.4 Gate Dielectrics

The RCA cleaning procedure, proposed by Kern and Puotinen (1970), is still used widely in its original form or with minor modifications. The cleaning procedure consists of two steps. The first step involves cleaning in a hot, high pH H,O, SC1 solution (H20/H,0,/NH40H = 5 : 1: 1) in order to remove organic contaminants from the silicon surface by oxidation. The second step involves treatment of the silicon surface with a hot, low pH H,O, SC2 solution (H,O/H,O,/HCl= 5 : 1 : 1) to remove the metal contaminants via metal complex formation. An additional intermediate step of dilute H F dip is often used to remove the oxide grown during the first cleaning step. A detailed review of the chronological development of the cleaning processes has been published by Kern (1990). As the oxide thickness is scaled down to below 100 A, the requirements on the cleaning processes have become more stringent. Although RCA or modified RCA clean are adequate in effectively removing the surface contaminants, these cleaning treatments can also lead to surface microroughness due to the presence of alkaline N H 4 0 H solution used. Ohmi et al. (1992) investigated this phenomenon in detail and reported that microroughness causes lowering of breakdown electric field and charge-to-breakdown in gate oxides grown on these surfaces. They suggested the use of a 5 : 1 :0.25 H,O/H,O,/NH,OH solution, rather than the traditional 5 : 1 : 1 mixture in order to prevent the surface microroughness. Optimization of the NH40H/H20,/H,0 ratio in the SCIcleaning has been studied by Meuris et al. (1992). It was found that both metal contamination and particle densities were equal after the complete RCA cleaning for wafers processed using SC1 with different mixtures (NH,OH/H,O,/H,O = 0.1 - 1 : 1 :5).

From this, one would normally expect similar breakdown properties of subsequently grown gate oxides. However, large differences were found in yield. The 0.25:1:5 SC1 mixture results in much higher gate oxide integrity than the 1 :1 :5 mixture due to the Si-surface roughness caused by SC1 solutions. A qualitative model for the action of the SC1-cleaning helps to understand the observations (Meuris et al., 1992). When silicon is exposed to the SC1mixture, the peroxide will oxidize the silicon surface while the ammonia will disperse this chemical oxide; i.e. a chemical oxide layer will continually form and dissolve as a result of the compensating effect of the two chemical components. This process slowly etches the silicon. A high etching rate will increase the particle removal efficiency by undercutting the particles, but will cause a larger surface roughening during 10 min of cleaning. Consequently, it is important to find an optimum between particle removal efficiency and silicon surface roughening. An etching rate of 0.2 nm/ min was found to be the best. New cleaning solutions such as choline are also being used (Kao et al., 1989) with a reduction in defect density in oxides. The metallic contamination on Si wafers after various cleaning treatments is shown in Table 9-3 (Verhaverbeke et al., 1991). In general, a final cleaning step in H F results in lower metallic contamination compared with standard RCA cleaning. Surface metal Table 9-3. Typical metallic contamination after various final cleaning steps followed by DI water rinsing (10" at/cm2) (Verhaverbeke et al., 1992).

RCA HF HF/H,O, BHF

Ca Cr

0.3 0.1 0.6 0.2

8.6 3.8 1.6 1.4

5.1 0.3 2.2 2.6

3.3 0.1 0.2 0.3

0.3 0.06 0.09 3.7

0.4 0.1 1.2 0.7

0.2 0.05 0.3 0.4

432

9 Silicon Device Processing

contamination resulting from SC-1 solutions include the following: -

Fe will form non-soluble iron hydroxide under SC-1 conditions; Iron hydroxide can be removed during SC-2 cleaning; Electrochemical plating of noble metals (e.g..Cu) from HF.

The hydrogenated surface resulting from H F etching allows electrochemical reactions with noble metals to occur. The reaction product is mostly a silicide, a chemical substance very difficult to remove in a subsequent set of chemical cleaning steps. Cu is present in an acid HF-solution with a higher half-cell potential than hydrogen and, therefore, can be deposited on the Sisurface from an HF-solution (Kern et al., 1991). This can be avoided by using highly purified chemicals or by adding small amounts of H,O, to the HF-solution (Ohmi et al., 1991). Contaminants in the chemicals used in wet etching and DI water distribution system have been major sources of metallic impurities which reduce the gate oxide integrity. In a recent work (Verhaverbeke et al., 1991), roles of various metallic contaminants on the gate oxide breakdown properties were studied. Ca was found to interact strongly with the Si substrate, resulting in interface roughness and deterioration of breakdown properties. Whereas Fe was observed to degrade the oxide integrity by forming defect spots during oxidation, A1 was shown to cause damage under the polysilicon gate/SiO, interface. Unlike Fe and A1 contamination, Ca contamination is largely unaffected by the gettering cycle. This is consistent with the fact that Ca is mainly located in the thermal oxide. From these results it can be concluded that for gate oxide integrity, Ca is the most important contaminant. The Ca

contamination can be avoided by using ultra-pure chemicals, ultra-pure distilled (DI) water, a carefully designed DI-water distribution system and by final cleaning with H F (Verhaverbeke et al., 1992). After the last cleaning step with HF, the metallic contamination on the Si-surface is lower on the average than after an RCA-cleaning for the typical metals found after a stateof-the-art cleaning. Owing to their low metallic contamination, HF-dipped surfaces are well-suited for the growth of highlyreliable thin gate oxides. However, hydrophobic surfaces are well-known to be susceptible to particle deposition, particularly during subsequent DI-water rinsing (Table 9-4). These particles can be reduced significantly after oxidation. Table 9-4. Particles on a 5 inch wafer after HF-dip and rinse-dry (Verhaverbeke et al., 1992).

N, manual blow HF-dip/no rinse HF-dip/overflow rinse HG-dipiquick dump rinse

Spin Spin dryer rinsedryer

250 6900

400 3100

500 6100 1200 7600

By adding minute amounts of isopropyl alcohol (IPA) to the HF-solution (Verhaverbeke et al., 1992), the deposition of particles on the Si surface can be prevented during HF-dipping and subsequent rinsing and results in highly reliable oxide layers. By adding 200 ppm or more IPA to the 0.5 YOH F solution, the particle deposition is dramatically reduced. The IPA does not chemically react with the Si surface; it is only physically adsorbed and desorbs readily at moderate temperatures. As the devices become smaller and smaller, there are several serious concerns for wet chemical cleaning. These include:

9.4 Gate Dielectrics

- Particulates generated after cleaning; - Drying difficulties (watermarks) ; - Large amount of hazardous waste chemicals produced; - Inability to clean small contact holes with large aspect ratio; - Incompatibility with certain existing processes ; - Incompatibility with integrated processing. For these reasons, dry cleaning processes have attracted significant attention (Moslehi et al., 1992; Ruzyllo et al., 1989) over the past several years. Advantages of dry cleaning include : -

A "cleaner" process; Gas reactive species have easier access to the wafer surface, capable of penetrating minute, high aspect ratio trenches; Significant reduction in chemical waste disposal ; Can be incorporated in situ for integrated single wafer processing; Removal of metal and organics can be achieved by using UV-enhanced or plasma dry cleaning.

Ruzyllo et al. (1989) reported that the use of UV treatment on wafers in an 0, ambience to remove organic contaminants had no detrimental effect on mean time-tobreakdown ( t b d ) as well as t b d distribution. Kao et al. (1991) used a vapor phase HF/ HCl cleaning procedure and observed a ten-fold increase in tb, for the subsequently grown gate oxides compared to the oxides on RCA cleaned wafers. Kasi and Liehr (1992) concluded that a pre-oxidation high temperature UV/O, treatment can effectively remove the hydrocarbon contamination. f*ckuda et al. (1992) adopted a rapid thermal cleaning approach in which the wafers, initially subjected to H,SO,-H,O, cleaning and 1 % H F dip were treated in

433

either H, or HCl/Ar ambience for various temperatures and durations. It was concluded that the HCl/Ar cleaning removes metallic impurities as well as the native oxide, whereas the H, cleaning is unable to remove the metallic impurities.

9.4.2 Process Dependence of Gate Oxide Quality The impact of gate oxide temperature on the quality of the gate oxides has been investigated by several researchers. For example, in an earlier work, Deal et al. (1967) reported that the fixed positive charge in the oxide decreased nearly linearly with increasing oxidation temperature. Hahn and Henzler (1984) studied the structural and electrical properties of the Si/SiO, interface as a function of oxidation temperature. They reported a strong correlation between the atomic steps at the interface, which were taken as a measure of roughness, and the electrical properties and concluded that high temperature oxidation results in a smoother interface with less interface states and less fixed charge. f*ckuda et al. (1992) also indicated that high temperature (1200 "C) RTP oxidation results in a superior gate oxide with lower interface state density, longer tbd and tighter tbd distribution, as compared to low temperature (800 "C) furnace grown oxide. Walters and Reisman (1990) reported that the density of electron traps in the gate oxide decreased with an increase in oxidation temperature from 800 "C to 1000 "C. Joshi and Kwong (1992) reported that MOSFETs with gate oxides grown at high temperature show improved electron and hole mobility as well as suppressed degradation under radiation and hot-carrier stress, as shown in Fig. 9-15. The improved mobility was attributed to the formation of a smoother interface at elevated

434

9 Silicon Device Processing

Temperature ("C)

5 20

omL

800

' 900

1000

1100

b, v

12cv

TEMPERATURE ("C)

Figure 9-15. (a) Effective electron mobility (perf)for two values of effective electric field (Eeff)in MOSFETs with gate oxides grown at different temperatures. (b) Increase in off-state leakage current (AZd,) and transconductance degradation as a function of gate oxide growth temperature.

temperatures, while the improved reliability was attributed to interfacial strain relaxation by viscous oxide flow at temperatures above 960 "C (EerNisse, 1977). These studies suggest that high temperature oxidation is preferred in order to achieve good performance and reliability in gate oxides. Consequently, rapid thermal oxidation at high temperature appears to be a suitable approach for gate oxide growth in ULSI MOS devices. Apart from the higher growth rate, suppressed number of early breakdown as compared to dry oxides is an attractive feature of wet oxides (Irene, 1978). Wu et al. (1989) observed that wet oxides

show very sharp t b , distributions with 15 x larger t b , values as compared to dry oxides. Li and Chang (1988) used a two step approach to grow gate oxides, with a combination of dry-dry, wet-dry and wetwet processes. The wet-wet process resulted in the minimum defect density. A systematic decrease in the number of low field breakdowns was observed with an increase in wet oxygen partial pressure during oxidation. Recently, wet oxides have been implemented in a 0.8 pm technology and some attractive features have been reported (Wei et al., 1992). The comparison was made between 850°C wet oxide MOSFETs and 900°C dry oxide MOSFETs. The breakdown histograms were comparable in both the cases, unlike the significant improvement for wet oxides reported in earlier studies. A 10% increase in linear transconductance was observed in n-channel MOSFETs with wet gate oxides. However, in p-channel MOSFETs, where electron trapping during hot carrier stress is the dominant degradation mechanism (Koyanagi et al., 1984), wet oxide devices are somewhat worse than dry oxide devices. The use of high pressure oxidation was suggested for growing thick field oxides, e.g., in a LOCOS isolation (Baglee et al., 1984). The major advantage of high pressure oxidation is an enhanced growth rate as compared to atmospheric pressure oxidation. If atmospheric pressure oxidation is used to grow thick field oxide necessary to provide isolation between adjacent MOSFETs, high temperature/long duration processing is necessary. For example, a 3000 8, field oxide can be grown by wet oxidation at 1000°C in about 2 h. Such a high thermal budget is not desirable in ULSI processing due to redistribution of dopants by diffusion. For example, channel width narrowing due to the encroach-

9.4 Gate Dielectrics

ment of channel stop implants into the active regions has been reported by Baglee et al. (1984). Due to the enhanced oxide growth rate, high pressure oxidation can be performed within a considerably smaller thermal budget either by lowering the oxidation temperature or by reducing the growth time. Since thermal budget reduction is crucial in ULSI processing, Tay et al. (1987) applied high pressure oxidation to grow gate oxides. At a pressure of 10 atm, an 120 8, thick gate oxide was grown at as low a temperature as 700°C. The pressure ramp-up was performed in N, ambience in order to avoid nonuniform oxide growth on wafers due to temperature instabilities. These oxides shows low interface state densities in the 1010 eV-' cm-, range. In a more recent work (Tay et al., 1990), the same research group demonstrated that high pressure oxidation at 700 "C followed by nitrogen annealing at 900 "C results in gate oxide films (80 8,) with up to 15 MV/cm breakdown field and high quality Si/SiO, interface. In an earlier work, it has been indicated that high pressure oxides and conventional oxides grown at atmospheric pressure show similar radiation response (Gupta et al., 1980). Although the high pressure gate oxidation technique appears to be attractive due to its low thermal budget, a more detailed investigation is required to judge its applicability to ULSI MOS processing, especially regarding the MOSFET reliability.

9.4.3 Chemically Modified Gate Oxides

Over the past decade, a considerable amount of work has been reported on chemically modified gate oxides for MOS applications. The main goal of chemical modification is to introduce controlled quantities of impurities such as nitrogen or fluorine primarily at the Si/SiO, interface

435

to improve the interfacial properties that are critical to the performance and reliability of SiO, . The Si/SiO, interfacial region consists of a non-stoichiometric monolayer followed by a 10-40 8, thick strained SiO, (Grunthaner and Maserjian, 1978). The non-stoichiometric monolayer results from incomplete oxidation and the strained region is due to lattice mismatch between Si and SiO,, which causes a compressive strain in the interfacial SiO, . Relaxation of intrinsic strain at the Si/SiO, interface is an important technique to improve the reliability of MOS devices under electrical or radiation stresses. It is known that tensile strain exists in Si3N4 in the Si3N4/Si system. This led to an approach which involves incorporation of a small amount of nitrogen in the interfacial region so as to oppose the compressive strain (Vasquez and Madhukar, 1985). Strain relaxation in such nitrided oxides is probably due to the formation of Si,N,O (Vasquez and Madhukar, 1986). Triangular planer bonding in Si,N,O allows a smoother transition from the tetrahedral bonding in silicon to amorphous SiO,. In addition, since the Si-N bond strength is significantly higher than that of Si-H bonds, defect generation by hot carriers and ionizing radiation is suppressed. The other important advantage of introducing nitrogen into SiO, is the improved diffusion barrier properties to boron penetration, an extremely important requirement for p -polysilicon-gated surface-channel p-MOSFETs (Lo and Kwong, 1991). Incorporation of fluorine at the Si/ SiO, interface is another approach to modify the properties of MOS system. Fluorine has been suggested to satisfy some of the dangling bonds at the Si/SiO, interface (Wright and Saraswat, 1989). In a conventional process, the dangling bonds are satisfied by hydrogen during the sintering step. Since the bond strength of Si-F +

436

9 Silicon Device Processing

bonds (5.73 eV) is significantly higher than that of Si-H bonds (3.17 eV), defect generation by hot carriers and ionizing radiation is suppressed. Moreover, fluorine incorporation leads to strain relaxation at the interface (da Silva et al., 1987). Both these approaches to chemically modify thin oxides have been extensively studied. Annealing of gate oxides in NH, (It0 et al., 1982a; Lai et al., 1983) has been reported to achieve such desirable properties as good resistance against impurity diffusion (It0 et al., 1982a) and endurance against hot electron stress (Lai et al., 1983). Rapid thermal nitridation (RTN) is an attractive approach due to its low thermal budget requirement and good control over the resulting nitrogen profile (Mosleh and Saraswat, 1985). Reoxidation (Hori et al., 1989; Yang et al., 1988; Dunn and Scott, 1990; Joshi et al., 1992) or inert gas annealing (Wright et al., 1990) was proposed to reduce electron trap and fixed charge density in the nitrided oxides while still retaining the nitrogen-rich layer at the Si/SiO, interface. However, the electron traps induced by residual nitridation cannot be eliminated completely by reoxida-

tion or annealing, resulting in worse reliability in p-channel MOSFETs (Momose et al., 1991). The reoxidized nitrided oxides used in this case were prepared by rapid thermal processing after the conventional oxide growth. It turned out that reoxidized nitrided gate oxides are superior to pure oxides in numerous aspects. However, the presence of residual nitridation induced electron traps is a shortcoming in these dielectrics and, as a result, pMOSFET reliability is worse than that of the conventional gate oxide MOSFETs. The disadvantage can be avoided by using light N H ,-nitridation, but such light nitridation may not be sufficient to prevent boron penetration into the channel region. This trade-off is depicted in Fig. 9-16 (Momose et al., 1991). Compared to NH,-based processes, the N,O-based processes have an important advantage in addition to the process simplicity, Le., the elimination of any hydrogen-containing species during processing. Therefore, the hydrogen-related disadvantages can be avoided. Depending on process design, thermal budget limitation, and device applications, several processes have

Figure 9-16. Performance and reliability of RTN/ RTO S O , as a function of nitrogen concentration.

9.4 Gate Dielectrics

been developed to use the significant advantages offered by N,O process. These include

500

437

1 L

Oxidation of Si in pure N,O (Lo et al., 1991); Nitridation of thermally grown SiO, in N,O (Ahn et al., 1992a); Densification and Nitridation of CVD SiO, in N,O (Ahn et al., 1992b); Nitridation of N,O oxides in NH, for p+-poly-Si gated P-MOSFETs (Yoon et al., 1993).

Figure 9-17. Comparison of the growth kinetics between N,O and 0, oxidation of Si.

The oxidation process is self-limiting compared with 0, oxidation, as shown in Fig. 9-17, allowing growth of ultrathin oxides with excellent thickness controllability. The process is simple, hydrogen-free and easy to integrate into modern ULSI processes. Because of nitrogen incorporation at the Si/SiO, interface during N,O oxidation, the resulting oxynitrides show lower hole trap density, reduced electron trap generation under high-field stressing, and reduced interface state and neutral trap generation under both hot-carrier stressing and X-ray irradiation in comparison to the control oxide. NH, nitridation of N,O-oxides does not reduce electrical and reliability properties of N,O-oxides, with the additional advantage of significantly improved resistance to boron penetration. Finally, study of hot-carrier related reliability in both n- and p-MOSFETs with N,O-based gate oxides under application specific stress conditions such as for SRAM-type pass transistors, CMOS logiccircuit transmission gates and CMOS analog devices shows that all the hot-carrier induced damages (Le., interface states, electron/hole trapping, and neutral electron traps) are greatly suppressed in N,Obased gate oxides compared with control oxide devices (Yoon et al., 1993). These results suggest that N,O-based gate oxides

are promising for numerous MOS ULSI applications. Fluorine incorporation in the gate oxide has been performed by different techniques, such as immersion of Si wafers in H F prior to gate oxidation (Nishioka et al., 1988), F ion implantation (Lo and Kwong, 1991 ; Nishioka et al., 1989) and NF, purge during or before gate oxidation (Lo et al., 1992). Different techniques produce different distributions of fluorine in the gate oxide, resulting in a wide variation of electrical properties. Since excessive fluorine incorporation in the oxide can lead to worse dielectric properties (Lo and Kwong, 1991; Nishioka et al., 1989), excellent control over the amount of incorporated fluorine is necessary which can be achieved by rapid thermal processing (RTP). Fluorination has been reported to increase fixed positive charge but suppress interface state density (Nishioka et al., 1989; Lo et al., 1992). Wright and Saraswat (1989), on the other hand, reported a negative charge in the fluorinated oxides. The reduction in interface state density has been attributed to passivation of dangling bonds at the Si/SiO, interface by fluorine (Wright and Saraswat, 1989; Nishioka

300 400

100 0

200

" " " ' " " ' " " ' " ' ' 1 " '

100 120 140 160

Oxidation Time (min)

438

9 Silicon Device Processing

et al., 1989: Lo et al., 1992). whereas the increase in positive charge is due to the formation of nonbridging oxygen defects by incorporation of fluorine in the oxide. Wright and Saraswat (1989) reported that the hot electron induced degradation in MOSFETs is considerably suppressed with an increase in the amount of fluorine incorporated in the gate dielectric. Lo et al. (1992), on the other hand, reported that both the amount and distribution of fluorine in the gate dielectric affect the hot carrier reliability of fluorinated oxides. Only a small process window was observed to result in improved hot carrier reliability as well as radiation hardness as compared to pure oxides. Moreover, the presence of fluorine at the Si,SiO, interface was found to be essential in order to realize a gate dielectric with superior reliability. The improvement in radiation and hot carrier immunity in fluorinated oxides has been mainly due to suppressed interface state generation. Interfacial fluorine incorporation has generally been accepted as a cause for the improvement (Ma and Dressendorfer. 1989). 9.4.4 CVD and Stacked Oxides

Deposition of gate oxide, rather than its growth from the substrate, is an attractive technique to suppress the density of defectrelated breakdowns in oxide films because the deposited oxides are less likely to be affected by the defects from the Si substrate. Another advantage of this technique is the feasibility of low temperature processing, which is an attractive feature from the viewpoint of stringent thermal budget requirements in ULSI MOS processing. Various CVD oxides such as TEOS, HTO, and LTO have been studied (Tseng et al., 1993). Ahn et al. (1992b) investigated hot-carrier reliability of MOSFETs with

z 65 8, LPCVD gate oxides (silane and oxygen reaction) annealed in presence of N, . The compressive stress in the films after post-deposition annealing was observed to be smaller than conventional thermal oxides, and was suggested to be the cause of improved current drive capability as well as hot-carrier reliability. In a recent report (Ahn and Kwong, 1992), N 2 0 post-deposition is used instead of the conventional N, annealing in order to incorporate a small amount of nitrogen at the Si/SiO, interface. The resulting films show superior hot carrier reliability due to nitrogen at the Si/SiO, interface as well as low defect density due to the deposition of oxides, rather than growth from substrate. Roy et al. (1988) studied oxide films containing a stack of a “pad” oxide and a CVD oxide on top of it. The dramatic reduction in defect density observed in this stack layer was mainly attributed to misalignment of defects in individual components of the stack. Moreover, the stress at the Si/Si02 interface is close to zero due to the stress compensation between component layers. Kawamoto et al. (1987) demonstrated stacked layers with performance comparable to thermal oxide films. 0 stacked Tseng et al. (1991) used ~ 1 4 8, CVD oxides (40 8, thermal oxide and 100 8, LPCVD/TEOS) for 0.5 pm CMOS process and demonstrated several advantages. Firstly, the number of low field breakdowns was significantly smaller than for the conventional thermal oxides. In addition, due to the smaller levels of stress at the SiiSiO, interface, a large reduction in process induced damage was observed. An optimum ratio of bottom thermal oxide thickness to the top CVD oxide thickness was reported to achieve longer time-tobreakdown and lower defect density. The optimum ratio is a consequence of the compensation between the intrinsic defect

9.5 Shallow Junction Formation

densities of the two layers and the mismatch mechanism. The use of oxide and Si,N, in a gate dielectric stack (ON (oxide/nitride) or O N 0 (oxide/nitride/oxide)) can yield two advantages. Firstly, as in the case of stacked CVD and thermal oxide, the misalignment of micropores in the individual components acts as an effective “seal” to prevent the early gate dielectric failures (Roy et al., 1988). Secondly, the use of Si,N, increases the effective dielectric constant of the film and serves as effective barrier against boron penetration. Iwai et al. (1990) studied the hot carrier immunity of MOSFETs with stacked ON gate dielectrics. It was observed that by reducing the top nitride thickness to about 3 0 & the charge trapping in stacked layers can be significantly reduced and can be comparable to a conventional thermal oxide film. Dori et al. (1987) used ON dielectrics for a dual gate process and demonstrated that the top nitride layer is an effective barrier against boron penetration, which facilitates the fabrication of p +-polysilicon gated p-MOSFETs. In addition, these dielectrics showed a tighter E,, distribution than the conventional thermal oxides. Reduction in electron trapping by reducing the top nitride layer thickness was reported, as also stated by Iwai et al. (1987).

439

9.5 Shallow Junction Formation A significant requirement in high-performance semiconductor technologies is CMOS source/drain junction depth reduction to suppress MOS punchthrough leakage and to minimize device short channel effects such as drain-induced barrier lowering (DIBL) in CMOS devices. Device junctions with relatively high surface dopant concentrations, ultra-shallow depths, low contact and sheet resistances, and low junction leakage currents will be critical for advanced CMOS technologies. It has been projected that ultra-shallow junctions with junction depth <60 nm will be required in the source/drain regions of MOSFETs for L,,,=0.25 pm devices. By 2010, Le,, is expected to reduce to 0.1 pm geometries, with a concomitant reduction of junction depth, Xj, to 10 nm and junction leakage current to 0.1 nA/cmZ(Table 9-5). In concert with the reduction of junction depths, the surface doping concentration (N,,,,) in the source/drain junctions immediately next to the channel is expected to reduce from lo1’ cm-, to (5-10 x lo1’ cm-,. The reduction of Xj is dictated by short-channel effects while the reduction of Nsurf is mandated by the high fields near the pinch-off region which cause adverse hot carrier effects. The

Table 9-5. Evolution of MOS S/D junction technology requirements. Le,, (w)

vom Xj (nm) Nrurf (Cm-3) Nchannel (cm - 3, Junction leakage (nAtcm’)

0.5

0.35

0.25

0.18

0.12

0.10

5 120 1Ol8 mid IO1’ 1

3.3

2.2

100 10l8 mid IOl7 0.8

2.2 40 (7-10) x 1017 8 x 1017 0.1

1.5 25 (5-10) x lo” 10’8 0.1

1.5 10 10 x 10” 1018 0.1

10l8 6 x 1017

0.2

440

9 Silicon Device Processing

simultaneous reduction of Xjand Nsurfresults in an excessive increase in the sheet and spreading resistance and, therefore, the sourceidrain series resistance. 9.5.1 Ion Implantation

Ion implantation has been the technique of choice for forming shallow junctions. The junction depth is controlled by the implantation energy and subsequent diffusion steps, A lower limit on implantation energy is imposed by reduced beam current, and the lower limit on the diffusion temperature is set by the necessity to anneal implantation damage, activate dopants, and avoid transient enhanced diffusion of dopants during annealing (Fair, 1988; Morehead and Lever, 1986; Sedgwick et al., 1988; Kim et al., 1991). Current generation commercial implanters do not routinely go down to energies much below 10 keV. At extremely low energies (1-10 keV) (Davies, 1985; Hong et al., 1988; Bousetta et al., 1991), there are problems of beam stability and low beam currents (which cause throughput problems). The projected range of commonly used species, such as B for p-type doping, are too deep for formation of ultra-shallow junctions using current generation implanters. Although the problems are somewhat alleviated by using BF, instead of B for p-type, the projected ranges at the lowest currently available energies ( = 10 keV) are still too large. Also, there are problems associated with the straggle, lateral straggle and channeling in tightly controlling the as-implanted profile to achieve junction depths below 6 0 n m . Finally, since there is damage associated with the ion implant, it is necessary to anneal it out using the lowest possible thermal budget. There are tradeoffs in terms of the mini-

mum acceptable dopant diffusion (which increases with thermal budget) and junction leakage (which decreases with increasing thermal budget). Residual defects not only increase junction leakage via SRH generation-recombination sites, but can also cause enhanced gate induced drain leakage (GIDL) in MOSFETs. It can be enhanced by residual trap sites which cause defect-assisted tunneling. Driven by a need for lower thermal budgets, there has been a shift from furnace annealing to rapid thermal annealing (RTA). However, the thermal dissolution of these defect clusters produce excess point defects (vacancies and silicon interstitials), which give rise to the phenomena of transient enhanced diffusion of dopants (Fair, 1988; Morehead and Lever, 1986; Sedgwick et al., 1988; Kim et al., 1991) observed in the initial stages of the annealing process. In other words, as the Dt product of the RTA is decreased by reducing the temperature ( T ) or time ( t ) , the broadening of the implanted profile cannot be reduced below a certain value which is governed by thermal, defect-assisted diffusion. An alternative solution has been proposed and demonstrated for p+-n shallow junction formation. By implanting an electrically inactive species, such as Si or Ge, to form a fully amorphous surface layer, the channeling effect can be removed (Bousetta et al., 1991; Ruggles et al., 1989). In addition, the fully amorphous layer would result in a better quality crystal after annealing compared to heavily damaged implant layers. The leakage current and final junction depth of the pre-amorphized junctions is very sensitive to the amount of post-annealing residual damage and its location relative to the junction. Although the epitaxially regrown region is free of extended defects, a high density of dislocation loops form on the crystalline side of

9.5 Shallow Junction Formation

the original amorphous/crystalline (a/c) interface. The position of this interface relative to the junction region will determine the amount of leakage current and enhanced diffusion observed (Sedgwick et al., 1988; Brotherton et al., 1989). If the defect region is in the vicinity of the junction, then both leakage current and dopant diffusion increase. Therefore, the tail of the impurity profile must be carefully controlled in order to avoid the damage region near the ajc interface. The question of whether a particular amorphizing species (Si', Ge', Sb', In', Sn', F') has a different effect on defect formation over another species has been investigated by many research groups. A systematic study by Brotherton et al. (1989) and Ruggles et al. (1989) revealed no difference in boron diffusion in Si', Ge', and Sn' preamorphized substrates, but Tanaka et al. (1991) and Ajmera et al. (1986) found that Ge+ preamorphization produced fewer end-of-range defects and had lower leakage current than Si' preamorphized samples. Sb, although of the opposite conductivity type to boron, can also be used for pre-amorphization. Sb is much heavier than both Si and Ge, and

44 1

therefore produces a sharper crystalline/ amorphous interface so that the defects can be controlled with minimal thermal budget. The estimated concentration required for amorphorization with Sb is about one order of magnitude less than Ge (Davari et al., 1989). In addition to forming an amorphous region, n-type Sb compensates the boron in the tail region, resulting in a sharp junction. The end of range dislocation loops are annealed out for heat cycles as low as 950 "C and 10 s for an Sb dose and energy of 1 x IOl4/cm2, 40 keV, which produces a 60 nm amorphous layer. Davari et al. (1989) fabricated p'/n junctions by implanting boron into Sb-pre-amorphized layers, followed by annealing. The experimental conditions and junction characteristics are shown in Table 9-6. Shallow junctions with lower leakage current and fewer end-of-range defects than Si+ pre-amorphization were achieved. A 600 A deep p'jn junction has been fabricated by Sb pre-amorphization and low energy BF, implantation [13]. Although the exact mechanism which causes the difference in defect structure in not known, it is certain that the density and position of the end-of-range defect

Table 9-6. Experimental conditions and junction characteristics of p +-n junctions fabricated by antimony pre-amorphization.

No. 1 2 3 4 5 6 7 8 9 10

Ion/energy/dose (keV, atoms/cm2) Sb/40/1 x Sb/40/1 x sb/40/1 x Sb/40/1 x Sb/60/3 x sbpo/i x sb/40/1 x sb/40/i x sb/40/i x Si/30/1 x

1014 1014 ioi4

1014 1014 10i4 ioi4

1014 1014 1015

Boron dose (atoms/cm2) ix 1 1 2x 2x 1 1x 2 1 2

1015 1015 1015 1015 IO'S 1015 1015 1015 1015 1015

Annealing ("C, SI 800/300 900jlO 950110 950110 950110 lOOO/l 0 800/1800 800/900 0

x, (nm)

85 90 95 105 50 110 110 115 75 75

(WD) 123 192 197 170 156 160 399 230 120 90

Z@(-5.0V) (nA/cm2) 265.0 8.0 7.5 4.7 1.3 x 104 2.7 100.0 3.6 2.0 x 106 4.1 x 10'

442

9 Silicon Device Processing

with respect to the dopant profile play key roles in determining the amount of enhanced diffusion observed. If the defect region is in the vicinity of the junction, leakage current and enhanced diffusion due to Si interstitials increase, and a higher density of dislocation loops at the a/c interface allow fewer interstitials to pass through into the regrowth region from the crystalline side. Therefore, careful defect engineering is required. Fluorine is known to segregate near defect sites and therefore acts as a marker for defects, such as in BF, implantation (Tsai et al., 1978). Ohyu et al. (1990) and Ando et al. (1990) performed FiB dual-implantation and observed a reduction in boron diffusion. They explained that the fluorine immobilized the Si interstitials which cause the enhanced diffusion of boron. Fluorine post-implantation has been shown to reduce phosphorus and arsenic diffusion (Kato. 1990). reduce leakage current, and decrease the hot-electron induced interface trap density in MOS capacitors as well (Ohyu et al., 1990: Nishioka et al., 1988). The improvement in electrical properties was believed to arise from the termination of dangling bonds by the fluorine, thereby reducing the trap density, or the stress state of the SiiSiO, interface was affected by the presence of fluorine. By combining fluorine pre-amorphization with low energy (10 keV) BF, implantation. the advantages of implant channeling elimination and diffusion retardation in the tail region were realized by Ando et al. (1990). Shallow n * -p junctions have been fabricated by using As, As,, and Sb implantation followed by RTA or low temperature furnace annealing. Shibata et al. (1990) was able to fabricate a 60 nm, low reverse current junction by simply implanting 2 x 1015cm-, dose As at 25 keV and annealing at 450’C for 5 h. Instead of using

As, Sb was implanted at 35 keV (10 keV), 4 x 1014cm-2 dose by Sai-Halasz and Harrison (1986) to fabricate a 80 nm (65 nm) n’/p junction after 16 min annealing at 950 “C. Their electrical characteristics showed very low leakage and low sheet resistivity. In comparison with As, Sb has smaller diffusion coefficient and its concentration enhancement is also less pronounced. For a given mean ion implant depth, Sb has less straggling. The lateral straggle at mask edges is even more significantly diminished. This is critical to deep sub-micrometer MOSFET structures where the source/drain junction edges must be as abrupt as possible. Dual-implant techniques can be applied towards n + - p junction formation. Phosphorus was implanted into Sb-preamorphized Si by Harame et al. (1991). Using As, ion implantation instead of As’ ions and rapid thermal annealing, 40 nm n’-p junctions with very low leakage current ( < 0 . 5 nA/ cm2) up to 2 V reverse bias have been realized by Park et al. (1982). 9.5.2 Advanced Techniques for p+-n Junction Formation

The main disadvantage associated with ion-implantation is the residual defects remaining near the critical junction area and the need for high temperatures to eliminate them. Various techniques have been attempted in order to overcome the difficulties associated with the fabrication of shallow p+-n junctions using ion implantation. These include: Diffusion from doped deposited layers Epitaxial Si, Ge, and Si,-,Ge, Polycrystalline Si and Si - xGex Silicide Borosilicate glass (BSG) Spin-on oxide Gas-immersion laser doping

9.5 Shallow Junction Formation

Gas phase diffusion Plasma immersion ion implantation

9.5.2.1 Diffusion from Doped Deposited

Layers The advantage of using doped layers above the contact region as a diffusion source is that the diffusion profile in the substrate has a high surface concentration and is very steep without the characteristic channeling tail observed in ion-implantation. When using a constant diffusion source, the surface layer is highly doped so that the dopant concentration at the sourceisubstrate interface is above the solid solubility for that particular annealing temperature. Various materials have been used as a diffusion source for shallow junction formation: epitaxial and polycrj stalline Si, crystalline and polycrystalline Si, -xGex, spin-on oxide, borosilicate glass (BSG), and silicide. Due to the presence of high diffusivity paths along the grain boundaries of polysilicon, dopant diffusion within the poly-Si is fast compared to that in the single crystal silicon, and therefore, dopant distribution is uniform within the poly-Si. Since only mobile dopants can diffuse into the Si substrate, the surface concentration is fixed at the solubility limit for the annealing temperature. Another factor in poly-Si source diffusion is that the transport of dopant from the poly-Si into the single crystal silicon can be greatly affected by the nature of the poly-Si/Si interface. For example, an interfacial oxide will create a barrier for dopant diffusion into the substrate (Raicu et al., 1990). In situ arsenic doping of poly-Si for shallow (40-50 nm) n+-p junction formation has been demonstrated by Hsieh et al. (1990) using rapid thermal CVD (RTCVD). Georgiou et al. (1990) investi-

443

gated the p+-n junction formation through BF, implantation into LPCVD deposited poly-Si. Poly-Si has also been applied in the fabrication of shallow emitters in bipolar transistors (Nouri and Scharf, 1992); Hamel et al., 1992). Si, -xGex can be used as an alternative diffusion source, with the added advantage of increased selectivity of Si, -,Ge, deposition between Si and SiO, compared with poly-Si deposition (Grider et al., 1991; Sanganeria et al., 1991). The process sequence and diffusion behavior is similar to that of the poly-Si diffusion source. Grider et al. (1990) selectively deposited Si, -xGex (x = 0.3) by RTCVD followed by 10 keV boron implantation to form a 40 nm p+-n junction. When device dimensions are downscaled to 0.25 pm or less, it becomes increasingly necessary to use metal silicides, self-aligned (SALICIDEs) to the diffusion areas to reduce contact and interconnect resistance which become comparable with the channel resistance (Osburn, 1990). Since silicon consumption during silicide formation is a part of the junction depth, both the silicide thickness and the diffusion of dopant beyond the silicide should be minimized. Compared to the conventional SALICIDE process in which junctions are formed before silicide formation, dopant diffusion from titanium and cobalt silicide layers into silicon substrate, the silicide-as-diffusion-source (SADS), has received much attention. In this process, the silicide is formed before the junction. Dopants are then implanted into the silicide, followed by RTA drive-in to diffuse the dopants into the substrate. This process has the potential of minimizing the diffusion length beyond the silicide and produces a junction that follows the contours of the rough silicide/% interface so that the junction is not locally penetrated and shorted.

444

9 Silicon Device Processing

A novel SALICIDE technology uses rapid thermal annealing and ion-beam induced interface mixing for self-aligned Ti silicide formation, and a doped silicide as diffusion source for shallow junction formation (Ku et al., 1990). The ion-beam mixing can break up the native oxide at the TijSi interface and achieve interface mixing that enhances the Ti-Si reaction rate and results in a smooth silicide surface. The detailed structure and process steps of this technology are shown in Fig. 9-18. After polysilicon gate patterning and oxide spacer formation, a layer of titanium was sputter deposited on the wafers. These wafers were then implanted with "Si' ions to achieve interface mixing. The wafers were then first annealed at a relatively low temperature in the presence of

Gate oxide n-

,-'

p-Si 750A titanium deposition

Si ion-implantation

si+

Low temperature RTA (650'C, 30s in Selective etching High temperature RTA in N2

As ion-implantation CVD oxide deposition

BPS

Figure 9-18. Process sequence of SALICIDE technique using ion-beam mixing, doped silicide and RTA.

nitrogen using RTA. The titanium nitride and unreacted Ti were then selectively removed followed by a high temperature RTA in an NH ambience for contact barrier formation. Suitable impurity ions are then implanted into silicide layers for shallow silicided junction formation. After BPSG deposition, high temperature RTA is used to drive-in the implanted ions from the silicide layers into the Si substrate as well as to anneal the BPSG layer, followed by contact opening, A1 sputtering and sintering. In general, this technology has several significant advantages over other techniques including enhanced Ti-Si reaction rate, improved surface morphology, and smoother silicide/Si interfaces due to the suppression of the native oxide effects at the TijSi interface, and the formation of the same silicide thicknesses on both nand p-channel devices. By controlling the subsequent drive-in conditions (RTA time/ temperature), silicided shallow junctions with sufficiently high carrier concentration at the silicide/Si interface were achieved (Ku et al., 1989). The p'/n diodes and LDD p-channel MOSFETs with Ti SALICIDE structures fabricated using the doped silicide technique showed excellent electrical characteristics (Ku et al., 1988). There are several critical issues associated with SADS processes, however. The implantation of dopants into very thin silicide films is limited by the channeling of boron through the polycrystalline silicide. In addition, the dopant concentration at the silicide/Si interface varies with the dopant redistribution in the silicide/silicon system which is determined by the complicated interactions of diffusion within the silicide, surface segregation, and the extensive loss of dopant via evaporation. In Fig. 9-19, SIMS profiles are shown for diffusion of boron and arsenic from various

9.5 Shallow Junction Formation

012

ti3

implanted silicides into Si (Maex et al., 1991). The depth scale of the SIMS profiles starts at the silicide/Si interface. As can be seen, out-diffusion of dopants from CoSi, and MoSi, is much easier than in the case of TiSi, and TaSi, , In the case of Ti%, , formation of metal dopant compound precipitates (TiAs and TiB,) has been observed during annealing in the implanted TiSi, layer and at the TiSi,/Si interface (Probst et al., 1988). The defect clusters in the implantation-damaged zone may act as nuclei for the formation of metal dopant compounds during drive-in annealing. This compound formation results in dopant immobilization and thus low carrier concentration at the TiSi,/Si interface. As a consequence, the contact resistance between p-n junctions and TiSi, is unacceptably high, especially for boron. Finally, material characterization and dopant profiling are becoming increasingly difficult when both the silicide thickness and the junction depth are only tens of nanometers.

445

Figure 9-19. SIMS profiles in Si after diffusion of (a) B and (b) As from various diffusion sources upon furnace treatment. The origin of the depth axis is the silicideiSi interface.

Takemura et al. (1987) demonstrated the use of borosilicate glass (BSG) to fabricate shallow emitters. BSG and doped poly-Si emitter technologies are combined to fabricate the base and emitter regions, respectively. After the window has been etched over the emitter region, BSG film is deposited by CVD over the entire wafer. Boron drive-in is done by RTA to form the intrinsic p- base region. The BSG film is removed by reactive ion etching, leaving behind boron doped sidewall spacers around the emitter window. Then, n + poly-Si is deposited and annealed to form a shallow emitter junction. The BSG spacers allow the formation of p + regions, which naturally link the intrinsic and extrinsic base regions. The resulting boron profile is very steep, and the base resistance can be controlled by adjusting the boron concentration in the BSG film. M. Saito et al. (1992) applied solid state diffusion process and RTA to fabricate 0.1 pm PMOS with ultra-shallow junctions. The schematic diagram of the solid-

446

9 Silicon Device Processing

1 / 1 (BF2) 15 keV 4 x i oi3cm.* 1000°C 15sec 1000°C 3sec 950°C 15sec

c 10

.-c0

(

SPD ( B S G )

s * 10

4 x10~’crn-~ 0

i00nm iOOO°C 15sec

phase diffused drain PMOS structure is shown in Fig. 9-20. The highly doped BSG sidewall is used as the diffusion source for the ultra-shallow junction formation. The junction is extremely shallow compared with those formed by BF, implantation, as shown by the SIMS profiles. Unlike other solid source diffusion materials, the deposition of spin-on films can be done at room temperature. which therefore eliminates one thermal cycle. Usami et al. (1992) used spin-on phosphorus doped oxides and polymeric-boron doped films to obtain very shallow junctions. By controlling the RTA parameters and the amount of B and P i n the doped film, ultra-

Figure 9-20. (a) Solid phase diffused drain structure. (b) Boron SIMS profiles.

shallow junctions 50 nm deep and less were fabricated. The junction depth was found to increase with temperature, heating rate, and surface concentration. The effect of heating rate on the enhanced diffusion of B and P was attributed to the formation of point defects at the film/substrate interface due to the difference in thermal expansion coefficients. These ultra-shallow junctions, however, exhibited very large leakage and required a second annealing process (SOO’C, 60 s) to remove defects. Although this reduced the leakage current, the junction depth nearly doubled to x 100 nm after the second annealing process.

9.5 Shallow Junction Formation

9.5.2.2 Gas Immersion Laser Doping Gas immersion laser doping (GILD) incorporates the dopant into very shallow layers using a melt/regrowth step to drive in a gas phase surface adsorbed impurity (Carey et al., 1985; Kat0 et al., 1987; Sameshima et al., 1987). Usually a doping gas is enclosed in the chamber during the laser irradiation. The incident laser fluences cause the the silicon to melt and simultaneously create dopant atoms by photolysis or pyrolysis of the doping gas molecules. Then dopant atoms are incorporated into a shallow molten region by the liquid-phase diffusion. Finally, the molten region is recrystallized in the way of liquid-phase epitaxy, and the doping process is completed. Pulsed excimer lasers such as XeCl operated in the ultraviolet wavelength region are often used for laser doping. Since single-crystal silicon has a large absorption coefficient at the ultraviolet region (Jellison and Modine, 1982), the incident laser fluences are absorbed extremely close to the surface of the silicon substrate ( z 20 nm). It is only able to melt a shallow region, resulting in very shallow junctions. Dopant atoms are known to be supplied mainly from the adsorbed layers formed either prior to the laser irradiation or during the irradiation (Bentini et al., 1988; Matsumoto et al., 1990; Landi et al., 1988). The formation of the adsorbed layers is sensitive to the surface state of the sample and the pressure of the doping gas (Matsumoto et al., 1990; Foulon et al., 1989); this is the reason for the rather poor control of sheet resistances and junction depths as compared with the ion-implantation technique. In order to control the sheet resistance, a two-step doping process consisting of the deposition of a doping source and the incorporation of dopant

447

atoms in silicon in a successive process was developed (Inui et al., 1991).

9.5.2.3 Gas Phase Diffusion Recently, a novel approach based on surface chemical adsorption and solid state diffusion has been developed (Nishizawa et al., 1990a, b; Kiyota et al., 1991, 1992; Inada et al., 1991) for very shallow, high quality p+-njunction formation. This process consists of three steps: (1) removal of native oxides from the Si surface by thermal annealing in H,, (2) formation of an adsorbed boron layer on the Si surface by supplying 5 % B2H6 diluted in nitrogen, and (3) solid phase diffusion of boron atoms from the adsorbed boron layer into the Si substrate in a hydrogen environment. Boron atoms are incorporated into Si by diffusion in an oxygen-free atmosphere at a relatively low temperature. This process differs from the conventional diffusion process in which boron diffusion is performed in an oxygen-rich ambience. Results show that the boron concentration in the adsorbed boron layer on the Si surface exceeds the solid solubility of boron in Si. In addition, ultra-shallow p+-n junctions (junction depth x 700 A) with excellent electrical characteristics (leakage current < 2 x A/pm2 at 5 V) have been achieved (Kiyota et al., 1991). Ultra-thin base (base width < 25 nm) bipolar transistor with excellent performance has also been demonstrated (Inada et al., 1991). The formation of an adsorbed boron layer on S O , was also examined and results showed that the total amount of boron adsorbed onto the SiO, surface was less than 1 % of that adsorbed onto the silicon surface, indicating selective doping.

448

9 Silicon Device Processing

9.5.2.4 PIasma Immersion Ion Implantation In plasma immersion ion implantation (PIII) (Chueng, 1991), a wafer holder of 10 inches diameter is immersed in a high-density plasma created by an electron cyclotron resonance (ECR) source. When microsecond pulses of negative bias are applied to the wafer holder, electrons are repelled from the wafer surface, creating a sheath region. Positively charged ions are accelerated across this sheath and implanted into the wafer. The charge per pulse is measured by an integrator attached to a Rogowski loop on the wafer holder. and implant time is chosen to set the implant dose. One major concern with the PI11 doping process is the contamination level involved from the multi-species gaseous plasma, the sputtering of the wafer holder and the chamber wall. Because there is no mass selection or ion focusing in this system, the result is largearea implantation of all the ion species created in the plasma source. Since both the processing chamber and ECR source chamber are fabricated from aluminum parts, detrimental contamination due to PI11 needs to be carefully studied. Fabrication of a sub-100-nm p + junction requires a two-step implant: first, ions from an SiF, plasma are implanted to create a surface layer of amorphous Si (a-Si), and B is then implanted into the a-Si layer using a BF, plasma (Pic0 et al., 1991; Qian et al., 1991). The thin amorphous layer reduces B channeling into the substrate (Wu et al., 1989). Enhanced diffusion of B in the a-Si, as reported by Hong et al. (1991), is also observed. Additionally, the presence of F may further reduce the diffusion of B in a-Si during annealing (Jones and Cheung, 1993). With PIII. the two implantation steps can be performed without breaking

vacuum at extremely low energies (1 -6 kV), and with high ion dose rates. Low-resistivity, ultra-shallow p'/n junctions have been demonstrated using the PI11 technique (Qian et al., 1991; Minondo et al., 1993). Other advantages of PI11 are continuous bias waveform adjustment, high throughput and no destructive field oxide charging during the short implant times required for shallow junctions (En and Cheung, 1993).

9.6 Metallization In order to meet the quality required for high performance ICs, more and more functions are integrated into each device. For system-on-chip or high speed design, multilayer metallization is indispensable. Today, 4 to 6 metal layers are not uncommon for bipolar and CMOS ASICs (application specific integrated circuits). To save space and increase packing density, planarized dielectrics, vertical-walled, filled vias and tight-pitched metal lines are increasingly being used, as shown in Fig. 9-21. There are several critical issues in the development of multilevel metallization technology : -

Refilling via-holes and contact-holes with high aspect ratios. Planarizing structures with both narrow and wide lines/spaces. Developing new conductor materials.

The desirable characteristics required for interconnecting materials are (1) low resistivity, (2) ability to withstand subsequent elevated processing temperatures, (3) chemical compatibility with intermetal dielectrics and their formation methods, (4) chemical compatibility with other metals, ( 5 ) good resistance to electromigration as well as (6) stress migration, In

9.6 Metallization

Figure 9-21. Schematic cross-section of a two-layer multilevel interconnect system.

addition, they must be deposited uniformly on the underlying topography and etched easily by RIE. This chapter will cover several metallization topics: gate electrodes, contacts, and multilevel interconnections. Advanced interconnection concepts and technologies that will be useful for deep submicrometer CMOS circuits will also be discussed. 9.6.1 Gate Electrodes

Gate electrode materials have traditionally been the realm of heavily doped n-type (n+) polysilicon. Typically, the p-channel MOSFET using an n + polysilicon gate will have a threshold that is too negative, and a boron implant is required to increase it. This counterdoping produces a buried channel type device that has poor turnoff or subthreshold characteristics. A larger work function allows the device designer to reduce the boron implant dose, thus improving the subthreshold characteristics. Conversely, the threshold of an n + polysilicon gate NMOS device is too low because a moderately doped p-type silicon surface is depleted by the low work function of the n + polysilicon gate. The acceptor doping concentration must, therefore, be increased to raise the threshold. Other methods to minimize short channel effects include the use of surface chan-

449

nel devices: i.e. n + poly for NMOS and p i poly for PMOS. With proper choices of polysilicon thickness, implant dose and annealing conditions, flat-band voltages corresponding to the degenerately doped polysilicon/SiO, interface can be obtained (Wong et al., 1988). However, even when the proper gate work function is achieved, a slight polysilicon depletion which causes device current degradation could still take place at reverse biases. There is evidence that rapid thermal annealing (RTA) after the polysilicon implant helps reduce the depletion significantly through increased dopant activation. This depletion in polysilicon will become more severe as the gate oxide thickness is downscaled. As the gate oxide thickness is decreased, increased carrier density is required to limit the current loss due to polysilicon depletion effects. Taking into account grain-boundary and interfacial segregation where the dopants are generally considered to be electrically inactive, chemical concentrations of the dopants, as measured by SIMS, should be even higher than the indicated carrier density. A major concern with p + polysilicon is the penetration of boron from the degenerate p + polysilicon through thin gate oxide into the channel region (Sun et al., 1989). Boron penetration introduces VT shift and degrades VT control. The thermal cycle, polysilicon gate thickness, and boron dose should be optimized to meet the requirement of p -poly work function without causing boron penetration. Boron penetration through thin gate oxide is most easily studied by fabricating p+-poly gate MOS capacitors on n-Si substrates and monitoring the C-V shift. Since the diffusivity of boron is also greatly increased in a hydrogen environment, care must be taken to minimize hydrogen or moisture in the annealing ambience after boron is implanted +

450

9 Silicon Device Processing

Table 9-7. Effects of oxidation and passivationireflow on boron penetration after the p+-poly gate is doped to 1 x 10’’ boron cm3 (Sun et ai.. 1989). r,, (nm)

7 7

I I 13 13 13 13 13

Process conditions

dry oxidation (10 nm) wet oxidation (20 nm) LTO cap t N, annealing 30 rnin LTO cap + steam annealing 60 rnin BPSG cap + N annealing 15 rnin BPSG cap + steam annealing 15 rnin LPCVD nitride cap (100 nm) LPCVD nitride cap + 30 rnin N, TEOS cap + N, annealing 60 rnin

into the polysilicon gate. RTA allows the highest temperature for p+-poly processing without boron penetration. Effects of conventional passivation/steam reflow processes on boron penetration in p+-poly-Sigated MOS devices have been extensively studied by Sun. et al. (1989) and are summarized in Table 9-7. It was also reported (Bakeret al.. 1989: Sunget al., 1989; Wong and Lai. 1986) that fluorine (from BF, implant) enhances boron penetration into and through the gate oxides of p-channel MOSFETs using p + polysilicon gates. Inclusion of a phosphorus co-implant or TiSi, salicide was shown to minimize this effect. The boron penetration phenomenon can be modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the Si0,iSi interface. Elemental boron is therefore considered to be superior to BF, as an implant species for surface channel submicrometer PMOS devices. Another disadvantage of polysilicon gates is found in their low conductivity. A good alternative to doped poly-Si is a gate interconnection involving a polycide. The polycide structure uses a silicide shunt on a doped poly-Si pad to reduce the overall sheet resistance to as low as 1 Q/n. This technique combines the advantages of the

Process temperature 800 ‘C

850’C

900°C

OK OK OK AVT=O.l V OK OK AVT=0.2 V

OK AVT=0.3 V OK -

OK OK

AVT=0.2 V

AVT=l V

well characterized SO,-poly-Si interface with the advantages of the silicide, which include low resistivity and thermal and process stability. Various silicides and their material properties are listed in Table 9-8 (Murarka, 1983; Chow et al., 1986; Kato et al., 1986). However, the lateral diffusion of dopants in various silicides is extremely high (Chu et al., 1990), causing gate workfunction shift as well as the formation of a depletion capacitor at the polysilicon/SiO, interface. When polycide interconnections are used to connect p + contacts, considerably high contact resistance is observed

Table 9-8. Silicide resistivity at room temperature.

Material CoSi, HfSi, MoSi, NbSi, Nisi, PdSi, PtSi TaSi, TiSi, WSi, ZrSi,

Co-Sputter (pacm)

Metal-Polysilicon Reaction ($2 cm)

17-20 45-50

100 70 50-60

50-55 35 40-70

50 30-35 28-35 35-45 13-16 35-40

9.6 Metallization

due to boron segregation at the SiO,/WSi, interface and the lateral diffusion of both As and B through WSi, during high temperature treatment, as shown in Fig. 9-22 (Fuji, 1992). To reduce the degradation of dual-polycide-gate n'/p CMOS polycide transistors as well as dual polycide interconnections, the thermal budget should be kept as low as possible. More recently, chemical vapor deposition (CVD) has been used to produce polycide films, particularly WSi, because the films have lower resistivity, less contamination of oxygen, and better step coverage. The first process to be successfully integrated into production was that based on the reduction of tungsten hexafluoride (WF,) by silane (SiH,) (Saraswat et al., 1983; Shioya and Maeda, 1986). However, WSi, films produced by this process contain fluorine in high amounts ( > 10,' atom/cm3), which, upon annealing, diffuses into the underlying gate oxide and leads to performance degradation of metal oxide semiconductor (MOS) devices (Shioya et al., 1987a; Wright and Saraswat, 1988). In addition, the silane-produced films suffer from poor step coverage and adhesion problems, and tend to crack and peel off, especially over extreme topography (Ellwanger et al., 1991). These problems can be avoided by changing the reducing agent to SiH,Cl, (dichlorosilane - DCS). The fabrication of DCS-WSi, films in a batch reactor (Shioya et al., 1987b; Selbrede, 1988; Hara et al., 1990) as well as in a plasma-enhanced single-wafer system (Wu et al., 1988) with loner F content, improved step coverage and adhesion, have recently been published. A specific problem with DCS-WSi, is related to in-depth compositional nonuniformity. DCS-WSi, films, especially those grown on poly-Si, show a reduction in s at the initial stages of the deposition

45 1

Figure9-22. Diffusion path of the dopants in the conventional dual polycide structure.

that is below the optimal regime of 2.2 to 2.6. Values smaller than 2, the stoichiometry of the stable tungsten silicide, have been observed (Hara et al., 1990). This is extremely unfavorable since the formation of a W-rich region at the WSi,/poly-Si interface can cause excessive interdiffusion of Si, localized stress, and adhesion problems following a high-temperature oxidation process. Sheet resistance nonuniformity across the wafer has also been a problem in DCS-WSi, in contrast to silane-based WSi, . Using single wafer reactor, highly uniform in composition (in depth and in lateral position) CVD WSi, films have been deposited on 200 mm Si wafers using SiH,CI,/WF, on SiO, or poly-Si (Telford et al., 1993). Annealing at 900°C in N, of such films deposited on P-doped poly-Si resulted in a uniform reduction of x to a value of 2.1 to 2.2 and resistivity values in the range of 80 to 100 $2 cm. The as-deposited films were predominantly in the hexagonal structure of WSi,, which transformed to the tetragonal structure upon annealing at temperatures above 600 "C. The films had a very good step coverage even at high aspect ratios and did not crack or peel off upon annealing. The films contained relatively little F: z 6 x 10l6 to 2 x io1' atoms/cm3.

452

9 Silicon Device Processing

For future scaled CMOS devices using thinner gate oxides, it is advantageous to work with a gate electrode material with a larger work function to obtain the desired threshold voltage. The larger work functions of Mo (4.7 V). W, or refractory silicides produce low and nearly symmetrical thresholds for p- and n-channel devices on moderately doped substrates (Kim et al.. 1983). In addition. MOSFETs with refractory metal gates require much less channel doping than n i polysilicon gate devices (Takeda et al.. 1985) and reduced subthreshold leakage. However, they are rarely used directly on gate oxides as gate electrode materials due to incompatibilities with the underlying gate oxide. inability to form stable dielectrics. and poor contamination barrier characteristics. 9.6.2 Contacts

After aluminum deposition, most processes need an annealing step at 400 'C anneal. This reduces defects and lowers contact resistance by dissolving any "native" silicon oxides betheen the aluminum and silicon. During this annealing - and other high-temperature processing steps - silicon tends to diffuse into the aluminum forming silicon pits and aluminum spikes. The silicon-into-aluminum diffusion can be suppressed by adding 0.5-2% silicon to a deposition source. When this alloy cools, however, the solubility of silicon in aluminum decreases. i.e.. the aluminum becomes saturated with silicon and any excess silicon precipitates. The precipitated silicon causes an increase in contact resistance. The use a barrier layer between AI and Si can reduce the diffusion of silicon into the aluminum during sintering and. at the same time. act as "etch-stops" to avoid aggressive etching of Si in the contact area due to a misalignment error.

The diffusion barrier can be chemically inert to the materials it separates, or it can be stuffed with small amounts of impurities to inhibit diffusion along fast diffusion paths such as grain boundaries or microcracks that the impurities seal. Diffusion barriers must satisfy a number of criteria. For example, they must be chemically and thermally stable, and they must adhere to both the silicon substrate and the metal film. In addition, they must have minimum intrinsic stress to avoid stress-induced-microcrack failures (Kohlhase et al., 1989). Titanium-tungsten (Ti-W) and titanium nitrides (TIN) are first choices for barrier layers for several reasons. They have very high thermodynamic stabilities and are relatively easy to process. Tungsten is the principal component of Ti-W ; it contains 3 -28 % titanium to improve adhesion, contact resistance, corrosion behavior and ease of etching. Although Ti-W alloys have shown excellent barrier properties, they have very high compressive film stress, resulting in film delamination from the sputtering chamber walls and the subsequent increase in particles. In addition, while TiW can be an excellent etch-stop with chlorine-based dry-etch compositions, it is also very prone to post-etch corrosion and undercut. Titanium nitride (TIN) is an excellent choice because of the following advantages : -

Extremely high thermal stability - TIN resists silicon interdiffusion at temperatures up to 600 "C for 20 h (Wittmer and Melchior, 1982); Low and stable contact resistance when used with a titanium silicide layer - contact resistivity for a Si/TiSi,/TiN/Al scheme remains stable when exposed to 550°C for 20 min (Wittmer, 1985); Low sheet resistance - can be used as a

9. 6 Metallization

local interconnection in CMOS technology (Jeng et al., 1993); Low stress ( zIO9 dyne ern-,) (Kohlhase et al., 1989); Excellent etch-stop capability (Brat et al., 1987).

with furnace annealing or rapid thermal processing. The latter, in particular, forms a TiN/TiSi, structure during a two-step, self-aligned salicide process (Ku et al., 1987). However, there are limits to the quality of the resultant titanium nitride and its thickness. For high aspect ratio contact or via holes ( > 2 : l), film conformality is a critical issue. Collimated sputtering technology has been developed to deposit low resistance Ti and TiN films to improve the contact coverage. A collimator, whose aspect ratio is 1.O, is placed between the sputter target and the wafer so that the wafer can collect the fraction of Ti clusters with normal incidence angle to the surface of the wafer. The problems with collimated sputtering have been shown to consist of no deposition on the side of the contacts, low deposition rate, and particles generation from the collimator. CVD TIN becomes a viable alternative, since these films can be almost 100% conformal. It is also possible to completely fill sub-micrometer contact holes. Traditional CVD TiN processes involve the reaction TiCl, + N, + H, at 1000°C or TiCl,+NH, (6 TiCl,+ 8 NH, --t 6 TIN +24 HCl S N , ) at lower

Several methods have been proposed for TiN deposition, including sputtering, reactive evaporation, thermal nitridation of pure titanium and CVD. Recent results have shown that high quality TiN/TiSi, bilayer can be formed using Ti-rich TIN films deposited from a single TIN,,, alloy target followed by rapid thermal nitridation. Excellent contact resistance and junction thermal stability as well as tight control over the stoichiometry of the sputtered films have been demonstrated, as shown in Fig. 9-23 (Nakamura, 1993). Reactive sputtering of Ti in the presence of N, results in films with low stress and high adhesion (Circelli and Hems, 1988; Stimmell, 1986). The metallization scheme typically included a 10 to 30 nm thick layer of pure titanium, 80 nm and 120 nm thick layers of TiN and 800 nm of aluminum-I YOsilicon. TIN can also be formed by thermal nitridation of titanium in the presence of NH3

4 8 12 16 Breakdown Voltage [ V ]

( M .> l O b A )

453

Breakdown Voltage [ V ]

(M: >IObA)

Figure 9-23. Breakdown voltage distributions of pure Ti and Ti(N0,J samples after (a) 450°C. (b) 525°C annealing.

454

9 Silicon Device Processing

temperatures (Price et al., 1986; Kurtz and Gordon, 1986). Since TiC1, and NH, react at room temperature to form a solid product, it is difficult to mix the gases and introduce them to the reactor without gas phase nucleation. I t has been found (Price et al., 1986: Kurtz and Gordon, 1986) that these two gases neither react in the gas phase nor deposit any TIN film on surfaces in the temperature range of ~ 2 5 0 - 3 5 0 ° C . Based on this fact, both a low-pressure, hot-tube system at 700°C and an atmospheric pressure. cold-wall tube reactor and deposited films at 500-650°C were developed. More recently, a number of studies have demonstrated that the TiCl, + NH, reaction could be carried out in a low-pressure, cold-wall. single-wafer reactor at similar temperatures and high deposition rates (500-1000 k m i n ) (Yokoyama et al,, 1989; Sherman. 1990; Smith, 1989; Buiting et al.. 1991). One group used a reactor with warm (rather than cold) walls ( Z250-350 "C) to prevent deposition on the walls (Smith, 1989). Although resistivity of these films is considerably higher than bulk TIN, it can be kept quite low when depositions are done at higher temperatures. Values from 100 to 300 pR cm are typical, with the lowest values observed at the highest temperatures. Excellent diffusion barrier properties have been demonstrated (Sherman, 1990; Reid et al., 1991; Travid et al., 1990) between silicon and aluminum. Contact resistance of = R cm were obtained for TiN deposited onto titanium silicide (salicide) contacts and p'-Si (Sherman, 1990; Travid et al.. 1990) with excellent leakage current. A number of studies have shown that conformality for TiN can be outstanding, even for sub-micrometer trenches (Yokoyama et al.. 1989; Sherman, 1990; Smith, 1989; Buiting et al., 1991). Rather than using TiC1, as the Ti precursor in

CVD TiN, one could use an organometallic molecule, thereby avoiding chlorine contamination. Two choices are available. One possibility would be the use of tetrakis (dimethylamido) titanium, Ti(N[CH,],), and pyrolize it to yield TIN, since the molecule already contains nitrogen. It has been shown that a more successful approach involves reduction with NH, (Fix et al., 1989). In this case, deposition in an atmospheric-pressure, cold-wall tube reactor at 200-400°C yielded reasonably pure stoichiometric films. Another approach would be to use biscyclopentadienyl titanium, (C,H,),Ti, again with NH, (Yokoyama et al., 1990). Here, reasonably pure films are reported at deposition temperatures of 450 "C in a low-pressure, coldwall reactor. If either film, when deposited at temperatures 400"C, can be shown to have properties similar to the higher temperature films deposited from TiCl,, they will be better choices than aluminum or silicon. Finally, the deposition temperature can be lowered using a glow discharge. Although a number of studies have shown that this is possible for TiCl,+ N, + H, or TiCl, + NH,, they all result in a large amount of chlorine incorporation. One exception has been reported where a TiCl, NH, mixture was excited at 13.45 MHz, and the chlorine content of the film was found to be quite low at 400°C (Hilton et al., 1986). The performance of MOS ICs depends on several parameters, of which the RC time constant is probably the most important. As the size of MOSFET devices decreases, the RC time delay due to the wiring (metal and polysilicon layers) that is used to contact the device gate, source, and drain, does not scale with the shrinking of the physical dimensions of the device. Therefore, for downscaled MOSFETs, the RC speed enhancement can be leveled by

455

9.6 Metallization

the time delay due to the wiring. Selfaligned silicides (SALICIDEs) including PtSi, TiSi,, CoSi,, MoSi,, and WSi,, have been reported to simultaneously form silicide on source/drain and diffused interconnections with the gate. The conventional SALICIDE process flow for n-channel MOSFETs fabrication consists of the following steps. The sidewall oxide spacers are formed after polysilicon gate patterning, lightly-doped source/drain ion implantation, and activation. A thin metal film chosen to form metal silicide is then deposited to cover the entire surface area. Metal silicide is thermally formed at both polysilicon gate regions and source/drain diffusion regions. A selective etching process removes the unreacted metal from the silicon dioxide surfaces but does not attack the metal silicide. A layer of doped glass (BPSG or PSG) is then deposited, followed by flow, contact window opening, reflow, and A1 metallization. For noble and near noble metal silicides, the metal is the dominant moving species during the reaction. This reduces the probability of bridging between gate and source/drain because of less lateral silicide formation. One major disadvantage of no-

ble and near noble metal silicides is the high temperature limitation. This temperature limitation can be relaxed by the use of refractory metal silicides, due to their high temperature stability. The use of TiSi, and CoSi, in SALICIDE technology has received considerably more attention than other metal silicides because of low resistivity, good adhesion, and high temperature stability. A comparison between CoSi, and TiSi, is shown in Table 9-9. Using the conventional TiSi, SALICIDE process for CMOS applications causes several problems, including the formation of native oxide at the metal/Si interface which slows down the reaction and results in a rough silicide surface, critical ambient control, lateral silicide growth, different amounts of Si consumption in p-channel and n-channel devices, and non-ohmic contacts due to significant dopant redistribution during silicide formation. The native oxides at the TijSi interface cause the reaction to proceed in a non-uniform fashion, resulting in a rough silicide surface. In addition, a high concentration of As at the Ti/% interface retards titanium silicide formation. Therefore, the growth rates of titanium silicides formed on n + (As doped)

Table 9-9. Comparison of the properties of CoSi, and TiSi,. Properties Resistivity (pR/cm) Metal-dopant compound formation Thermal stability on single crystal Si Thermal stability on polysilicon (undoped) Mechanical stress (dyneicm') Reaction temperature with SiO, ("C) Dominant diffusion species during silicide formation Sheet resistance control Resistivity to dry/wet etching Native oxide consumption Thermal stability in the Al/silicide/Si system Lattice match with Si

CoSi,

TiSi,

10-15 no good poor (8-10) x lo9 > 1000 "C

13-16 Yes good poor (2-2.25) x 10" 700 "C Si poor poor good poor poor

co good good poor poor good

456

9 Silicon Device Processing

and p + (B doped) regions are different, resulting in different amounts of silicon consumption in the diffusion regions of pand n-channel MOS devices. Furthermore, significant amounts of dopant redistribution in source and drain areas occurred during SALICIDE formation, which makes the ohmic contact resistance very difficult. The above mentioned problem is avoided in the source-drain extension structure (Taur et al., 1993). in which shallow p + (or n - ) source-drain extensions are used in conjunction with deeper p + (or n + ) source drain regions implanted after thick oxide spacer formation. as shown in Fig. 9-24. The shallow extension depth is decoupled from the deep junctions required for the SALICIDE process. A 600 8, deep p + source-drain extension has been fabricated by Sb pre-amorphization and low energy BF, implantation (Taur et al.. 1993). Another approach is to use selective silicon deposition to form raised sourcedrain structures (Mazure et al., 1992; Kotaki et al.. 1993). Issues with SEG elevated S:D structures and technologies are: capacitance increase, effects of faceting.

9.6.3 Interconnections The reduction in interconnection feature sizes has lead to reliability degradations

caused by electromigration and stress-induced migration. The increase in wiring resistance as a result of the increase in chip size has been solved by increasing the number of interconnection levels. To meet this requirement, the thicknesses of both conductors and inter-layer dielectrics have been kept constant to reduce parasitic resistances and capacitances, making contact- and via-hole aspect ratios greater than one. Therefore, new contact- and viahole filling technologies as well as highly reliable multilevel interconnection conductor systems will be required. An example of interconnection materials and technologies for 256 M D R A M is shown in Table 9-10 (Kikkawa, 1992). As traditional interconnection materials AI as well as various alloys of A1 have been used. Aluminum has a number of ideal properties: (1) low resistivity (eBulk = = 2 . 8 pi2 cm); (2) excellent adhesion to S O , : and (3) excellent wire bonding properties. However, because of its very low melting point (660 "C), electromigration occurs at relatively low temperatures and low current densities. Electromigration of A1 atoms takes place at the grain boundaries within the metallization line. The electron stream creates a flow of these atoms because they are less tightly bound than those within grains where the atoms are bound in lattice positions. Because the atom flow

n-WELL p - T Y P E SUBSTRATE

Figure 9-24. Schematic cross-section of 0 1 prn CMOS devices with source drain extension structure for sil!c ided J anctions

457

9.6 Metallization

Table 9-10. Interconnection materials and technologies for 256M DRAM (Kikkawa, 1992). Interconnection Word line Bit line Bit contact Capacitor contact Peripheral contact

Material

Process

Design rule

Aspect ratio

WSi,,poly-Si WSi, N * poly-Si N + poly-Si W/TiN/Ti

sputtering/LP-CVD sputtering doped LP-CVD doped LP-CVD blanket W-CVD collimated sputtering reflow sputtering (L. T.) collimated sputtering reflow sputtering (H. T.) collimated sputtering sputtering

0.25 0.25 0.25 0.25 0.3

1-1.4 0.5-1.0 2-4 3-6 3-4

0.3

3-4

0.3 0.25

3-4 1-2

0.25 0.6

1-2 1-1.5

0.6

1-1.5

AI-Ge/TiN/Ti

Metal line

Via-hole

Al-Si-Cu/ TiN/Ti TiN/Al-Si-Cu/ TiN/Al-Si-Cu/TiN cu W/TiN/Ti Al-Ge/TiN/Ti

sputtering blanket W-CVD reactive sputtering reflow sputtering (L. T.) reactive sputtering

occurs along the grain boundary in the direction of electron flow, a grain boundary that extends completely across the metallization pattern (“bamboo” structure) should have greater electromigration resistance. However, this type of structure is not manufacturable. The practical method of reducing grain electromigration is to introduce impurities, such as Si and Cu, that passivate the grain boundaries. The additions of high percentages of Cu make alloys difficult to etch and prone to corrosion problems; therefore, large numbers of circuits are still being made with A1 (1 ‘Yo Si) or A1 (1 YOSi) with a small percentage of Cu ( <0.5 %). The addition of Si causes Si “nodule” formation due to Si precipitation within the line that can occur during cooling or during the operation of the device (Shen et al., 1985). As the nodule grows in size, the current density in the A1 around the nodule increases and the line can eventually crack because of the stress around the growing nodule. Nodule growth can also cause interlevel metal

shorts or time-dependent breakdowns. Another traditional problem with A1 metallization has been hillock formation. Hillocks are formed by solid-state diffusion of A1 to relieve the film stress during thermal cycling at temperatures below those where plastic flow can occur. Hillocks are also formed by electromigration. Ti (0.2-3 wt.%) has been substituted for Cu to add to an A1 (1% Si) alloy to reduce electromigration. These additions of Ti increase the resistivity. Thin multilayers of Ti and A1 (1 YOSi) have been proposed and demonstrated with a 10 to 100 times improvement in the mean time to failure compared to A1 (1 YOSi) films (Shen et a1.,1985; Jones et al., 1985; Gardner et al., 1985). It must be noted that it is especially important to create a good barrier between the contact to silicon if an Al-Si-Ti metallization is used because the solubility of Si in the A1,Ti intermetallic compound can be as high as 15% (Shen et al., 1985). A new interconnection structure using TiN/A1-1 %Si-0.5 %Cu/TiN/Al-

458

9 Silicon Device Processing

1 %Si-O.5 %Cu)TiN/Ti layered films has been developed for both electro- and stress-migration-resistant interconnections (Kikkawa et al.. 1991). The multilayer interconnection shows larger Vickers hardness value, less tensile stress relaxation and longer electromigration lifetime in comparison with Al-Si-Cu single layer. These improvements are due to the rigid intermetallic compounds, Ti,Al, at the interface between TIN and Al-Si-Cu (Kikkawa et al., 1991). Contact holes with minimum geometries in the order of 0.25 pm and aspect ratio greater than one must be plugged with an interconnection material having good coverage, low resistivity, stability during thermal processing, and compatibility with existing processes. Aluminum alloy reflow sputtering is a promising low-cost technology for contact-hole filling. Aluminumgermanium (AI-Ge) alloy (Kikuta et al., 1991) can flow and fill in quarter-micrometer contact holes at 300°C due to its lower eutectic temperature (424 'C) than other Al-alloys. A highly reliable sub-half-micrometer via and interconnection technology using high temperature sputter filling of Al-Si-Cu alloys has been developed by Nishimura et al. (1992). A thin Ti underlayer was employed to prevent Si from precipitating. The substrate temperature during the sputtering for a filled via was 500'C. Complete filling of a 0.15 pm diameter via with aspect ratio of 4.5 has been realized with four orders of magnitude improvement in electromigration resistance compared with conventional via formation sputtering. Silver is a potential candidate for ULSI interconnection because of its lowest resistivity compared with other interconnect materials. However, silver has numerous processing difficulties, which limited its wide use in the past (Table 9-1 1). The ma-

Table 9-11. Properties of AI, Cu, Ag and Au. AI Resistibit) (pi2 cm) 2.8 Melting point ( T ) 660 EM endurance 1 (normalized to AI) Heat of formation -400 of oxide (kcal mol) Diffusion into S O , no Agglomeration no RIE easy

1.7 1083 20

1.6

2.2

961 10

1063 20

-40

-7.3

-0.8

yes small difficult

yes no severe no diffi- difficult cult

jor problems are the lack of reliable dry etching and the requirement of high temperature annealing needed to obtain low resistivity. A novel planarized silver interconnect technology with TiO, passivation has been developed by Ushiku et al. (1993). The process sequence is shown in Fig. 9-25. The first annealing at 400°C results in Ag planarization due to significant surface diffusion of Ag. After etching back or CMP process, the sample is then annealed at 600 "C. During annealing, Ti diffuses upwards through the Ag films to the surface and forms a TiO, layer. The TiO, layer protects the agglomeration in Ag films during annealing. Recently, a novel contact filling technique has been developed based on polysilicon plug and Ni silicidation with a TIN barrier layer (Iijima et al., 1992). The process details are shown in Fig. 9-26. This

Figure 9-25. Process sequence of Ag interconnection technique: (a) Ag deposition; (b) annealing at 400°C; (c) etch-back or polishing; and (d) annealing at 600'C.

9.6 Metallization

Poly-Si Plug Poly-Si

TiNlTi a) Ni Sputtering Si-Substrate Ni ",Si

b) Ni silicidation

Silicidation stop

c) Selective metal etch Si-Substrate

Figure 9-26. Schematic process sequence of the Ni,Si contact plug technology: (a) Ni sputtering; (b) Ni silicidation; and (c) selective metal etching.

process is self-aligned, selective, and is capable of filling both shallow and deep contacts simultaneously with the help of a TIN silicidation stop layer. During Ni silicidation, Ni diffuses into polysilicon plug, resulting in a flat plug surface. Excellent junction leakage and transistor characteristics have been obtained with these selective Ni,Si contact plug techniques. In order to achieve lower contact resistances in high aspect ratio contact-holes, metal plugging is necessary. CVD of metals, particularly selective deposition of interconnections, represents a fundamentally different capability for integrated circuit manufacture than has been available in the past. With its advent vertical wiring capabilities arise that will enhance the pace at which industry can implement multilevel metallization for three or more levels of interconnections. Especially in the deep submicrometer range, CVD metallization will reduce processing problems by provid-

459

ing an effective technique to achieve planarized wiring and by increasing reliability. For the past few years, A1 CVD has been investigated for its capability of achieving conformal step coverage (It0 et al., 1982b; Cooke et al., 1982; Lvey et al., 1984), selective growth onto the Si surface (Amazawa and Arita, 1991 a ; Amazawa et al., 1988; Sasaoka et al., 1989; Masu et al., 1990; Shinzawa et al., 1989) and single crystal growth on Si wafer (Kobayashi et al., 1988). To provide full control over selective and nonselective deposition of high quality Al, Tsubouchi et al. (1992), have developed a plasma excitation technique for A1 CVD deposition. Dimethylaluminum hydride [DMAH; (CH,),AlH] was chosen as the precursor due to its high vapor pressure ( z 2 Torr at 20 "C, ten times higher than that of triisobutyl aluminum). A1 is produced from DMAH and H, via the following reaction : (11

CH3 \ A I - H + i H,

A1 1 + 2CH4 1

CH,' Using this process, single crystal (100) and (111) AI are selectively deposited on (111) Si and (100) Si, respectively with resistivity close to the bulk resistivity. The selective growth mechanism is explained sequentially as follows: (1) the Si surface is hydrogen (H) terminated after cleaning by dilute HF, followed by a pure water rinse; (2) the terminated H atom (the terminator) reacts selectively with the CH, radical (the selective reacting radical) of adsorbed DMAH; and (3) after A1 deposition, the H atom of the DMAH molecule remains on the deposited surface as the new terminator. In the case of the nonselective deposition, the plasma supplies both electrons and H atoms to the SiO, surface. As a result, the reaction of C H , + H + CH,

460

9 Silicon Device Processing

occurs on the SiO, surface, producing a thin Al layer on SiO,. A 0.25 pm via plug process based on selective CVD aluminum for multilevel interconnect has been developed by Amazawa and Arita (1991 b) using triisobutyl aluminum (TIBA), as shown in Fig. 9-27. Surface native oxides on AI, Ti. or W have prevented A1 growth. In situ R F cleaning was used in this study to remove native oxides prior to A1 deposition. In order to avoid AI nucleation on dielectrics treated by R F etching, amorphous Si was deposited on dielectrics. 0.25 pm via holes with very low contact resistivity and excellent electromigration reliability have been demonstrated. In recent years CVD tungsten has received the most attention among CVD metals and is likely to replace aluminum alloys in the lower metallization levels because of better deposition uniformity than aluminum and excellent electromigration resistance. The higher resistivity of W relative to A1 can be tolerated because line lengths in the lower levels are relatively short. Tungsten originally attracted attention because of its potential for selective

deposition. Tungsten deposition only occurs in the oxide or nitride windows that have been opened to the surface of the Si and not on the oxide and nitride surfaces. In applications such as via filling, barrier metal, and source/drain/gate shunts, selective deposition is attractive since it would allow the elimination of mask and etch steps, thereby reducing the complexity of the production process. Moreover, because deposition occurs only at the base of the feature, void-free feature filling is automatic and step coverage is not an issue. However, tungsten has poor adhesion to the underlying silicon (in the case of vias). The adhesion can be improved by performing a precleaning step to remove any residue or native oxide that may be present. followed by the deposition of an adhesion layer such as TiN. A novel doubleself-aligned TiSi,/TiN contact with selective CVD tungsten plug for submicrometer device and interconnection applications has been developed by Wang et al. (1991). As shown in Fig. 9-28, the reactively sputtered TIN layer on dielectric-1 layer provides a stable surface which prevents any tungsten nucleation during selective CVD

Figure 9-27. Selective CVD aluminum via plug process.

9.6 Metallization

46 1

After Low temperature anneal, selective wet etch, and N implantation TiSi, A

FOX

After dielectric 1 (Dl) deposition, TIN deposition, and contact patterning Ti

After: Plasma CHF3- 0 contact dry etch stop on TiSi 9OO'C NH 3 rapid thermal aneal to densify D1, and convert TiSix to T i W i S i ,- bilayer -

N-Well After s

Figure 9-28. Schematic process flow of SCVDW (selective CVD tungsten) plug process

tungsten process. However, tungsten will nucleate on the TiN/TiSi, layer formed by RTA of TiSi, in presence of NH, . The selective nature of the tungsten deposition is initiated by the highly exothermic, rapid reaction of WF, with silicon to produce solid tungsten and gaseous silicon fluorides (2 WF, 3 Si -, 2 W 3 SiF,). Since the reaction involves Si consumption, the deposition is selective. The reaction is characterized by a fast growth rate, but the W thickness is self-limiting. After a thin layer of W is deposited, a barrier is created. This barrier prevents the WF, molecule from diffusing through the W film and reacting with the Si surface, or the Si is prevented from reaching the surface and reacting with WF,. The final W film thickness is dependent on substrate, deposition temperature, WF, partial pressure and

total pressure. Thicker W films can be deposited by adding a reducing agent such as H, to the reactor. Hydrogen dissociatively adsorbs on the growing tungsten film and reduces co-adsorbed WF, producing W and volatile H F (WF6+3 H, + W s 6 HF). Hydrogen does not readily adsorb dissociatively on silicon dioxide or nitride. It is this difference in adsorption behavior which, at least in principle should allow deposition to continue in a selective manner. Silicon reduction reaction which initiates selective deposition removes Si from under the edge of the oxide at the base of the contact hole and deposits W under the oxide. The haloing effect (encroachment of W at the Si/SiO, interface) as well as the wormholes (tunnel formation in the Si) (Broadbent and Stacy, 1985) can be mini-

462

9 Silicon Device Processing

mized by adding silane in the gas phase to reduce Si consumption at the WiSi interface (3 SiH, + WF, + 2W + 3 SiF, + 6 H,). Silane reduction provided faster deposition rates, a lower deposition temperature and was a much cleaner process. However, the resulting W films contain Si and have larger resistivities than films deposited by hydrogen reduction (Kusumoto et al., 1988; Yu et al.. 1989). Because of these interfacial problems, barrier layers such as TiN have been deposited between Si and W. Conformal composite layer metallization. such as tungsten selectively deposited onto patterned aluminum interconnection, has been demonstrated (Hey et al., 1986). Open circuit failures have been reduced dramatically because of improved step coverage and greater electromigration resistance from the uniform tungsten cladding layer that can be made to encapsulate the aluminum lines. Selectivity loss is the most serious concern with selective tungsten deposition. The selectivity loss on patterned silicon wafers has been related to the reaction intermediates or by-products such as silicon subfluorides and silicon oxyfluorides formed by etching of SiO, by WF, or H F ablation of SiO, (Foster et al., 1988; Hirase et al., 1988; Kwakman et al., 1988). Experimental results suggested that volatile tungsten subfluorides produced on tungsten surfaces adsorb on surrounding Si02, producing tungsten nuclei (Creighton, 1987). Process parameters which influence selectivity loss include the partial pressures of WF, and H,, total pressure, deposition temperature and time. and reactor configuration. In addition, dielectric surface properties also affect selectivity loss. For example, sputter-deposited SiO, exhibits a greater tendency towards selectivity loss than thermally grown SiO, (Sumiya et al., 1987). Because of these difficulties in selec-

tive tungsten CVD, blanket deposition with etch-back has been adopted in multilevel metallization schemes to achieve via fills. Copper is a potential candidate for interconnection because of its high conductivity and high reliability. Theoretically, copper exhibits significant advantages over aluminum as a high density interconnection material. The electrical resistivity of copper is 30-50% lower than that of aluminum alloys. Also, the electromigration performance of copper interconnections is expected to be more than two orders of magnitude better than for systems based on aluminum alloy due to copper's considerably higher melting temperature. Thus, copper interconnections deposited with the same design rules as AI alloys could increase the operating frequency of devices as well as allow higher current densities. Despite these advantages, however, there are several concerns with copper interconnection technology: (1) the lack of a suitable Cu dry-etch process; (2) copper is incompatible with silicon and acts as a "poison" to the active device area by forming deep acceptor level traps in the forbidden gap, reducing the minority carrier lifetime; (3) the lower heat of formation of copper oxide compared to Si/SiO, results in low thermal stability during annealing, planarization and etch-back processes; and (4) the high diffusion coefficient of copper in silicon dioxide. The fast diffusion of Cu through oxide and then into the Si substrate can be prevented by completely encapsulating Cu, as shown in Fig. 9-29 (Cho et al.. 1991). Figure 9-29A involves the use of selective tungsten for encapsulation. Figure 9-29 B starts with the deposition of a seed layer (TiW) for tungsten into LTO trenches. The diffusion of Cu into the sides of trenches is protected by the use of nitride spacers.

9.6 Metallization

463

Figure 9-29. Process sequence for (A) non-planar and (B) planar Cu interconnection with W cladding.

Selective CVD for metal surfaces has been the subject of a number of contradictory reports in recent literature, most probably because of the differences in surface pre-treatments, reactor systems and deposition conditions used by various groups (Jain et al., 1992a; Reynold et al., 1991;Norman et al., 1991 ; Baum and Larson, 1992). A number of groups have proposed that the interaction of organometallic precursors with the SiOa surface is a crucial aspect of the selective deposition of metals such as W and Cu in the presence of SiO, (Cheek et al., 1992; Creighton, 1991). The surface of SiO, consists partially of hydroxyl groups (Si-OH) and oxo-groups (Si-0-Si) which are most likely to be the active sites available for absorption of the precursor molecule. Differences in selectivity have been attributed to the differences in the interaction of (hfac)CuL molecules with the hydroxyl groups in a series of model experiments on SiO, (Cab-0-Sil) surfaces (Hardcastle et al., 1991). Chemi-

cally passivating or removing the surface hydroxyl groups resulted in modified selectivity (Jain et al., 1992b; Dubois and Zegarski, 1992). Copper CVD following the intentional modification of the SiO, surface hydroxyl groups on the silica surface using functionalized silanes with a variety of copper(1) precursors resulted in controlled selective deposition of copper on SiO, versus other metal surfaces.

9.6.4 Planarization for Multilevel Interconnections The trend toward modular VLSI design with computer aided routing of interconnections is pushing the technology toward multilevel metallization structures. Besides easing the routing problem, thus enhancing circuit performance, this results in smaller chip size connected with cost reduction because of the larger number of chips per wafer. Unfortunately, the topography created by the first-level metallization of-

464

9 Silicon Device Processing

ten makes continuous metal lines difficult in upper metal levels. seriously affecting die yield. To compensate for this topography, various planarizing and smoothening processes have been developed. In order to planarize the deposited dielectric layer over severe topography, the deposited dielectric layer must be thicker than the required final film thickness since a significant portion will be removed by the planarizing process. Furthermore, the thick deposited dielectric layer must be free from defects. The key film characteristics desirable for interlevel dielectrics are : -

Good step coverage on metal and dielectrics: Good gap filling for planarization; Low as-deposited stress and small hysteresis on heat treatment; No stress-voiding in metal lines either on heat treatment or long term storage; High dielectric breakdown strength; Stability with respect to ion migration; Low density of defects/particles.

A common problem is the formation of voids or key holes in gaps with high aspect ratio. The CVD technology used to deposit a gap filling dielectric layer was originally based on the oxidation of silane. Silane oxide, however, does not give a very uniform coating over topography with aspect ratios of 0.5 or larger. The use of the CVD TEOS, oxygen process greatly improves the conformality of the deposited oxide. As a result, TEOS oxide has become the most popular film type for interlayer insulation in sub-pm devices. Reflow oxide films under A1 metallization are generally made with TEOS oxide films using normal pressure CVD. One technology attracting attention is the combination of TEOS and 0, normal pressure CVD. The step coverage is improved from TEOS+O, and voids in concave sections are eliminated.

The dielectric films deposited by thermal TEOSiozone process tend to be rather porous and may absorb a significant amount of moisture (Nguyen et al., 1990). Therefore, it is common to use it in the dep/etch process so that the bulk thermal TEOS/ ozone film is etched away leaving only this film in the gap filling area (Pennington et al., 1989). The step coverage capability and the dielectric quality of the TEOS/ozone films can be improved by increasing the deposition pressure. The deposited TEOS/ozone films at atmospheric pressure (APCVD) or sub-atmospheric pressure (SACVD) using high ozone concentration tend to be thicker at the inside corners of a gap, thus giving a rounded or “reflowed” profile over a step (Nishimoto et al., 1989; Fujino et al., 1991; Kotani et al., 1989; Lee et al., 1990). This is opposite to the cusp formation over a step in standard CVD dielectric films. Furthermore, these AP-TEOS/ozone or SA-TEOS/ozone films tend to be denser and absorb less moisture than TEOS/ ozone films deposited at low pressure (Kotani et al., 1989; Lee et al., 1990). However. AP-TEOS/ozone film deposited with high ozone/TEOS ratio tend to be surface sensitive and pattern density sensitive. This would make the step coverage vary with different surfaces and pattern densities. Adding Ge to AP-TEOS/ozone films can significantly alter the mechanical properties of the film, dramatically reducing the reflow temperature and improving film stability (Baret et al., 1991). The capability of the AP-CVD TEOS/ozone deposition process to fill submicrometer high aspect ratio gaps or re-entrant profiles could provide significant simplifications to the planarization processes for future ULSI structures. The resist spin-on and etch-back procedures were developed to provide the low

9.6 Metallization

temperature planarization process (Adams and Capio, 1981). This process is based on the planarization capability of a photoresist which is coated in liquid form over the topography surface in question by spinning the wafer at high speed. This technique starts with the deposition of a 1-1.5 pm thick layer of CVD silicon dioxide. The exact thickness is determined by such parameters as polysilicon thickness, first metal layer thickness, and geometry pitch. After oxide deposition, the photoresist is spun onto the wafers and baked above the glass transition temperature to flow the resist and create a planar surface. Next, the nearly planar surface of the photoresist is transferred to the underlying dielectric film by using a dry-etching process that etches the photoresist and the dielectric layer at nearly equal rates (1 : 1 selectivity). The etching process is continued until all the photoresist is removed so that the smooth photoresist surface contour is transferred into the dielectric film. Finally, a second deposition of silicon dioxide brings the interlayer metal dielectric to the desired thickness for the second level of metallization. This process has been widely used to planarize dielectric layers over A1 metallization. However, the degree of planarization depends not only on the resist coating thickness, but also on underlying geometries. Good planarity is obtained only for small closely spaced patterns. The planarity degrades rapidly when the pattern width or gap width exceeds several micrometers. Although this problem can be reduced by using an additional photolithography step (Sheldon et al., 1988), it in- creases the process complexity. The surface planarity of the spin-on layer can be greatly improved if thermally flowing polymer is used for the spin-on layer. Sufficient planarization can be achieved over geometries as large as several hundred micrometers (Ting et al., 1989).

465

While a very planar surface can be obtained by the photoresist etch-back technique, the planar surface results in oxides of varying thicknesses in areas where vias are to be cut to the first metal layer over diffusion areas, field areas, or polysilicon. Oxide thicknesses can vary by nearly 100 YOfrom area to area. For example, oxide thickness of nearly 1.8 pm can exist in areas where vias are over diffusions and are as thin as 0.9 pm of oxide over polysilicon. If a via fill or tungsten plug process is not available, a tapered via etching process produced by photoresist erosion etching is necessary to ensure adequate metal step coverage into the via. Tapering the developed vial profile in the thick resist layer has required post-exposure baking or carefully controlled post-develop baking of the thick resist. These processes are very temperature sensitive and often result in incomplete developing of the polysilicon vias. In addition, since the photoresist is lost during the via etch, it should be at least as thick as the thickest oxide. The via etching time must be long enough to etch the thickest oxides - those over diffusion areas. Consequently, the thinner oxides over polysilicon get nearly 100 % over etching. This results in vias that are oversized with no taper. The resist spin-on etch-back process can be simplified if the spin-on material can be used either as a stand-alone dielectric layer or in conjunction with CVD dielectric films. Spin-on glass (SOG) films have received much attention for this application. There are many different types of SOG materials such as silicates, doped silicates and a variety of polysiloxanes. They can be coated from liquid to give a spin-on film with good surface planarity. SOG films can be cured at relatively low temperature to give a silicon dioxide-like film. However, the film properties depend on the

466

9 Silicon Device Processing

starting material and the curing conditions as well as subsequent processing conditions (Pai et al., 1987). In general, the density of SOG layer is lower than the thermal oxide and it cracks easily for thick layers. Therefore, it is usually used in conjunction with other CVD dielectric layers to form a CVD-SOG-CVD sandwich structure (Nguyen et al., 1990). A partial etch-back process is generally used to remove SOG from the via opening areas to avoid excessive moisture absorption in the SOG films. The silicate SOG film cured at low temperature is rather porous and can absorb a large amount of moisture. The porosity of the film can be reduced if the SOG is densified at high temperatures (Le., 90OZC),which is not acceptable for aluminum. Another way to reduce the porosity is by using siloxane materials, which have organic groups such as methyl or phenyl groups at the end of silicon-oxygen chain to relieve film stress and to reduce moisture absorption. With proper material choice, the moisture absorption of a siloxane film can be reduced to a negligible amount. In general, the wafers are soft baked after coating at 150-35O’C to remove the solvent base. Then they are cured at 425 “C for 60 min. The resulting film is nearly 100% silicon dioxide with some organic substituents. This smoothing process fills in any voids created by the initial oxide deposition process. After curing, the process continues with a “blanket” etch-back. Then, the resulting substrate is capped with additional CVD oxide forming a CVD-SOG-CVD sandwich structure. Thick single coatings of SOG tent to crack. Topographies on the wafer can produce SOG as thin as a few hundred angstroms over high spots to as thick as 8000 A between minimum spaced line pairs. To minimize the chance of cracking, the SOG is

spun on in two applications with soft baking after each coating application. The final cure plays an important role for the quality of the finished film. SOG cracks from thermal shock. If SOG remains in areas where vias are to be cut, out-gassing of retained or absorbed water can cause an “exploding” or “poisoning” of vias (Ting et al., 1987). This results in high contact resistance or open circuits. To prevent this, SOG should be etched back so there is none where vias were to be cut, leaving only fillets sandwiched between CVD oxide structures. The integrity of organic substituents containing siloxane films is destroyed by oxygen plasma, such as those commonly used for organic resist stripping. The siloxane film with organic groups partially removed by oxygen plasma is very porous, and it cracks easily and absorbs a large amount of water. Therefore, the oxygen plasma steps must be eliminated if the siloxane film is to remain on the wafer surface such as that used in the non-etch-back SOG planarization process. Otherwise, the siloxane film must be protected from the oxygen plasma by using a dense capping layer over the SOG film. A physical etching process has an incident-angle-dependent etching rate. It generally has a lower etching rate for flat surfaces than sloped surfaces. Therefore, physical etching processes can be used to remove sharp corners to give a smoother surface. Using repeated etching and deposition cycles, a planarized surface can be obtained over small dimensions. To reduce wafer handling for repeated dep/etch cycles. several equipment manufacturers have developed automated systems that combine etching and CVD deposition processes in a single system. By using different combinations of deposition and etching cycles one can obtain various degrees of

9.6 Metallization

planarization in the final dielectric layer surface. The well-known AMP-500 system uses plasma TEOS for the main dielectric layer. However, plasma TEOS does not have sufficient step coverage for tight geometries. Therefore, it is used in conjunction with thermal TEOS/O, to provide the needed step coverage. Unfortunately, thermal TEOS/O, has rather poor dielectric properties (Le., a high water content as mentioned previously) so an etchback process is used to remove most of the film leaving only pockets of thermal TEOS/O, in the gaps to provide a planarized surface. Both SOG and resist etch-back planarize over a distance in the tens-of-micrometer range. For deep sub-half-micrometer devices, etch-back and SOG techniques are not sufficient for wafer planarization or topography smoothing. Chemical-mechanical polishing (CMP), which involves the use of mechanical padpolishing systems with fumed-silica as the slurry, offers one major advantage: global wafer planarity, as shown in Fig. 9-30. Planarity across the wafer is required for the following reasons: -

Global planarity can compensate for shallow depth of focus (DOF) ( < 0.5 pm) with high numerical aperture lenses (i-line, 365 nm). This is essential for fine line lithography over a large stepper field size. With photoresist thickness variation over topography, CD control is very diffucult. Global planarity also improves metal step coverage and its associated reliability. Since metal is situated where the device topography is most severe, perfectly flat metals will improve device yield and reliability. Global planarity exerts an additive topography effect on the final metal layers.

467

Non-planarization

Smoothing

n n

Local planarization

n n

Global planariration

Figure 9-30. Planarization capability.

Mechanistically, the removal rate, drldt, of a glass surface during polishing follows the Preston equation (Preston, 1927) dr/dt = K p (dsldt)

(9-1)

where p is the applied pressure, and ds/dt is the relative velocity between the glass surface and the pad. K , the proportionality constant, is termed the Preston coefficient. The units of K , area/force, relate it to the mechanical properties of the glass. At the fine polishing situations that are normally encountered in planarization, the Preston coefficient is related to the Young’s modulus and the hardness of the glass. It is only a weak function of the applied pressure and the relative velocity. During a brittle grinding situation, macroscopic chunks of material are removed from the glass surface, whereas polishing is characterized by near surface interactions and removal of molecular clusters of material. The key tooling elements of a CMP equipment are shown schematically in Fig. 9-31 (Thomas et al., 1991). Wafers are held by rotating wafer chucks or heads. The wafer surface is exposed to the opposing surface of a polishing pad which is also rotating. A controlled amount of pressure is applied during this process. A slurry fed

468

9 Silicon Device Processing

--Gxz? Figure 9-31. Ke) tooling elements of CMP equipment

at a controlled rate wets the polishing pad and the wafer surface. The process of polishing is thought to occur according to the following sequence : (a) Formation of hydrogen bonding between the solvated oxide surface and the solvent in the slurry. The solvated oxide surface pertains to both the surface of the wafer and the surface of the slurry particles. (b) Formation of hydrogen bonding between the solvated surfaces on the wafer and on the slurry particles. (c) Formation of molecular bonding between the surfaces. (d) Removal of the bonded wafer surface as the slurry particle moves away. Polishing occurs when the depolymerization reaction proceeds faster than the polymerization reaction. The cleavage of the Si-0-Si below the wafer oxide surface is controlled by the diffusion of water through the oxide. The role of the slurry particle is to impart a chemical “tooth” to the polishing process. The strength of the bond between the slurry particle surface and the wafer surface determines the effective kinetic coefficient of friction between the two surfaces during polishing. Thus the chemical nature of the oxide dispersed in

the slurry is crucial to the final oxide removal rate. Cerium oxide shows in the highest removal rate, followed by Zr and Ti oxides. However, for the planarization process, the choice of the slurry components must be made not only based on the removal rate, but also on the planarity obtained, and the ability to distribute the particles effectively in a stable colloidal distribution. To achieve planarity with the polishing process is relatively simple. However, obtaining simultaneously stable, high removal rates and uniformity across the wafer is more challenging. The removal rate falls off with the age of the pad, causing process control problems. This dropoff with pad life is due to plastic deformation of the pad surface and the resultant glazing. Pad glazing appears to result in two phenomena: (1) the net area of contact between the pad and the wafer increases and hence the effective polishing pressure drops, and ( 2 ) the channels available for slurry transport to the interior of the wafer are blocked. It is hypothesized that the latter has the stronger effect. It has also been observed that an isolated small elevated feature on an otherwise flat topography polishes must faster than a dense array of elevated features. Large high areas polish the slowest. Hence differing densities of features within a die can result in degraded planarity due to different removal rates (Daubenspeck et al., 1991). Such a pattern sensitivity in polishing degrades within-die uniformity and if uncontrolled, might expose underlying layers in one portion of the wafer while leaving large under-polished regions in other parts. CMP can also be applied to form the aluminum contact and wiring plugs with different polishing liquids (Hayashi et al., 1992; Kikuta, 1993). Multilevel pla-

9.7 Cluster Tool Technology

narized-trench-aluminum interconnection using aluminum reflow sputtering and CMP has been demonstrated. Laser planarization is a viable technique for the fabrication of VLSI and ULSI interconnection layers (Magee et al., 1988; Wang and Ong, 1990). As shown in Fig. 9-32, via hole filling with a thin film of Au, Al, or Cu can be effectively planarized by briefly melting it with a pulsed XeCl (308 nm) excimer laser in a process vacuum chamber with substrate heating. Planarization is rapid because of the high surface tension and low viscosity of clean liquid metals. Micrometer and submicrometer diameter contacts and vias have been filled with A1 under proper conditions (Magee et al., 1988; Wang and Ong, 1990; Liu et al., 1989; Pramanik and Chen, 1989). Due to the high thermal diffusivity of A1 (1 cm2/s), the time required for heat transfer through a 1 pm thick film is only about 10 ns. A pulse tens of nanoseconds long is sufficient to melt the metal overlayer while minimizing metallurgical and thermal reactions between the film and its underlying barrier or dielectric layer. Dielectric films such as S O , with thermal diffusivities one hundredth that of

Metal Cap Formation

lPlug

Formation

molten A1 prevent heat transfer to the underlying substrate. The high surface tension, low viscosity, and excellent thermal diffusivity of A1 combined with the good thermal barrier of SiO, make it practical to planarize an A1 interconnection film without damaging underlying devices. The composite film stress changes from slightly compressive to slightly tensile after laser processing. Stress relief of the metal and out-diffusion of oxygen and other impurities occur during the laser process, similar to the zone-refining technique; this creates a high purity A1 alloy film which suppresses hillock growth. A general improvement in the distribution of contact resistance of the devices is observed on the laser planarized samples with no apparent shift in threshold or breakdown voltages. Pramanik et al. (1989) have shown a significant improvement in contact and via resistances of submicrometer contacts and vias with the laser planarization process with no observable junction degradation. The electromigration resistance of laser processed A1 wafers is significantly superior to the control devices (Boeck et al., 1990). Copper is also a good choice for the laser reflow process. Because Cu has lower reflectivity ( ~ 3 5 % )than A1 ( x 9 0 % ) , a lower incident laser fluence is required to reflow Cu, even though Cu melts at much higher temperature ( x 1035 " C ) than A1 (z660 "C).

9.7 Cluster Tool Technology

After Laser Pulsing

469

Figure 9-32. Laser planarization process.

Because of intense competition in manufacturing quality and cost, together with increasingly complex fabrication processes, future semiconductor manufacturing will require significant efforts toward defect reduction of any given process or tool. As shown in Fig. 9-33, for 4Mb DRAMS,

470

9 Silicon Device Processing

10 20 30 40 50 60 70 80 90

YIELD (70)

Figure 9-33. Relationship between defect density and yield for several DRAM generations.

1.6 defectsicm' equals a 40% yield. That same defect density in the manufacturing

Of Mb provide a Of only l o % , while the yield drops to zero for 64Mb By the year 2ooo' the number of discrete process steps in the manufacturing of advanced DRAM chips is expected to exceed 700, requiring an even more stringent control of both equipment and process induced defects. In addi-

tion, wafers with 300 mm in diameter should become available by the year 2000. The increase in wafer diameter significantly increases the process equipment cost, primarily due to the increased tool complexity to meet the uniformity requirements across the larger wafers. Today, about 60-70% of the cost for an 8 inch wafer fab is spent on equipment. As shown in Fig. 9-34, it will require $ 2 billion fabs to manufacture 1GB DRAMSwith feature sizes of 0.18 pm on wafers of 300-400 nm and five to six levels of interconnection (Chatterjee and Larrabee, 1993). Meanwhile, the typical life cycle of leading-edge ICs has dropped from five years to two or three years. When wafer fabrication areas change to new IC designs, they often need to dispose of still viable process equipment, rapidly escalating the manufacturing cost. As a result, the following trends in Si semiconductor industry could be observed over the past few years: -

Device/circuit scaling; Larger wafers; More dry processes;

Figure 9-34. Escalating ~

costs of wafer fabrication

factories (fabs). 00

9.7 Cluster Tool Technology

More single wafer processes; New cleaning philosophy : minimizing the generation of particles rather than focusing on the removal of the particles once they are on the wafer; Increased automation of real-time process and factory control; Differentiated products; Fast (cycle time), economical (cost) manufacturing of a variety of products (flexibility) with first pass success (quality).

9.7.1 Advantages These requirements provide a significant opportunity for a new class of equipment for future IC manufacturing where largesize single wafers are processed and sequential process steps can be “clustered” into multichambered in situ processing modules or into linked cells of independent modules (Doering, 1992). The single wafer cluster tool technology offers significant advantages in IC manufacturing. The inherent cleanliness of process chambers and wafer transfer environments provide substantial improvements in both film and interface quality due to reduction in particle contamination and reactive impurities (H,O, 0,, etc.). This, together with the reduction of the number of times that a wafer must be “handled” moving between operations, results in lower defect densities/higher yields. In addition, fast processing of new devices moves a company quickly up the learning curve, allowing early product introduction. This in turn can result in higher prices for the product on the wafers as well as increased market share. Reduction of cycle times also accelerates process development and yield/defect learning, an extremely important factor for cost-effective manufacturing. Furthermore, as the wafer size increases,

471

the value of each wafer becomes greater, particularly for ASIC circuits, and the risk of committing a large number of wafers to a batch process becomes significant. In an era of increased attention to process monitoring and real-time control for improved tool reliability, single wafer processing also offers improved diagnostic access, especially in comparison to batch processes. Finally, since new processes can be developed in a “production” module, their transfer from R & D to production may well be shortened. The main functional units of a cluster tool are shown in Fig. 9-35. Main units include the following: -

Central handling platform : contains the transport mechanisms to move wafers from module to module; Cassette stations; Single process modules: provide single wafer processing environments for cleaning, CVD, PVD, RIE, RTP, and other processes. Some of the process modules may involve proprietary design and some may be stand-alone standard process modules ; Batch modules: increase throughput of some slow process steps with batch or minibatch modules. I

Process

Process module

I w+-t

cassette Wafer

Figure 9-35. Main functional units of a cluster tool.

472

9 Silicon Device Processing

An important idea behind cluster tools is that a change in an IC fabrication process only requires a change in process modules. In this fashion, semiconductor manufacturers can accommodate a newly integrated process requiring a completely different set of process steps. They retain the cluster tool platform comprising the cluster controller and the transport and cassette modules with associated pumps, controls and power supplies. Only some of the peripheral process stations would then be needed to be upgraded, expanded. or replaced. The flexible, modular tools can be reconfigured to meet future process requirements developed on stand-alone R & D modules for rapid transfer to manufacturing, reducing retooling costs and extending the lifetime of installed equipment. Accordingly. capital expenditures are considerably reduced. One of the advantages of cluster tools is their capability to facilitate the performance of processes that would otherwise be very difficult or impossible. Most clustering activities are intended to reduce the costs of more sophisticated and advanced integrated processing tools by increasing performance and yield. In some cases, integrated clustering is intended to develop new materials, novel processes, and exotic structures. 9.7.2 Rapid Thermal Processing

Rapid thermal processing (RTP) tools are strategically important for submicrometer manufacturing because of trends towards reduced thermal budget and tightened process control requirements on large diameter Si wafers. The desirable attributes of a RTP tool are rapid lamp heating, cold wall. the capability of rapidly changing the wafer temperature and processing environment for multiple in situ processing, and

single wafer processing. The capability of a rapid ramp rate allows short-time processing with enhanced temperature programmability and range. Since chemical reaction rates are thermally activated and thus usually increase significantly with temperature, much higher manufacturing throughput can be obtained in CVD processes using RTP. This overcomes the primary drawback to single wafer processing. The cold wall aspect is important for CVD applications where deposition takes place primarily on the wafer and not on the chamber wall. This minimizes contamination and particulate problems. The implementation of multiple in situ processing steps within the same equipment has the potential to reduce particulate contamination by improved control of the wafer environment, and increased throughput by reducing overall processing time. The single wafer processing feature is important for large wafer sizes to improve process control. In an era of increased attention to process monitoring and real-time control, single wafer processing also offers improved diagnostic access, especially in comparison to batch processing. Furthermore, each isolated single process module can be integrated or “clustered” to match processing needs in an “application specific” fashion. Various Si technology process modules are being developed in RTP for submicrometer device manufacturing. Formation of SALICIDE and TIN, junction formation, channel dopant profile control, thin gate dielectric formation, native oxide removal, glass reflow, and contact metallurgy sintering are some of these processes. By combining RTP with CVD (RT-CVD), the substrate temperature and the reactive gas flux are used as switches to turn a CVD reaction rapidly ON or OFF. The thermal exposure of the substrate is therefore minimized, allowing

9.7 Cluster Tool Technology

ultrathin film deposition. In addition, precise control of layer thickness, and its composition and structure can be obtained. Furthermore, RT-CVD is capable of in situ multilayer processing for high purity interfaces, an extremely important characteristic of fabricating ultrathin high quality stacked dielectrics. The extremely fine control of layer thickness and composition, and the capability of in situ cleaning and processing by RT-CVD, lead to the possibility of multicycle processing within a single chamber, and have led to exciting breakthroughs in ULSI technologies. Because of its unique characteristics, RT-CVD is becoming the most important process module for integrated processing. In the following, some of the important clusterable processes that employ RTP and RT-CVD are discussed. 9.7.2.1 In Situ Dry Cleaning The structural, chemical, and electrical properties of various interfaces between different layers (semiconductor/dielectric, semiconductor/semiconductor,and metal/ semiconductor) strongly influence the overall performance and reliability of the resulting devices. Approximately 40 YOof the processes used to fabricate today’s ICs involve wafer cleaning steps. Wet cleaning processes for wafer surface cleaning are used exclusively to remove both particles and contaminants remaining on wafer surfaces after each process. As the devices become smaller and smaller, it will be more and more difficult for wet chemicals to clean abrupt contact holes and deep trenches. In addition, a much higher level of cleanliness is required for wafer surfaces of deep submicrometer devices. Furthermore, the large amount of chemical wastes generated by such processes are hazardous to the environment and their proper treat-

473

ment and disposal have become very expensive. Because of the equipment and process incompatibility, traditional wet cleaning processes have been prevented from being integrated into a cluster tool. For these reasons, significant advances must be made in cleaning technology. One promising possibility is to use vapor phase or gas phase dry cleaning technology, which requires only minute amounts of chemicals (Moslehi et al., 1992). Compared to liquid-based compositions, reactive gas species enjoy a greater access to the wafer surface because gas molecules don’t have to diffuse through a thick water layer to reach the wafer. As a result, a gas phase system uses anhydrous H F from one 5 lb (-2.3 kg) HF bottle to process 90 000 wafers, compared to 2000 lb (- 900 kg) of 10% H F for a wet bench system. The typical method used for in situ cleaning in RT-CVD is the H, pre-bake ( 2 1000°C, 2 1 min). Limits may be placed on the contribution of the in situ cleaning to the total process thermal exposure in order to reduce autodoping and broadening of any existing doping profiles. As long as the partial pressures of 0, and H,O are kept below the critical values for a given temperature, the fast oxide etching rates reported by Ghidini and Smith (1994) and Smith and Ghidini (1982) should allow the pre-bake time to be reduced to the order of seconds. Recently, conditions have been established (not due to hydrogen passivation by H F treatment) by which Si and Ge,Si - , epitaxies were achieved with 500-800°C H, pre-baking for 15-30 s (Jung et al., 1991a). Recently, in situ anhydrous HF (AHF) cleaning with H, in the range of 325-750°C has been demonstrated (Apte et al., 1991). The AHF cleaning process is simple and manufacturable, and it is selective in a way that it removes surface native oxides, but leaves thermal

474

9 Silicon Device Processing

oxides intact. The other potential low temperature gas phase RTP cleaning to remove native oxide layers and other surface contaminants is germane-assisted cleaning (Moslehi et al., 1992). The cleaning process composition consists of a mixture of GeH, and H, . The germane-to-hydrogen flow ratio is kept very low to prevent deposition or surface nucleation of germanium during the thermal cleaning process. The GeH,/ H, processes clean the Si substrate surface by direct reaction of GeH, with the native oxide layer, producing volatile germanium oxide species (GeO). Although this process works well on native oxides and CVD oxides, it does not easily remove thermally grown oxides. These RTP-based gas phase dry etching techniques can be easily integrated into various RTP-based thin-film growth and deposition process modules in a cluster tool environment. 9.7.2.2 Interface Engineering Interface engineering is critical to high speed bipolar and Bi-CMOS processes. It consists of the steps of surface cleaning, controlled interfacial oxide or nitride growth, and polysilicon deposition (RTP cleaning, oxidelnitride growth by RTP, in situ doped poly-Si deposition by RTCVD). 9.7.2.3 Gate Stack of Oxide and Oxynitride The gate stack process is a good example of a process which may potentially benefit from RTP cluster tool processing. It consists of RTP cleaning, gate dielectrics growth by RTP, and in situ poly-Si deposition by RT-CVD. Critical interfaces are kept free of contamination in a cluster tool to achieve excellent device performance and reliability. An excellent example is the fabrication of a simple MOS capacitor. The MOS capacitor can be fabricated com-

pletely within the same RT-CVD chamber, utilizing the processes of rapid thermal oxidation (RTO) and in situ doped poly-Si deposition. Additional processing can easily transform the MOS capacitor into a MOSFET. High quality MOS capacitors and MOSFETs have been demonstrated (Sturm et al., 1986). For a 290 8, gate oxide cm’, valand capacitor area of 4.5 x ues of 5 x lo9 cm-’ eV-l for the midgap interface state density, ~ 1 0 1 0cm-, for the fixed charges, and 10 MV/cm for the breakdown field were achieved. Oxynitride gate dielectrics grown by RTP of Si in presence of N,O are superior to conventional SiO, grown ones in 0, (N,O oxides have significantly less charge trapping and interface state generation under constant current stress, a tenfold increase in both charge-to breakdown and time-to-breakdown values, and much better dopant diffusion barrier properties) (Hwang et al., 1990). The lifetime of MOSFETs with N,O gate oxides is almost one order of magnitude longer than that of the control devices under identical channel hot-carrier stress conditions (Hwang et al., 1991). Stacked nitride/oxide (NO) films have received considerable attention due to their low defect density, low leakage current, diffusion barrier property, and excellent long-term reliability (Watanabe et al., 1984; Young et al., 1988; Weinberg et al., 1990). Charge trapping in the nitride or at the nitride/oxide interface has limited the application of these films to memory elements. It has been demonstrated that the charge trapping in NO layers can be considerably reduced by in situ multi-layer processing for high purity interfaces in a RT-CVD reactor. In the experiments, the bottom oxide of the NO structure is prepared by RTO in 0, at 1050°C followed by in situ nitride RT-CVD deposition us-

9.7 Cluster Tool Technology

ing SiH, and NH, diluted in N, at 850°C. The nominal bottom oxide thickness was 40 8, and the nitride thickness was 30 8,. The leakage current of the control oxide fabricated by RTO at 1050°C and NO devices are comparable at low fields. Capacitors with NO dielectrics exhibited V,, very close to that of the control oxide. Both control and NO devices exhibited Dit values of ~2 x 10" cm-2 eV-', indicating excellent interfacial integrity. NO devices showed dramatic improvements in breakdown field distribution over the control oxides, although the control oxide and the bottom oxide of the NO layers were grown in the same RT-CVD reactor with the same recipe and in consecutive order. The high quality top nitride covered up or sealed the defects of the bottom oxide, thus significantly reducing the frequency of low-field breakdown events (Roy et al., 1988). Another possibility is that the in situ nitride deposition effectively protects the oxide from contamination before poly-Si deposition. 9.7.2.4 Deposition of DRAM Storage Dielectrics The application of RT-CVD technology to the formation of ultra-high density DRAM storage dielectrics is becoming increasingly important. The process could consist of RTP cleaning/surface passivation, storage dielectric deposition by RTCVD, in situ post-deposition RTP annealing, deposition of in situ doped polysilicon top electrode by RT-CVD. For oxide/nitride/oxide (ONO) DRAM storage dielectrics, the bottom SiO, over the bottom polysilicon electrode plays an important role in the film integrity. The reason is that the thin bottom S O , , usually a low-grade native SiO, , degrades the quality of O N 0 films. In addition, the bot-

475

tom SiO, prevents further scaling of the effective dielectric thickness and thus limits the maximum attainable capacitance. Therefore, it is extremely critical for advanced DRAM manufacturing to eliminate the native oxides completely prior to dielectric deposition. It has been demonstrated that by using rapid thermal nitridation (RTN) in pure NH, of poly-Si surface prior to Si,N, deposition, (bottom native SiO, free) Si,N, dielectric (t,,, eff M 35 A) with enhanced reliability can be achieved (Lo et al., 1992). The defect-related dielectric breakdown caused by low-grade native SiO, is completely eliminated by the use of RTN. In addition, capacitors with RTN treatment have an improved lifetime (by factor M lo3) than the ones without RTN. The ultrathin stacked NO layer can also be fabricated by in situ multiprocessing (RTMP) (Ando et al., 1993). As shown in Fig. 9-36 a, the multiprocessing steps include in situ surface cleaning, RTN, rapid thermal CVD of the Si,N, films, and rapid thermal CVD of poly-Si. All these steps are carried out in sequence without lifting the vacuum. Elimination of interfacial oxides at the Si,N,/Si interface leads to high quality nitride films with low leakage current density and extremely high reliability. As shown in Fig. 9-36 b, the TDDB characteristics of Si,N, films prepared by in situ RTMP are improved about lo4 times over conventional LPCVD Si,N, films. This result clearly demonstrated the capability of in situ multiprocessing for the fabrication of high quality ultrathin films for ULSI applications. 9.7.2.5 Selective Deposition Processes Process complexity and number of mask levels steadily increases with each generation of IC technology. Projections of present trends indicate as many as 700 process

476

9 Silicon Device Processing

. .

4 6 8 Tlme (mln)

In.ahr RTMP

7 Stress time (sec)

Figure 9-36. ( a ) Schematic time- temperature profile of in situ RTMP processing for fabricating D R A M storage capacitors. (b) Comparison of TDDB characteristics of dielectrics fabricated by various techniques.

steps in IC technologies by the year 2000. The increased use of selective processes is one way to greatly reduce the number of process steps, since each selective process can eliminate many other process steps (usually mask levels, lithography and etching steps). Selective metal deposition (tungsten. copper. TiN) and selective silicide (TiSi,) processes are two of the better known and more mature of the various selective processes. Other possibilities include selective epitaxy processes for advanced CMOS isolation and for raised source drain CMOS devices. Selective processes are emphasized here because they provide considerable leverage for cluster

tools. They eliminate the need for masking steps and facilitate more sequential processing steps within a single cluster tool before the wafer must be removed for lithography steps. Selective epitaxy growth has been applied to a novel transistor structure, the low-impurity-channel transistor (LICT), for advanced CMOS applications. By selectively growing a thin undoped Si epilayer on top of the heavily-doped wells, threshold voltages can be lowered and band bending made more gradual, thereby weakening the effective field for carriers and reducing surface-roughness scattering. In addition, carrier freeze-out is eliminated since no channel implantation is performed. The heavily-doped wells are for sharpening turn-offs and preventing punch-through. Fairly good transistor operation has been achieved for 0.1 pm CMOS devices implementing the LICT structure (Aoki et al., 1990). Critical to LICTs are steep impurity profiles which makes RT-CVD ideal for LICT fabrication since RT-CVD can provide minimal autodoping and out-diffusion of impurities (Gibbons et al., 1985; Lee at al., 1989; Jung et al., 1991 b).

9.7.2.6 Ultra-Shallow Junction Formation Recently, a novel approach based on surface chemical adsorption of dissolvements from induced dopant gas molecules has been developed by Nishizawa et al. (1990b) and Inada et al. (1992) for very shallow, high quality p+-njunction formation. In this process boron atoms are incorporated into Si by diffusion in an oxygen-free atmosphere at a relatively low temperature. This process differs from the conventional diffusion process in which boron diffusion is performed in an oxygenrich environment. Kiyota et al. (1994) have developed a rapid thermal vapor-phase

9.7 Cluster Tool Technology

doping technique to fabricate ultra-shallow boron-doped junctions with junction depth less than 30 nm and surface boron concentration of 5.8 x 10'' ~ m - ~ .

9.7.2.7 Integrated CMOS Processing Based on RTP A 0.25 pm CMOS technology has been developed and demonstrated with all-RTP thermal processing (Moslehi et al., 1993a). These RTPs cover a processing temperature range of 450" to 1100"C. The process features are listed in Table 9-12. Excellent CMOS transistors with considerable process simplification have been established. Improved RTP control over furnace was also demonstrated. These results show the effective use of RTP for IC manufacturing.

9.7.2.8 Ge,Si, by RT-CVD

477

/Si Heteroepitaxy

RT-CVD was the first non-UHV technique used to demonstrate high performance Ge,Si -,/Si heterojunction bipolar transistors (HBTs). Early work showed higher current gains of 400 compared to Si devices and high unity gain cut off frequencies of 28 GHz (Kamins et al., 1989). Improved HBT performance has been obtained by controlling base dopant out-diffusion and using graded base layers (Sturm and Prinz, 1991). More recently, a double base HBT has been demonstrated which could find application as a single-transistor NAND gate (Prinz et al., 1992). Si, -,Ge,/Si heterostructure FETs have a potential for higher performance due to higher carrier mobilities in strained Si and

Table 9-12. List of the lamp-heated RTP-based CMOS fabrication processes (Moslehi et al., 1993 a). RTP-based processes

Applications

RTP parameter domain

Germane clean

split gate formation

Dry RTO

gate oxide, PBL oxide

Wet RTO Source/drain RTA and gate RTA

thick oxides ("0NED"-tank and sacrificial oxide) S/D activation, gate annealing

RTP tank formation

CMOS n & p well formation

LPCVD polysilicon

CMOS gate formation

LPCVD amorphous Si

CMOS gate formation

LPCVD tungsten

multilevel metal

TiNITiSi, RTA reaction and annealing RTP sinter (FGA)

Salicide, silicided contacts forming gas annealing

LPCVD nitride

PBL nitride deposition

LPCVD oxide

oxide spacers, undoped oxide

65O-75O0C, low pressure (75OoC/15 torr) GeH,/H, 1000- 1050 "C, high pressure (1O0O2C/65Otorr) 0, 950- lOOO"C, high pressure (1OOO0C/65O torr) H,O/O, 950-1O5O0C, high pressure (95O0C/65OTorr) Ar or NH, 1050- 1100 "C, high pressure (11OO0C/65Otorr) NH, 65O-75OcC, low pressure (650T/15 torr) SiH,/Ar 500-590°C. low pressure (560 "C/15 torr) SiH,/Ar 475 -500 "C, low pressure (475 "(720 torr) SiH,/H,/WF,/Ar 65O-75O0C, low pressure (65O0/75O0C/1torr) N,, Ar 450-475 "C, high pressure (475"C/650 torr) H,/N, 80O-85O0C, low pressure (3 torr) SiH,/NH, 7O0-75O0C, low pressure (740 "C/l torr) TEOSIO,

478

9 Silicon Device Processing

Si, -,Ge, channels. Higher hole mobilities at room temperature have been achieved in GeSi/Si heterostructure FETs grown by RT-CVD with a buried SiGe channel compared to a silicon surface channel (Garone et al., 1992). Similarly, improvements in electron mobility have been reported in both surface and buried tensile strained Si channels on top of a relaxed Sio.,,Geo,29 layer (Welser et al., 1992). Peak effective mobilities were 2.2 times larger than those in devices fabricated in bulk silicon at room temperature. Si, -,Ge, alloys could provide low cost alternatives to compound semiconductors in the fabrication of long wavelength receivers and other optoelectronic integrated circuits due to the well-established Si VLSI technology. By adjusting the Ge content in the SiGe layers the operating wavelength can be tuned in the technologically important 1.3 to 1.55 pm range. RT-CVD has much to offer in growing epitaxial GeSi layers required for such devices. Low loss waveguides and directional couplers have been fabricated (Mayer et al., 1991). SiGe/ Si superlattice waveguide pin photodetectors with high internal quantum efficiency and low dark currents that can operate at 1.5 Gbit/s at 1.3 pm have been demonstrated (Jalali et al., 1992). Evidence of the fine control with which superlattice layers can be grown by RT-CVD is seen in the growth of a 50 period superlattice containing a 24 8, SiGe layer and a 23 8, Si layer (Sturm et al., 1991). The ability to rapidly switch the gases and growth temperature enables the optimization of growth temperature of individual layers, resulting in the realization of multiple quantum well (MQW) structures with minimum interdiffusion and high throughput. The SiGe layers are grown at low temperatures (550"-650 "C) to avoid islanding growth and Si barrier layers are grown at some-

what higher temperatures (700" - 800 "C) in order to get adequate growth rates. The wide range of growth rates that RT-CVD can provide could be applied to the growth of thick waveguide layers and thin MQW layers to obtain integrated waveguidephotodetector structures. Further improvements in device performance can be expected utilizing the capability of RTCVD to grow selective epitaxial SiGe layers (Kamins et al., 1992) and SiGe on silicon-on-insulator (SOI) (Hsieh et al., 1991) structures. Commercial versions of RTP modules for CVD are not available with the uniformity and control required for the manufacturing environment. This is primarily due to the difficulties of measurement and control of wafer temperature and its uniformity across a large size wafer. The non-contact measurement and control of absolute temperature and of temperature uniformity across a wafer have proven to be major problems with single wafer RTP processing. Research is presently underway at many laboratories addressing these issues, and progress is being made (Moslehi et al., 1992; Peyton and Kwong, 1990). For example, the use of multi-zone heating techniques appear very promising for achieving process uniformity across a wafer. Several approaches are being explored for surface emissivity corrections to be used with non-contact temperature measurements in order to control the temperature magnitude as seen by a pyrometer looking at a wafer. All of these approaches appear promising but at present the single most important limitation is the lack of an RTP module design with acceptable process uniformity and control.

9.7 Cluster Tool Technology

9.7.3 Single-Wafer Integrated Processing One factor is now driving clustered integrated processing toward a broader spectrum of applications in which sequential processes with very different character (temperature, chemistry, pressure) are linked in clusters; that is the significant benefits from exploiting the advantages of integrated processing by the possibility it offers to mix and match whichever process combinations will result in the highest quality materials and structures. To tailormake films with matching physical, structural, dielectric, mechanical, chemical, crystallographic, and electrical properties, the existing and future processes must be combined together. Some of the important clusterable processes are: Cleaning, CVD, PVD, and etching processes must be integrated to cope with topographical problems in the upper levels of metallization, including multilayered metallization. Self-aligned silicide process (cleaning, PVD, RTP, etching). Multilevel film etching or multistep etching. This is necessary for complex structures. Since it may require different chemistries and etching technologies for individual steps, cross contamination and particulates become important issues (cleaning, etching). Interface engineering. This is critical to bipolar and Bi-CMOS processes. It consists of the steps of surface cleaning, controlled interfacial oxide or nitride growth, and polysilicon growth (cleaning, RTP, CVD). Selective deposition/growth processes rely on well-defined, properly prepared surfaces which are highly amenable to integrated processing (cleaning, passivation, CVD). The increased use of selective processes is one way to greatly re-

479

duce the number of process steps, since each selective process can eliminate many other process steps (usually mask levels, lithography and etching steps). Selective processes are emphasized here because they provide considerable leverage for cluster tools. Gate stack of oxide (or oxynitride) and in situ doped polysilicon (cleaning, RTP, CVD). The gate stack process is a good example of a process which may potentially benefit from cluster tool processing (Apte et al., 1992). It consists of pre-gate cleaning, gate dielectric growth, and polysilicon electrode deposition and annealing. Critical interfaces are kept contamination-free in a cluster tool to achieve excellent device performance and reliability. DRAM storage dielectrics deposition (cleaning, CVD, RTP). Ultra shallow junction formation based on surface chemical adsorption of dissolvements from induced dopant gas molecules (cleaning, RTP) (Nishizawa et al., 1990 b; Inada et al., 1992; Kiyota et al., 1994). BPSG flow (cleaning, CVD, high pressure RTP). To reduce the thermal budget for reflow, a single-wafer high-pressure RTP system has been used to reflow BPSG in steam or nitrogen at temperatures as low as 720°C. Oxide spacer/collar formation (etching, CVD, etching) (Matuszak et al., 1989).

Throughput has been an issue for cluster tools. For a single wafer process, 60 wafers per hour has been considered a reasonable figure. A substantial number of single wafer processes used or being considered in cluster tools achieve this value, including cleaning, stripping, RTP, and many etching processes. However, other etch processes and many CVD processes take

480

9 Silicon Device Processing

longer than 1 min. When these slower processes are integrated into the fabrication of cluster tools, typical throughputs are 10 to 25 wafers per hour. A cluster tool's throughput is dictated by the slowest or "bottleneck" process and to a lesser extent by machine throughput (i.e., the speed of wafer handling including pumping and venting). Significant efforts are being made to reduce the process times for the potential bottleneck processes. For some of the longer-time processes, batch process modules may be required. However. one of the unique characteristics of single-wafer processing is the ability to manufacture small lots with a fast turnaround. This is extremely attractive for process development and for applications where short cycle times are significantly more valuable than the wafer cost. Simulation results have shown that for single wafer lots running through the cluster fabs. the theoretical cycle times can be as short as 5 days. This should be extremely valuable for small-volume ASIC runs. A performance comparison of conventional fabs and cluster-based fabs is made in (Wood et al., 1991), in which the cost per wafer is plotted against average cycle-time. As can be seen clearly, at high throughput, the wafer costs are comparable. However, for the low throughput time range, the wafer costs are much higher for conventional fabs. The total use of single-wafer processing for fast-cycle-time IC production has been demonstrated recently (Moslehi et al., 1993 b). Complete 0.35 pm CMOS process integration and 3-day CMOS IC manufacturing cycle time have been established with all-RTP thermal processing. The future of cluster tools and the extent to which cluster tools will permeate and dominate IC manufacturing depends on the successful development of a broader

spectrum of single wafer processing technologies. In addition, to obtain fundamental mechanistic insight and to develop new levels of process control and material/ structure quality, the wafer surface and the process environment during the process must be studied in detail, using a variety of sophisticated techniques from surface science as well as mass and optical spectroscopy. If proposed benefits of improved process control, process configurability on a wafer-to-wafer basis and easy mixing of process technologies are to be realized, improved process sensors must be available and used in cluster tools. There is a great lack of adequate process sensors for key process variables including gas species and gas flows at the wafer, and thicknesses of films depositing or being etched on the wafer. Most sensors, if available, provide either indirect data or measure parameters at some point far off the wafer surface. It may be possible to use such remotely measured parameters with appropriate process and equipment models to infer values at the wafer. However, much research, development and process characterization work remains to be done.

9.8 References .Vote: I E D M stands for International Electron Device Meeting.

Abe. T.. et al. (1992). ECS Softbound Proc. 92-7, p. 200. Adachi. H.. Nishikawa, H., Komatsu, Y., Hourai. H., Sano. M., Shigamatsu, T.(1992), Mater. Res. Soc. S j m p . Proc. 262. 815. Adams. A. C.. Capio, C. P., (1981), J. Electrochem. Soc. 128. 423. Ahn. J.. Kwong. D . L. (1992), IEEE Electron. Device Lett. 13. 494. Ahn. J.. Ting. W.. Kwong. D . L. (1992a), IEEE Electron. Device Lett. 13, 1 1 7. Ahn. J.. Ting, W., Kwong, D. L. (1992 b). IEEE Elect r m . Device Lett. 13, 186. Ajmera, A. C.. Rozgonyi, G. A. (1986), Appl. Phys. Lett. 4 9 . 1269.

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Shioya. Y.. Kawzarnura, S.. Kobayashi, I., Maeda, M.. Yanagida. K . (1987b). J. Appl. Phys. 6 1 , 5102. Smith, G . C. (1989). in: Workshop on Tungsten and Other Refractor), Metals for VLSI Applications 1988: Blewer, R.. McConica, C. (Eds.). Pittsburgh, PA: Materials Research Society, p. 275. Smith. E W.. Ghidini. G. (1982), J. Electrochem. Soc. 129, 1300. Stirnmell. J. (1986). J. Vue. Sei. Technol. B 4 , 1377. Sturm, J. C.. Prinz. E. J. (1991). IEEE Electron Device Lett. 12, 42. Sturm. J. C., Gronet. C. M., King, C . A,. Wilson, S . D., Gibbons. J. F. (1986). IEEE Electron Device Lett. 7 , 577. Sturm, J. C.. Schwartz. P. V.. Prinz. E. J., Manoharan. H . (1991). J. Vac. Sci. Technol. B 9 , 204. Sumiya. T.. Hirase. I.. Rutin, D., Ukishima, S., Schack. M., Shishikura, M., Matsuura, M.. Itoh, A. (1987). in: Proc. 10th Int. Conf. on Chemical Vapor Deposition: Cullen. G . W. (Ed.). Pennington, N J : Electrochem. SOC..p. 645. Sun, J. Y.-C.. Wong. C. Y.. Taur. Y.. Hsu, C . C.-H. (1989). VLSI Tech. Swip., p. 17. Sung. J. M.. Lu. C. Y.. Chen, M . L., Hillenius, S. J.. Lindenberger. W. S.. Manchanda, L.. Smith. T. E., Wang. S. J. (1989). IEDM Tech. Digest. New York: IEEE, p. 447. Sung. J. M., Lu. C. Y.. Fritzinger. L. B., Sheng. T. T., Lee. K . H. (1990). IEEE Electron Device Lett. 11, 549. Takeda. E.. et al. (1985). IEEE Trans. Electron DeL'ices 32, 322. Takemura. H.. Ohi. S., Sugiyama, M., Tashiro, T.. Nakamae. M. (1987), IEDM Tech. Digest. New York: IEEE. p. 375. Tan, T. Y. (1977). Appl. Phys. Lett. 30, 175. Tanaka, A , , Yamaji. T.. Nishikawa, S. (1991), Jpn. J. Appl. PI1J.s. Lett. 30, L775. Taur. Y. et al. (1993). IED,M Tech. Digest. New York: IEEE. p. 127. Tay, S. P.. Ellul. J. P.. White, J. J., King, M . I. H . (1987). J. Electrochem. SOC.134, 1484. Tay, S. P., Kalnitsky. A , . Kelly, G.. Ellul. J. P.. DeLalio. P.. Irene. E. A . (1990). J. Electrochern. SOC. 137, 3579. Telford, S . G., Eizenberg. M., Change, M., Sinha, A. K.. Gow. T. R . (1993). Appl. Ph1.s. Lett. 62, 1766. Teng, C. W.. Slawinski, C., Hunter, W. R. (1984). IEDM Tech. DigrJr. New York: IEEE. p. 586. Teng, C . W.. et al. (1985). IEEE Trans. Electron Devices 32, 124. Thomas. M. E., et al. (1991). Tech. Proc. Semicond. Jpn. I S E h f I j . p. 295. Ting, P. L., et al. (1987). Proc. IEEE VLSI Multile\'el Interconnection Conf., p.61. Ting, C. H.. et al. (1989), Proc. V-MIC Conf., p. 491. Travid. E. 0..et al. (1990). IEDM Tech. Digest. New York: IEEE, p. 47. Tsai. M. Y.. Streetrnan, B. G.. Williams, P., Evans Jr.. C. A . (1978). Appl. PhJss. Lett. 32, 144.

Tseng. H. H., Tobin, P. J., Hayden, J. D., Chang, K . M . (1991), IEDM Tech. Digest. New York: IEEE, p. 75. Tseng, H. H., et al. (1993). IEDM Tech. Digest. New York: IEEE, p. 321. Tsuboushi, K., M a w , K . (1992). J. Vue. Sci. Technol. A IO, 856. Tsuya, H . (1991). The 9th Workshop o f U L S l o n Ultra Clean Tech., p. 5. Usami. A,, Ando, M., Tsunekane, M., Wada, T. (1992). IEEE Trans. Electron Devices 39, 105. Ushiku, A , , et al. (1993), VLSI Tech. Symp., p. 121. Vasquez, R. P., Madhukar. A. (1985), Appl. Phys. Lett. 47, 998. Vasquez, R. P., Madhukar, A . (1986), J. Appl. Phys. 60, 234. Verhaverbeke, S., Meuris, M., Mertens, P. W., Heyns, M. M., Philipossian, A,, Graf, D., Schnegg, R. (1991), IEDM Tech. Digest. New York: IEEE, p. 71. Verhaverbeke, S., et al. (1992), V L S I Tech. Symp., p. 22. Walters. M., Reisman, A. (1990), J. Electrochem. Soc. 137, 3596. Wang, S.-Q., Ong, E. (1990), Proc. 7th Int. IEEE VLSI Multilevel Interconnection Conf., Santa Clara, CA. p. 431. Wang, M.. Bradbury, D.. Hu, H . K., Chiu, K . Y. (1991), VLSI, 41. Watanabe, T., Ishikawa, M., Kumagai, J. (1984), IEDM Technical Digest. New York: IEEE, p. 173. Weber, E. R. (1988). Properties of Silicon. London: INSPEC. p. 236. Weber, E. R . (1990). in: Semiconductor Silicon, Vol. 90- 7: Huff. H . R., Barraclough, K. G., Chikawa, J. I. (Eds). Pennington, N J : Electrochem. SOC.,p. 585. Wei, C. Y , et al. (1992), IEEE Trans. Electron Devices 38, 2433. Weinberg, Z. A,, Stein, K. J., Nguyen, T. N., Sun, J. Y (1990), Appl. Phys. Lett. 57, 1248. Welser, J.. Hoyt, J. L., Gibbons, J. F. (1992). IEDM Tech. Digest. New York: IEEE, 31, 7 . Wen. D. S., et al. (1991), VLSI Tech. Symp., p. 83. Wittmer, M. (1985), J. Vac. Sci. Technol. A 3 , 1797. Wittmer, M.. Melchior. M . (1982), Thin Solid Films 93, 397. Wong. C. Y.. Lai, F. S. (1986), Appl. Phys. Lett. 48, 1658. Wong, C . Y.. Sun, J. Y.-C., Taur, Y., Oh, C. S., Angelucci, R.. Davari. B. (1988). IEDM Tech. Digest. New York: IEEE. p. 238. Wood. S., et al. (1991), Proc. Int. Semiconductor Manufacturing Sci. S j w p . , p. 208. Wright, P. J.. Saraswat, K. C. (1988), IEEE Trans. Electron Devices 36, 1707. Wright, P. J., Saraswat, K . C . (1989), IEEE Trans. Electron Devices 36, 879. Wright, P. J., Kermani, A,, Saraswat, K . C. (1990), IEEE Trans. Electron Devices 37, 1836.

9.8 References

Wu, T. H. T., Bosler, R. S., Lamartine, B. C., Gregory, R. B., Tompkins, H. G . (1988), J. Vac. Sci. Technol. B 6 , 1701. Wu, C. P., McGinn, J. T., Hewitt, L. R. (1989a), J. Electron. Mater. 18, 121. Wu, I. W., Koyanagi, M., Holland, S., Huang, T. Y, Mikkelsen Jr., J. C., Bruce, R. H., Chiang, A. (1989b), J. Electrochem. SOC.136, 1638. Xu, X., Kuehn, R. T., Ozturk, M. C., Wortman, J. J., Nemanich, R. J., Harris, G. S., Maher, D. M. (1993), J. Electron. Mater. 22, 335. Yamabe, K. (1990), in: Semiconductor Silicon, Vol. 90-7: Huff, H. R., Barraclough, K. G., Chikawa, J. I. (Eds). Pennington, NJ: Electrochem. SOC., p. 349. Yamabe, K., Imai, K. (1981), IEEE Trans. Electron Devices 34, 1681. Yamabe, Y., Taniguchi, T., Matsush*ta, Y (1983), Proc. Int. Reliability Physics Symp. New York: IEEE, p. 184. Yamagishi, H., Fumegawa, I., Fujimake, N., Katayama, M. (1992), Semiconductor Sci. Technol. 7 , A135. Yang, W., Jayaraman, R., Sodini, C. G. (1988), IEEE Trans. Electron Devices 35, 935. Yokoyama, N., Hinode, K., Homma, Y. (1989), J. Electrochem. SOC.136, 882.

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Yokoyama, N., Homma, Y, Hinode, K., Mukai, K. (1990), U. S. Patent 4 897 709. Yoon, G . W., Ahn, J., Lo, G. Q.,Kwong, D. L. (1993a), Int. Conf. S S D M , p. 145. Yoon, G. W., Joshi, A. B., Kim, J., Kwong, D. L. (1993 b), IEEE Electron Device Lett. 14, 179. Young, K. K., Hu, C., Oldham, W. (1988), ZEEE Electron Device Lett. 9, 616. Yu, M. L., Eldridge, B. N., Joshi, R. V. (1989), in: Tungsten and Other Refractory Metals for VLSI Applications, Vol. IV: Blewer, A,, McConica, C. M. (Eds.). Pittsburgh, PA: Materials Research Society, p. 221. Yu, C., Fazan, P. C., Mathews, V. K., Doan, T. T. (1992), Appl. Phys. Lett. 61, 1344. Zorinsky, E. J., et al. (1986), IEDM Tech. Digest. New York: IEEE, p. 431.

General Reading Tungsten and Other Refractory Metals for VLSI Applications, Vols. I, 11, 111, IV, V, VI: Pittsburgh, PA: Materials Research Society.

10 Compound Semiconductor Device Processing

John M Parsey. Jr

Motorola. Semiconductor Products Sector. III-V Device Development Laboratory. Tempe. AZ. U.S.A.

List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 490 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 10.1 10.2 Doping Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 10.2.1 Ion Implantation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 10.2.2 Diffusion Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 10.2.3 Epitaxial Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 10.3 Isolation Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 515 10.3.1 Mesa Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Ion Implantation Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . 517 522 10.3.3 Sidegating and Backgating . . . . . . . . . . . . . . . . . . . . . . . . . Diffusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 525 10.5 Etching Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 532 10.5.1 Wet Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.2 Dry Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 10.6 Ohmic Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 Schottky Barriers and Gates . . . . . . . . . . . . . . . . . . . . . . . 552 10.7 10.8 Annealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Dielectrics and Interlayer Isolation . . . . . . . . . . . . . . . . . . . . 567 10.9 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 10.10 Metallization and Liftoff Processes . . . . . . . . . . . . . . . . . . . . 581 10.1 1 10.1 1.1 Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 10.11.2 Liftoff Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 10.12 Backside Processing and Die Separation . . . . . . . . . . . . . . . . . 590 10.12.1 Backside Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 597 10.12.2 Die Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 10.13

490

10 Compound Semiconductor Device Processing

List of Symbols and Abbreviations Richardson constant change in lattice parameter concentration: capacitance diffusivity diffusion coefficient activation energy conduction band energy donor energy level Fermi energy semiconductor energy gap valence band energy maximum oscillation frequency transconductance drain-source current (units are mA/mm) reverse bias saturation current thermionic current flux channel saturation current density Boltzmann constant; wave vector; segregation coefficient effective length length ion mass ideality factor charge resistance range scatter time; thickness temperature voltage applied voltage built-in potential drain-source voltage gate- source voltage impressed voltage sidegating voltage width effective contact width direction coordinates thermal expansion coefficient dielectric constant thermal conductivity

List of Symbols and Abbreviations

4JI3 $1"

X.. AC CBE C-HIGFET CMOS

CVD DC ECR ECRE EOR erfc FA FIB FMA GSE GSMBE HBT HEMT HFET H IGFET HPA HV IC JFET LDD LEC LPE LTB MBE MESFET MIS MOCVD MODFET PCM PE PECVD pHEMT PR RF RIBE

resistivity Schottky barrier height metal work function electron affinity alternating current chemical beam epitaxy complementary heterostructure insulated-gate field-effect transistor complementary metal oxide silicon compound semiconductor chemical vapor deposition direct current electron-cyclotron resonance electron-cyclotron resonance etching end-of-range complementary error function furnace annealing focused ion beam failure mode analysis gas-source epitaxy gas-source molecular beam epitaxy heterostructure bipolar transistor high electron mobility transistor heterostructure field-effect transistor heterostructure insulated-gate field-effect transistor high power amplifier high vacuum integrated circuit junction field-effect transistor lightly-doped drain liquid encapsulated Czochralski liquid-phase epitaxy low-temperature buffer molecular beam epitaxy metal- semiconductor field-effect transistor metal-insulator-semiconductor metal-organic chemical vapor deposition modulation-doped field-effect transistor process control module plasma etching; piezo-electric plasma-enhanced chemical vapor deposition pseudomorphic high electron mobility transistor photoresist radio frequency reactive ion beam etching

491

492

10 Compound Semiconductor Device Processing

RIE RTA SAGFET SAINT SARGIC SEM SPC TEM UHV

reactive ion etching rapid thermal annealing self-aligned gate field-effect transistor self-aligned implantation for n+ layer technology self-aligned refractory gate integrated circuit scanning electron microscope statistical process control transmission electron microscope ultra-high vacuum ultraviolet vertical cavity surface emitting laser vapor phase epitaxy

VCSEL VPE

Companies AT - Assembly Technology, Kulicke and Soffa Industries, Inc., Willow Grove, PA. Disco Hi-Tec America, Inc., Tempe, AZ. Dynatex International, Santa Rosa, CA. Electrotech Corp., Santa Rosa, CA. Motorola, Inc., Schaumburg, IL. Nitto Denko Corp., Ltd., Tokyo. Plasmatherm, St. Petersburg, FL. TriQuint Semiconductor, Inc., Beaverton, OR. Vitesse Semiconductor Corp., Camarillo, CA.

10.1 Introduction

10.1 Introduction In the latter half of the 1990s, there has been a dramatic paradigm shift in the compound semiconductor field. Ion-implanted processes are being rapidly displaced by epitaxy-based approaches, as operating frequencies move well above - 1 GHz. The superior performance offered by epitaxial materials has become quite evident. Manufacturers are responding to these market demands with materials and processes to support high frequency communications and digital signal processing. Ion implanted metal-semiconductor field effect transistors (MESFET), and even high electron mobility transistor (HEMT) devices, are giving way to pseudomorphic high electron mobility transistors (pHEMT) and heterostructure bipolar transistors (HBT) (for further information on these devices, see Daembkes, 1991; or Ali et al., 1991). The compound semiconductor materials GaAs, InP, and related ternary compounds, such as InGaAs, AlGaAs, and InGaP, are used for the manufacture of ultrahigh speed analog, digital, and microwave devices, light-emitting devices such as lasers and light-emitting diodes, high speed electrical and photonic detectors, and solar cells. The last decade has seen exciting gains and improvements in device processing and process development. Wafer fabrication processes have stabilized, and device structures have begun to converge as “ideal” epitaxial structures have evolved, metallurgical interactions have been understood, and manufacturers incorporate the developments of the past decade into their standard process flows. Complex integrated circuits containing well in excess of 100 000 gates have been fabricated for digital applications (Vitesse, 1990; Tsen et al., 1993). Using new technology, CGaAsTM (Motorola) digital devices

493

with more than 1 17 000 transistors have been manufactured (Brown, 1998). At the same time device dimensions continue to shrink: 0.7-0.5 pm gate lengths are commonplace (Gamand et al., 1988; Matsunaga et al., 1989; Saunier et al., 1988), devices with 0.3 pm gates are in development (Thiede et al., 1998), and critical dimensions of less than 100 nm have been created in the laboratories (Bernstein and Ferry, 1988; Han et al., 1990; Studebaker, 1994; Pereiaslavets et al., 1996). Base thicknesses for HBTs are typically 60-80 nm in dimension for 75- 100 GHz operation (Low et al., 1998; Bayraktaroglu, 1993). Fabrication of compound semiconductor ICs integrates materials science, materials characterization and semiconductor process engineering. An implicit precept for the materials growth and device fabrication is that these processes must be manufacturable: controlled, reproducible, and supported by realistic fabrication and operating tolerances, especially for fine critical dimension geometries. In this sense, a process sequence for compound semiconductors should appear silicon-like. That is, carried out within Class 1 or Class 10 cleanroom facilities, it should have a well-defined, relatively planar process morphology supported by batch processing with automated equipment, and use automated step-and-repeat lithography for pattern generation. However, the utilization of “pure” silicon processing tools versus tools configured for compound semiconductor processing must be balanced against the material’s properties of GaAs, such as the cleavage properties, the piezoelectric nature of the compound semiconductor lattice, strongly differing thermal and electrical characteristics in the native state, vapor pressures, wafer mass, density, etc. During the late 1990s, GaAs substrates have grown to 150 pm (6 in.) in diameter, while InP can be routinely obtained with

494

10 Compound Semiconductor Device Processing

75 pm diameter. The availability of large substrates has had a profound effect on the economics of GaAs device processing. reducing the cost of GaAs devices to roughly half that of silicon-based processes for equivalent functionality (Tomasetta, 1998). In contrast to silicon, gold and gold-based alloys are used in most of the present interconnect metallization schemes, and have been found to be suitable for circuit complexities in excess of 100000 gates. Some aluminum-based interconnection schemes (Vitesse, 1990, 1995) have been developed for high-density interconnection in digital applications, using alloy species such as copper to mitigate electromigration. However, for the preponderance of applications, NiGeAu compositions are used for ohmic contacts, and some form of gold-based metallurgy is used in gate structures to achieve low-resistance metal lines. The applications of multi-layer metallizations are growing rapidly: four-layer metal structures are readily available from “foundries” such as TriQuint and Vitesse. The successful process line must also be supported by statistical process control (SPC) and failure-mode analysis (FMA) methodology to ensure and maintain high quality and high yields from the process. The principal issues i n processing are: 1 ) the selection of materials and design criteria to achieve a desired set of device characteristics and performance. and 2) the definition and control of the requisite processing steps. The starting materials can be created with ion implantation doping, by epitaxial crystal growth, or by a combination of these methods. A typical process sequence will involve doping (by diffusion, incorporation during epitaxial growth, or ion implantation), photoresist patterning, isolation. annealing, etching. various metallizations, dielectric depositions and die or wafer level testing. and chip handling, as

well as multiple passes through several of these steps. All of the process sequences must be successfully carried out at high yields to fabricate functional, cost-competitive devices. The workhorse of the compound semiconductor device fabrication activity has been the metal - semiconductor field effect transistor (MESFET), and related variants. These devices are relatively simple to fabricate, but necessitate extremely tight control of the gate formation process (particularly the surface preparation or the gate recess etching step) to achieve control over the device threshold voltage and uniformity. Very fine (submicrometer) gate dimensions are needed to realize high-frequency operating characteristics (e.g., > 10-20 GHz ft values) i n MESFET devices. Since the early 1980s the heterostructure field effect transistor [HFET, HEMT, MODFET, HIGFET, etc., see Daembkes (1991)l has received extraordinary attention as a result of the higher frequency performance, better transfer characteristics, and relatively relaxed lithography requirements with respect to MESFETs, in order to realize a similar performance level. The base materials for these devices are created by molecular beam epitaxy (MBE) or by metal-organic chemical vapor deposition (MOCVD) methods. In HFET devices, the transfer characteristics are determined to a large extent by the multi-layered compound semiconductor heterostructure and the materials growth process. However, the fabrication process must be well characterized and controlled, as threshold voltages vary by 5 - 15 mV per atomic layer, similar to those of MESFET device,. Thus even small errors in surface preparation, random material loss during photolithography steps, damage induced by ion implantation, or dry etching may result in large variations in device characteristics. The HFET device family, its his-

10.1 Introduction

tory, and performance characteristics are reviewed in depth by Daembkes (1991). In the last few years, there has been a gradual conversion from the HFET to the pseudomorphic HEMT, incorporating InGaAs layers to form the conducting channel, so displacing the GaAs channel structures (see Brech, et al., 1997 for example). These devices have substantially improved transfer characteristics relative to the GaAs channel devices, and thereby offer superior electrical performance without incurring any additional processing complexity. Heterostructure bipolar transistors (HBTs) are now receiving some attention as HFETs enter production. The HBT devices are fabricated on epitaxial materials, and are nearly totally dependent on the crystal growth process for their characteristics. Recently, there has been a shift in the starting material’s structure, similar to that noted in the HEMT devices. In the case of the HBT, the structures were previously based on GaAs-AlGaAs hetero-barriers at the emitter-base junction (Ali et al., 1991). Presently, the trend is moving towards InGaPGaAs structures (Mochizuki et al., 1997; Lin et al. 1990; Ho et al., 1993; Ren et al., 1993), as devices fabricated with this materials system have shown phenomenally good reliability (Low et al., 1998; Pan et al., 1998). The HBT device characteristics were reviewed by Ali et al. (1991). The processing of HBTs is relatively straightforward, but requires a very high degree of process control, particularly over the base and collector etching and metallization steps. Dry etching of phosphorus-containing compounds is not compatible with all of the materials chemistries, so wet etching steps are required. However, the etching selectivity for some of these materials is in excess of thousands to 1, thus alleviating much of the concern for the wet etch processes (Ren et al., 1995). The transfer characteristics are

495

very sensitive to the distribution of the p- or n-type impurities in the collector-base (C-B) or emitter-base (E-B) junction regions, that is, the alignment of the metallurgical and electrical junctions. The materials quality and properties in the various layers are also crucial to the high frequency characteristics. It is notable that one major stumbling block in HBT devices has been the issue of reliability. This issue has been discussed at length at several venues (see GaAs IC, 1992, 1993a, b, 1994, 1998) without clear conclusion. The principal problem with these devices is that in the presence of high currents or elevated temperatures (Le., stressful operating conditions), the dopant species may redistribute near the junctions, thereby altering the device characteristics. Commonly this is observed as a degradation of the device gain, and many groups have reported this behavior. This issue remains under intense debate and investigation (Yamada et al., 1994; Sugahara et al., 1993). However, very recent results in the InGaP-GaAs based materials have shown reliability to be extremely high (Low et al., 1998; Pan et al., 1998), approaching lo8 hours at 150°C (Ueda et al., 1997). In the search for high-speed operation at extremely low power levels, a number of complementary devices have been fabricated. NPN and PNP devices such as junction field effect transistors (JFET) (Zuleeg et al., 1984, 1990; Wilson et al., 1989; Wada et al., 1989), and complementary heterostructure FETs (C-HIGFET) (Grider et al., 1991). The C-HIGFET circuit performance has been dramatically improved in recent years (Abrokwah et al., 1993), providing an ultra-low power GaAs-based circuit with much higher performance than similar silicon CMOS devices. More recently, HBTs (Ali et al., 1991; Slater et al., 1990; Kim et al., 1988), have yielded ultra-high performance devices and circuits. Enhancement-

496

10 Compound Semiconductor Device Processing

depletion structures have also been developed for logic and mixed signal applications (Dautremont-Smith et al.. 1990: Burton et al., 1983: Wada et al.. 1997). Implicit in this discussion is the need to maintain very high yields through each step of the process sequence. As an example, consider a processing sequence for the fabrication of a GaAs device or integrated circuit (IC). as illustrated in Fig. 10-1. This

process sequence would produce a transistor or an IC with 2 , 3 , or more levels of interconnect, and resistors, capacitors, and inductors. Figure 10- 1 also incorporates the steps needed for the fabrication of an HBT device, which entails a modified process sequence. Once the collector is defined and the emitter, base, and collector metallizations are complete, the subsequent processing steps are common to all fabrication flows.

Emitter Etch

I I

Epitaxial Material /

(ePi@V'

I I J

Base Etch

Dielectric Deposition

P-5-

Ohmic Contact

Collector Etch

t t

Dielectric Deposition

Ohmic Contact

t Gate Metal Etch

Dielectric Deposition

First Level Interconnect

Dielectric Deposition

ril Isolation I

Figure 10-1. Schematic representation of a process flow for the fabrication of an FET or integrated circuit. Various steps may he incorporated or bypassed as appropriate. The process sequence will vary depending on the individual process flows. the device requirements. and the requisite thermal budget. Since the processing for a HBT device is markedly different from that f o r an FET. the HBT process sequence is described by the flow on the right side o f the figure. At the "A". the process flows merge to define the interconnect strategy, thinning, and hack-surface metallurgy as required for the finished product.

10.1 Introduction

A “mask level” in this discussion incorporates numerous steps: cleaning, photoresist application, baking, exposing, developing, measurements, inspection, cleaning, a “layer” formation such as ion implantation, metallization, or dielectric deposition, additional inspection or measurements, and then returning to a cleaning step prior to a new mask level. The yields through each of these individual process sequence steps must be - 99% to realize just a 90% yield through a single mask level! If a 10 mask-level process were operating with a 90% yield at each mask level, only a 38% gross yield would be realized before the on-wafer electrical functionality evaluation. It is to the great credit of the wafer processing staff that very

high levels of process integrity and yield can be achieved and maintained. In addition to the plethora of process and materials related phenomena, such wellknown electrical phenomena as sidegating and backgating (discussed in Sec. 10.3.3) must be understood and controlled with respect to their impact on circuit performance (D’Avanzo, 1982; Makram-Ebeidand Tuck, 1982a, Vuong et al., 1990; Finchem et al., 1988). These inter-device interactions can have a strongly destabilizing influence on device performance. While these latter problems are coming closer to mitigation (Smith et al., 1988a; Brown et al., 1989), complete elimination of the interaction between devices fabricated in compound semiconduc-

Dielectric Deposition Multilevel Metal Interconnect Metallization

Scribe and Lands Air Bridge Metal Lines

Figure 10-1. (continued).

497

DC, RF or High Speed Testing

498

10 Compound Semiconductor Device Processing

tors has not yet been achieved. For example, DC sidegating performance has been observed to be extremely good in some cases (Smith et al., 1988b), but high-frequency performance may suffer from the vagaries of sidegating phenomena (Lin et al., 1990; Gray et al., 1990; Hitchens et al., 1989).In discrete devices, deep levels do not cause interactions, but rather give rise to dispersive effects and other time dependent behaviors. This chapter will deal with some of the general problems which have been faced and overcome in the processing of compound semiconductor materials for high speed device fabrication. It is not, nor can it be, exhaustive, as the topic is too vast. However, it will precent a wide range of materials, device, and process issues illustrating the key concepts, features, and problems in the present state of the technology. Other chapters are devoted to detailed development of materials growth, device structures, and related characteristics. and will be referenced where necessary. The first sections will describe some of the issues involved in creating the desired electrical characteristics on or in the compound semiconductor substrate, and then the fabrication process steps and process sequences will be discussed. The generic process sequence described here could ultimately result in the fabrication of either an active or a passive device. However, it should be emphasized that this description does not represent any specific process flow, as such detailed information is considered highly proprietary.

10.2 Doping Processes GaAs and InP are the dominant materials

in the compound semiconductor device arena, although research and small scale production activities span the gamut of III-

V and II-VI binary, ternary, and quaternary systems. This focus arises from the respective electronic and optical properties, and the demands of the market place. Electronic applications are present dominated by GaAs-based materials, especially for power amplification and high frequency (RF) devices in the range of - l GHz to -75 GHz. For higher frequency requirements, InPbased HEMT devices can be used up to - 100 GHz. In both cases, very small gate lengths are required, with electron-beam definition needed to produce the fine features. Electro-optic devices are predominantly built from InP-based ternary and quaternary materials, with some GaAs-based device applications as well. In any of these applications, n-type, p-type, or mixed conductivity layers must be created to form the active device. The modified semiconductor conductivity allows for metal-semiconductor (Schottky barrier), p- n, p- i- n, or other forms ofjunction to be formed. The advantages of compound semiconductors over silicon lie predominantly in the large bandgaps and higher carrier mobilities. In general, these properties permit operation at higher temperatures and higher frequencies. An additional feature of compound semiconductors is the ability to “engineer the bandgap” (Capasso, 1987, 1990) through composition variation (i.e., the mixing of group I11 and V, or I1 and VI elements), Le., binary, ternary, quaternary, or more complex compounds may be created. The group III-V (and the group II-VI) compound semiconductor elements may be mixed on either sublattice to tailor the bandgap and the optical and electronic properties. While there are some limitations imposed by thermodynamic and materials physics considerations, the electronic and optical properties may be readily optimized to the application, which makes the use of these materials so attractive for high-speed

10.2 Doping Processes

electronic and optoelectronic devices. The relationships of bandgap energy, direct/indirect band transitions, lattice parameter, and chemical mixing are shown in Fig. 10-2. Diagrams such as this have provided the basis for understanding the entire 111-V compound semiconductor alloy system. To fabricate an active or passive device in a compound semiconductor material, conducting regions or layers must be created. These regions may be n- or p-type in character, but for most compound semiconductor device fabrication n-type (majority carrier) conductivity is utilized. This is due to the significantly reduced high-frequency performance of devices based upon hole transport (low carrier mobilities). As examples, the maximum drift mobility for electrons in n-type GaAs at room tem-

499

perature is in the range of 8000-8800 cm2 V-' s-', versus 1200-1500 cm2 V-' s-' for n-type silicon (Sze, 198 1, App. G, H; EMIS, 1990, Chap. 5). The maximum drift mobility for holes is 400-450 cm2 V-' s-' in GaAs, while being somewhat higher in Si at 450-500 cm2 V-' s-'. For InP these values are 4800 cm2 V-' s-' for electrons and 150 cm2 V-' s-l for holes, respectively (EMIS, 1991, Chaps. 2, 4, 5). The high carrier mobilities in compound semiconductors arise from the polar nature of the lattice, and the concomitant differences in the band structure and the Fermi surface (Sze, 198 1, Chap. 1; EMIS, 1990, Chap. 7). It is the electron transport characteristics and the existence of a direct band gap that provide the large performance advantages over silicon devices. The direct band gap refers to the energy tran-

3.0

2.5

2.0

1.5

1.o

0.5

0.0

5.2

5.6

6.0

6.4

6.8

Lattice Constant (A) Figure 10-2. The 111-V compound semiconductor multi-nary tree. Tie lines link the binary compounds along ternary compositions. Dark solid lines indicate a direct band gap transition, while a light line indicates an indirect band gap. Silicon-germanium is included for reference. The x-axis is the lattice parameter; the y-axis is the bandgap energy in electron volts. The inset (upper right) shows the nitride materials, silicon carbide, and diamond relationships relative to the 111-V materials, (Figure courtesy of Dr. J. Woodall and E. S. Harmon, MellWood Laboratories, Inc., West Lafayette, IN.)

500

10 Compound Semiconductor Device Processing

sition when the valence band maxima coincide with the conduction band minimum at k = 0. This point is discussed by Sze ( 198 1. Chap. 1). Table 10-1 presents some of the critical physical properties of compound semiconductor materials. To create n-type behavior in compound semiconductors impurity species such as Si. Sn. Te, Se and S are suitable canditates. Acceptor impurities include Be, C. Zn, Cd, and Mn. Other transition metal species such as Cr. Ni, and Fe tend to produce midgap deep level states and high resistivity ("semi-insulating") characteristics. Figure 10-3 presents a summary of the energy levels for a number of impurity species in GaAs. Owing to

the differences in band structure and atomic configuration between the various compound semiconductors, group IV impurity species such as carbon or silicon may act as acceptors or donors in different 111-V alloys. The various dopant species may be introduced into a substrate or into epitaxial layers by the techniques of ion implantation or diffusion, or they can be grown-in during epitaxial layer growth. In the 111- V materials, the group VI impurities generally yield higher electron densities than do the group IV species at same dose and energy (ion-implanted case) or the same atomic concentrations (epitaxial growth), due to autocompensation effects

Table 10-1. Selected properties of semiconductor materials at room temperature

Melting point i " C ) Lattice constant (nm) Density (g cm-') Thermal conductivity ( W cm-' K-') Thermal expansion coefficient ( x IO-' K - ' ) Heat capacity ( J mol-' K-') Band gap (eV) Electron mobility ( c m V ' s ) Hole mobility (cm' V-' s - ' )

Si *

GaAs"

1415 0.543 1 2.328 I .s 2.6 19.6 1.12 I so0 450

I238 OS653 5.32 0.46 6.86 50.7 1.424 8500 400

I065 0.5869 4.79 -0.7 4.56 45.3 I .34 4800 150

Sze (1981): EMIS (1991).

Figure 10-3. Measured ionization energies for impurity atoms in GaAs. "D" and "A" denote donor or acceptor beha\ior. respectively. Otherwise. levels above the "gap center" are donor-like, and those below the gap center are acceptor-like stateb. [Original figure from S L i~1 % I ) . Reprinted by permission of John Wiley & Sons, Inc.]

10.2 Doping Processes

with the group IV species (amphoteric site selection by the dopant atoms). Carbon, a group IV element, is typically an effective acceptor in GaAs (as CAS)with relatively low autocompensation. In InP, carbon also acts mainly as an acceptor, although less readily incorporated. This behavior is advantageous for doping GaAs- or InP-based materials during epitaxial crystal growth by MOCVD or CBE methods. On the other hand, silicon (group IV) may exhibit strong autocompensation in GaAs and can produce dramatic reductions in desired electrical properties, particularly at high concentrations. The selection of ion implantation, diffusion, or epitaxial growth to create the conducting layers depends upon the requisite device’s electrical characteristics and the available fabrication process sequences. Diffusion-based methods for creating junctions have not been strongly pursued for compound materials in recent years, although several important applications exist in GaAs processing (Vogelsang et al., 1988; Wada et al., 1989; Harrington et al., 1988; Yuan et al., 1983). Control of the diffusedlayer depth and profile tends to be much more difficult than in ion-implanted or epitaxy-based processes, and therefore, interest in diffusion-based processes has waned. Ion implantation has been the choice of many process foundries for a broad range of applications (Rode et al., 1982; Shen et al., 1987; TriQuint, 1986; Vitesse, 1991). This is principally a result of the silicon-like nature of the process sequences, and the relatively low cost of device fabrication. Epitaxial layers, while somewhat more expensive than ion implanted substrates, have unleashed the power of compound semiconductors with the development of heterostructure device materials, and the near atomic level precision of doping and compositional variations. Due to the numer-

501

ous advantages of heterostructures (Daembkes, 1991; Ali and Gupta, 1991), these materials are rapidly displacing MESFET (metal-semiconductor field effect transistors) based on ion-implanted or epitaxial processes, especially for high-frequency and optoelectronic applications (Bayraktaroglu, 1993; Wada et al., 1997). Most of the n-type impurities are relatively stable in the compound semiconductor lattice. However, the diffusivities may vary strongly depending on the bandgap (binding energies), defect structure, concentration, and strain in the lattice structure. For example, the diffusivity of silicon in Al,,,Ga,,,As is roughly 10 times greater than that of silicon in GaAs (Schubert, 1990; Schubert et al., 1990). P-type impurities, such as Zn or Be, tend to be very rapid diffusers, and exhibit the combined effects of interstitial and substitutional diffusion. This behavior manifests itself as a “double diffusion front”, with interstitial species rapidly in-diffusing relative to the substitutional atoms (Tuck, 1988, Chap. 4; Gosele and Moorhead, 1981; Dobkin and Gibbons, 1984; van Ommen, 1983). Many of the ptype impurities (e.g., Mn, Zn, or Be) exhibit very large and anomalous diffusivities in compound semiconductor lattices (Jordan, 1982; Klein et al., 1980; Tuck, 1988, Chap. 5 ; Small et al., 1982). Control of the thermal budget (integrated time- temperature cycle) when annealing thus tends to be much more critical when dealing with acceptor species rather than donors. An example of the double diffusion behavior for Zn in GaAs is illustrated in Fig. 10-4. This phenomenon can give rise to an uncontrolled p-n junction position owing to the large difference between the diffusion rates of n-types and p-type impurities. Thus the final charge distribution is strongly dependent on the processing time- temperature sequences. Carbon atoms have been

502

10 Compound Semiconductor Device Processing ISWONCENTRATION LEVEL

45 min

8 V

D=6.78x10~a(S) - cm2s-1 1.2x1020

I IIT

I I

100

200

DEPTH (pml

Figure 10-4. Zinc diffusion behavior in GaAs. Isoconcentration (infinite source) diffusion has an erfc (complementary error function) profile. Concentration gradient diffusion reveals a concentration dependence of the diffusion constant and reflects the substitutional and interstitial diffusion behavior across regions I. 11, and 111. [After Gosele and Moorhead (1981). reprinted with permission of the authors.]

found to be very stable to thermal treatments in most compound semiconductors (Schubert, 1990). As a result, carbon is rapidly becoming the acceptor of choice for p-type doping for numerous applications. However, in some compound semiconductor materials, such as InGaAlP, carbon is not always an effective dopant species, and Be, Mg, or Zn remain the dopants of choice. Another difficulty encountered with impurities such as chromium or magnesium is the propensity for out-diffusing and accumulating on the surface or at interfaces i n the semiconductor material (Small et ai.. 1982; Tuck, 1988, Chap. 5 ) . This accumulation strongly alters the electronic properties in the surface region, and can lead to substantial inhom*ogeneities in the charge (resistivity) profile. It is this characteristic which led the industry away from the use of Cr-doped, semi-insulating GaAs substrates

to the “undoped” (native defect controlled) semi-insulating properties in the early 1980s. Rapid thermal annealing (RTA) or other short-duration, low-temperature processes may be used to minimize an undesirable impurity redistribution. Even for the donor impurities, with somewhat smaller diffusivities, it is generally desirable to minimize any atomic-level redistribution to maintain a “sharp” or “as-grown” impurity profile, or to prevent the movement of impurities into undesired regions of a device. For example, to maintain the gain of an HBT it is imperative to minimize diffusion between the collector-base and the emitter-base junction regions (Kim et al., 1991). In the case of an HEMT-type structure, the high mobility properties achieved by separating the donor species from the electron population are easily compromised if the donor atoms diffuse into the channel region. In the processing of epitaxial structures, thermal annealing may only be required for ohmic contact formation and device isolation (temperatures less than 500°C), and thus little impurity redistribution occurs. However, in self-aligned processes [SAGFET - Mitsubishi (Noda et al., 1988), SARGIC - AT & T (Dautremont-Smith et al., 1990), SAINT - NTT (Yamasaki et al., 1988), and similar processes), or when implementing the lightly doped drain (LDD), ion implantation is necessary to reduce the channel resistance and to alter the impurity concentration in the source-gate and/or gate-drain regions. Herein, the redistribution effects during annealing are critical for the device characteristics and performance: lateral carrier spreading can alter the effective gate length; excess charge or image may create leakage paths of short circuits. It is critical that a minimal thermal cycle is utilized and that the implications of the charge distributions on the device implications of

10.2 Doping Processes

the charge distributions on the device performance are well understood. Further information and a detailed treatment of various diffusion effects are provided in Secs. 10.4 and 10.8, and in Tuck (1988). One key issue in the use of ion implantation is the need for high-temperature annealing processes (see Sec. 10.8) to “activate” the implanted species, Le., to place the impurities onto substitutional sites in the host lattice and restore the lattice disorder produced by the ion flux. This thermal treatment must be carried out prior to metallization steps, or to utilize contact metals that are stable at temperatures greater than - 800-900°C. Diffusion doping processes also require relatively high temperatures with constraints similar to those in ion implantation-based processes. Epitaxial methods, on the other hand, have the impurity species incorporated during growth. However, the impurity distribution can be affected significantly by any process steps where temperatures exceed 400-600 “C. High-dose ion implantation or highly doped epitaxial layers are used to make highly conducting “n+” or “pf” layers and permit the formation of very low resistivity ohmic contacts. “Good” values for contact resistances are typically in the range of Q cm-2 for n-type materials, and lop5 R cmW2for p-type materials [Sharma (1981), and references therein]. Ion implantation can also be used to selectively dope regions within devices. For example, creating resistor stripes or enhancing device operating characteristics with “buried P” layers (Makinoet al., 1988; Noda et al., 1988), placing a p-type impurity below the n-type conducting channel to provide sharper pinch-off characteristics, or implementing the LDD (Kikaura et al., 1988) by selectively doping the gate-drain areas for improved gain linearity and breakdown properties.

503

The LDD process involves an additional donor concentration (n-type device), implanted selectively into the region between the drain and gate of an FET to reduce the drain-gate resistivity and create a graded electric field distribution. The LDD effectively decreases noise in HEMT devices, creates a lower source resistance, and mitigates short channel effects (Kikaura et al., 1988). In contrast to low-noise devices power FETs require highly doped source and drain regions to reduce the access and channel resistances, and reduce the heating problems associated with high operating currents. High-dose implants may be selectively added to increase the charge in these regions. In addition, all devices benefit from low contact resistances, which is a property well suited to selected area implantation. In other applications, such as low-noise amplifiers (LNA) or high-power, high-frequency power amplifiers (HPA), the critical issues are achieving a low source resistance, short, highly conductive gate structures, very high channel doping, and short (offset) gate-source spacing. For LNAs, a high concentration of charge must be localized very near to the surface of the semiconductor substrate in a selected area. Ion implantation is therefore carried out at very low energies (10-20 keV) to minimize the depth of the charge distribution. In power devices, the trade-offs become breakdown voltage, threshold voltage, ohmic-to-gate spacing, desired power, and maximum operating frequencies. Charge and distance must be carefully integrated to optimize the device performance. Epitaxial methods, which can precisely control the charge distribution in the surface regions, are now being applied to LNA and power device fabrication processes withgreat success (Ayaki et al., 1988; Danzilio et al. 1992; Pobanz et al., 1988; Tanaka et al., 1997; Goto et al., 1998; Takenaka et al., 1998).

504

10 Compound Semiconductor Device Processing

As the understanding of compound semiconductor processing has improved, many processes have evolved to epitaxial materials structures. This is due primarily to the ability to better specify the charge spatial distribution, and to the introduction of hom*o- and heterostructure devices and fabrication processes that utilize the precision of the epitaxial growth processes to reproduce semiconductor layer structures to within a few atomic distances (see, for example. Daembkes, 1991; Ali et al., 1991). New device designs such as pHEMT and HBT, and new materials options incorporating InCaP layers, have taken advantage of the precision charge distributions and hetero-barriers provided by epitaxial materials. These devices realize superior electrical characteristics and high-speed performance without resorting to extremely fine gate geometries. However, by further exploiting the ability to create fine geometries (- 0.1 pm) using deep ultraviolet light, or direct writing (e-beam or X-ray) methods for heterostructure FETs (HFETs) (Aust et al., 1989; Suzuki et al., 1989), or in HBT devices (where the critical dimension is the base

thickness, predetermined by the epitaxial growth process) (Kim et al., 1988; Low et al., 1998), switching speeds have exceeded 185 GHz (Nubling et al., 1989), and maximum oscillation frequencies (Fmax)are in the range of 500 GHz (Yu, 1998).

10.2.1 Ion Implantation Ion implantation doping is the process of injecting a desired impurity species into a semiconductor material by ionizing the impurity atom, accelerating it through a high potential (a few kV to greater than MV levels), selecting the correct ion species via a transverse magnetic or electric field, and collimating and guiding the ion flux as a "beam" onto the semiconductor substrate. Figure 10-5 shows an ion implanter in schematic form. The ions, upon colliding at the surface of the host material, expend their energy in collisions with the lattice atoms, and after some distance cease motion inside the host material. A small fraction of the ions may be reflected (recoil) from the surface and not contribute to the doping of the semiconductor. This effect is enhanced at low

4 Figure 10-5. Schematic representation of a high-voltage. high-current ion implanter. The main components of the \y\tem are denoted. (Figure courtesy of Dr. L. Parachanian-Allen, Ibis Technology Corporation, Danvers, MA.)

505

10.2 Doping Processes

ion energies or if the implanted species' mass is significantly less than that of the host material. The key issues in ion implantation are the control of the ion flux and purity, ion energy, and selection of the ion species (actually the m/q ratio, where m is the ion mass, and q is the charge state of the ion). This latter point requires that great care be taken to ensure that the selected m/q is predominantly the desired ion species, as many elements or complexes may have the requisite m a d c h a r g e ratio. Long beam lines, while adding additional complexities, permit filtering of the ion beam to enhance selection of the desired species. Extreme cleanliness in the implanter system and ultra-high purity source materials are prerequisites to successful ion-implantation processes. The depth of the ion penetration is proportional to the ion energy, the ion mass, and the host material average atomic weight. Typically, energies between 10 keV and 400 keV are utilized for implanting into compound semiconductors. Systems devel-

oping ion energies well above 1 MeV have been created for special applications. These energies will provide depths ranging from a few tens of nanometers to beyond a micrometer, depending on the ion species and the host material's properties, as shown in Table 10-2 (Gibbons et al., 1975). Ion doses range from - 10" ions cm-2 to greater than l O I 5 ions cm-2. Ion implanters are limited in their ion beam current (typically due to ion source limitations) and total power capabilities (beam current-accelerating voltage product). High dose implants require very extended times, which is hard on the ion sources and may cause the temperatures of the target wafer to rise substantially unless active cooling is provided. The latter point becomes more important as the dose-energy product increases. As the interactions with the lattice are statistical in nature, the impurities are distributed in essentially a Gaussian profile. The actual ion distribution is therefore described by the range, or peak concentration, R,, and the scatter, &$,, as shown in Fig. 10-6.

Table 10-2. Projected ion depths for 70 and 150 keV ion energiesasd. Ion

B H 0 N F Si Sc. Ge C P As

z I1 S a

Sib

GaAs

InP b , c

70 keV

1SO keV

70 keV

150 keV

70 keV

1SO keV

2 19160 7621 109 164156 158/47 187177 42/15 43/16 155139 86/34 84129 45/17 80132

420183 13911128 370198 344177 4601155 82/28 87/30 317160 188163 42/15 92/32 177160

177190 6391162 106158 122167 9415 2 59133 27113 28114 14417 6 5513 1 30115 52129

3821146 I2321205 2331100 26811 12 20719 1 129160 53/25 56/26 31 311 26 120157 60128 112153

1991101 7181182 119/65 137174 106158 66137 30115 31116 162185 -

4291164 13841230 261/112 3011126 2321102 145167 59128 63/29 352196 -

34/17 5 8133

6713 1 1261.59

,411 values in nanometers; data are presented as depthlstd. deviation; InP Values are scaled to GaAs results; Gibbons et al. (1975).

506

10 Compound Semiconductor Device Processing

Figure 10-6. Generalized ion-implantation profile in a target material, R , represents the peak of the concentration profile from the surface. ARp is the standard deviation of the profile. End-of-range damage region refers to a zone of high displacement damage due to ions stopping and transferring their residual energy to the lattice.

These parameters adequately represent the bulk of the implanted ions, but additionally there is a tailing of the ion distribution into a depth significantly deeper than R,, known as “straggle”. This phenomenon is not well represented by existing theoretical models (Biersack et al., 1980). For the ion implantation of donor species into most compound semiconductors, electron concentrations typically saturate i n the range of 3-8x 10” cm-3 after a furnace anneal. Under rapid thermal annealing (RTA) conditions the maximum electron concentration can be raised to greater than l O I 9 cmP3 (Liu et al., 1980). For high doses i t has been observed that the activation efficiency increases when ion implantation is carried out at slightly elevated temperatures (Donelly, I98 1, or with a “co-implanted” species such as fluorine (Pearton et al.. 1990b). The former result was attributed to the in situ recovery of lattice displacements during the implantation cycle, while the latter effect is attributed to lattice recovery from the additional energy dissipated in the lattice. For ptype implants using Be, Cd. or Zn, hole con-

centrations saturate at about 5-8x 10l8 cm-3 due to solid solubility effects. However, using Zn ions, acceptor concentrations above 3 x l O I 9 cmP3 have been obtained (Kular et al., 1978). There are several advantages to the use of ion implantation: good control of the doping concentration and depth of the ion distribution peak; relatively good uniformity of the ion flux across the substrate (typically a few percent variation); directionality (relative to diffusion methods): and good waferto-wafer reproducibility in modern ion implanters. In addition, the ions may be selectively implanted or shadow-masked by using appropriate masking techniques. The ion energy is determined by the accelerating field and therefore easily quantified. The ion flux is readily measured as a “beam current” in the implanter apparatus. By integrating the current with time the total dose may be calculated and controlled (the assumption here is that the ion beam is composed predominantly of the desired ion species). Corrections can be applied for low energy implantation processes to account for

10.2 Doping Processes

recoil losses. Ion ranging statistics are supported by a wealth of experimental and theoretical model information (Gibbons et al., 1975; Biersack et al., 1980; Zeigler et al., 1985), which has made the ion implantation process relatively straightforward to implement and control. The disadvantages to the ion implantation process are: substantially less than 100% efficiency in the activation process (ion species and host dependent); sensitivity of the activation to temperature; damage induced in the host material (defect introduction and electrical compensation); straggle and endof-range damage (deep random scattering and displacement events), as well as consideration of site selection and autocompensation. There is also a need to misorient the substrate with respect to the ion beam to avoid “channeling” which can, in turn, create shadowing effects at steps and edges of masked regions (Morgan, 1973; Kikaura et al., 1988). Some of these issues are addressed below. The efficiency of the activation process during annealing directly impacts the device characteristics, and is therefore used as a figure-of-merit for the implantation process. This figure-of-merit can be calculated from the ratio of the yielded charge in the lattice relative to the total measured ion dose. The effectiveness of the anneal cycle is affected by the amount of damage that is created by the ion flux, the site selection of the ion species (autocompensation), the annealing conditions (time and temperature), and the electrical compensation from the residual or native defects (see Sec. 10.8). Changes in the point defect concentration from the loss of volatile host atoms (e.g., As or P) may also alter the activation process. Defects arise from the displacement of atoms in the host lattice and the site selection of the implanted species. The defect family created by implantation consists of vacan-

507

cies, displacements, interstitials, complexes, substitutional atoms, antistructure, etc. Each of these defects carries a unique signature and provides electrical charge, compensation, and/or recombination tenters in the lattice. At excessive doses there may be so many defects created that the lattice is nearly completely disarrayed or amorphized (Howes and Morgan, 1985, Chap. 5 ) . This phenomenon will occur at fluxes in excess of 1 0 ~ ~ - 1cm-* 0 ~ ~for heavy ions in most compound semiconductors; significantly larger flux densities are needed to amorphize when using light ions such as protons (Anderson and Park, 1978). It has been found that by implanting at ternperatures above 150°C- 200 “C, GaAs cannot be amorphized even at high doses, as the minor atomic displacements anneal during the implantation cycle (Anderson and Park, 1978). Straggle and channeling are the “random components” of the implantation process. These phenomena arise from the random redirection of the ions due to scattering events in the host material. The effects are observed as lateral or azimuthal spreading of the ions in the host. Straggle refers to ions that come to rest far beyond the predicted positions in the lattice. End-of-range (EOR) damage may arise when these ions transfer their energy to the lattice upon stopping deep in the crystal. Channeling is another component of straggle, observed as a non-Gaussian depth distribution (“tailing”), as illustrated in Fig. 10-6. Channeling occurs when the ions are scattered down the “open” directions (e.g., (1 11) in a compound semiconductor) in the host lattice, and travel significantly further into the surface than predicted by the theory (Gibbons et al., 1975; Morgan, 1973). This phenomenon is prevalent in open lattices such as GaAs, InP, and other 111-V materials with large lattice constants. Channeling behavior and electrical effects are discussed

508

10 Compound Semiconductor Device Processing

i n Kikaura et al. (1988), and Myers et al. ( 1979) for example. Ion channeling and straggle may negatively affect the device’s performance. This effect is easily seen in Fig.10-7, where excessive sub-threshold leakage currents and a soft turn-on characteristic are evident. Interdevice interactions, such as sidegating. may also result from straggle due to the inability to adequately isolate adjacent devices. These manifestations are all related to the extended charge distribution in the depth of the channel below the gate. To ameliorate channeling the substrates are intentionally misaligned by 7- 13 degrees to the ion beam axis, and rotated about the normal to the wafer surface (Rosenblatt et al., 1988). In this manner the substrate presents a maximum apparent atomic density (amorphous-like) to the ion beam, which increases the likelihood of scattering events relative to the channeling probability (Morgan,

500

1973). Rotating the substrate continuously during ion implantation may also be used to optimize the ion distribution. However, there is no known method for totally eliminating these effects. To counter the effects of straggle and channeling of donor impurities in FET-type devices, a p-type “back-doping” or buried P implant may be added, deeper than the n-type implant, to sharpen the charge distribution at the bottom of the channel (Fig. 10-8). This step enhances the electron confinement and provides sharper I- Vcharacteristics at the expense of additional capacitance in the device. Great care must be taken to precisely position the p-dopant distribution and concentration to avoid compromising the device performance. Parasitic effects, isolation, and additional sidegating and backgating problems may arise from the presence of a p-type conducting layer (see Sec. 10.3.3).

-1

400

300

200

100

0 -4

-3

-2

Vgs(v0lts) Figure 10-7. I,,,- V,, transfer characteristics for an ion-implanted, and various epitaxial (MESFET and heterostructure) FETs. Note the lower on-resistance for the epitaxial-based structures relative to the ion-implanted case. The different device types are identified in the figure. The sharp turn-on characteristic and minimal sub-threshold leakage currents of the HEMT (high electron mobility transistor) devices are evident. Softer turn-on and higher sub-thresholds currents are characteristic of the ion-implanted and MESFET devices. (Figure courtesy of Dr. S. Wemple, Wemple Technologies, Wyomissing, PA.)

10.2 Doping Processes

509

Figure 10.8. Representative ion-implantation profiles in an n+-n-buried-p device structure. R,, AR,, EOR, and channeled ion have the their usual meanings. The buried-p implant is placed to compensate the tail of the n-channe1 region implant, while being (ideally) fully depleted by the donor species. This buried-p layer creates a sharper substrate-side effective charge profile leading to a sharper I-V turn-on characteristic, and lower leakage currents in the transistor

Implanting with a skewed alignment to the ion beam, while improving the ion distribution, can create other difficulties. If implantation is carried out after metal lines are defined, or with masking or dielectric layers present, as needed for device, LDD, buried-p, or isolation formation, self-alignment of the gate, etc. (e.g., gate metallizations, ohmic contacts), layers effectively screen the ion flux and shadow the areas adjacent to the metal runners as shown in Fig. 10-9. Shadowing can lead to nonsymmetric ion distributions, to nonuniform electric fields in the channel region, and create unexpected device asymmetries. To the designer, these effects may put significant constraints on the device layout (i.e., source and drain identity, or gate orientation) if predictable circuit characteristics are to be expected.

Several other issues are critical to the success of ion implantation processes. It is crucial to have “qualified”, controlled, semi-insulating (or conducting) substrate properties to achieve reproducible characteristics using ion implantation processes (Wilson et al., 1989, 1993). Prior to the mid 1980s, it was common to have Cr-doped or “Oxygen”-doped semi-insulating GaAs substrates (Makram-Ebeid and Tuck, 1982; Rees, 1980). In this time frame, the performance of ion implantation was strongly dependent on the raw materials, the crystal boule, the crystal grower, the crystal growth conditions, and even the position of the substrate in the boule. Chromium atoms rapidly out-diffuse from the bulk to the surface, rendering the active region partially compensated and highly resistive. This effect greatly complicates the use of high-temper-

510

10 Compound Semiconductor Device Processing

Figure 10-9. Schematic representation of the effects of topology on ion-implantation profiles. The angle between the incoming ions and the substrate (typically 7 " - 13" to the normal to the substrate surface, with a 45" rotation about the normal) is selected to minimize channeling. Ions are slowed near edges of photoresist features and may be deflected from metal trace corners, thereby perturbing the ion profiles in the host. The ion profile offset may be single-sided in systems with nonrotating and stations. while rotation of the substrate creates a more symmetric (two-sided)offset

ature annealing processes required for activating the impurities, and has the undesirable compensation effect on the implanted species. Thus chromium-doped materials are rarely used for device manufacture. In the case of InP. iron atoms are used to create the semi-insulating properties with very similar considerations. As crystal growth methods and materials' purities have improved, these early approaches have rapidly given way to high purity semi-insulating GaAs substrate materials (no intentional additions of impurity species) with well-controlled properties. The semi-insulating conditions arises from the presence of native deep-level defects [e.g., EL2 (the native defect level at 0.8 eV below the conduction band edge) and other deep levels. balanced with the concentrations of residual donor and acceptor species (Makram-Ebeid et al., 1982; Martin et al., 1977: Lagowskiet al., 1982;Milnes, 197311. InP crystals still require the addition of Fe to the crystal as there are no suitable native defects to produce undoped semi-insulating InP material (co*ckayne et al.. 1981; Parsey

et al., 1983). The present semi-insulating GaAs substrates are stable to extended thermal anneals at temperatures well above 900°C, and InP(Fe) substrates are stable at temperatures of 700"C-800"C. There are, however, sufficient variations in the substrate materials that many users still carry out "boule qualification" procedures to verify the performance of the material in their individual processes (Wilson et al., 1989). A boule qualification process will typically involve a representative implantation sequence followed by an annealing cycle, and then electrical measurements are carried out to test the implant activation efficiency and depth profiles. These qualification activities raise the expense associated with ion implantation processing, and may also affect design and processing conditions in order to compensate for the interaction of the substrate, ion implantation, and annealing processes. However, in the interests of maintaining high yields, such activity is presently use in some process facilities utilizing implantation techniques. Other highvolume GaAs foundries have achieved a

10.2 Doping Processes

consistency of substrate supply, process stability and designs which accommodate most variations, and rarely require such qualification efforts [see Smith (1994)l.

10.2.2 Diffusion Methods Diffusion processes can be categorized as “closed tube” or “open tube”. The closed tube process typically involves sealing the impurity materials and the substrates in a vessel, evacuating or filling the vessel with an inert gas, and then subjecting the entire assembly to an annealing cycle to in-diffuse the impurity. This method is cumbersome expensive, difficult to control and reproduce, and unsuitable for production environments. The open tube approach to diffusion has been refined over several decades of silicon wafer processing. In compound semiconductors, the analogous technology is applied, with considerations to the vapor pressures and toxicity of the group V species and their respective chemical derivatives. Herein, the substrates are patterned as required, loaded into a containment vessel or “boat” and placed within a high-temperature furnace usually surrounded by an inert gas flow. The entire system is thermally equilibrated, and the dopant gases are introduced into the furnace atmosphere. In deference to the high vapor pressure of the group V species, overpressures of arsine, phosphine, or similar gases, may be employed to prevent dissociation of the substrate material during the process cycle. Similar methods may be employed for 11-VI materials as well. These gases and the by-products of the dopant species (for example, silane, disilane, diethylzinc, dimethylmagnesium, carbon tetrachloride, etc.) are highly flammable or toxic, and must be handled in an environmentally safe manner. This requires extensive exhaust handling and safety equipment,

51 1

but does not impede the implementation and operation of these processes. The advantage of diffusion processes is that very shallow layers can be created in the surface region. These procedures are also supported by decades of experience from silicon processing, and thus are well established, “high-volume” manufacturing processes. Although the diffusivity of impurities in the compound semiconductors is relatively small at epitaxial growth temperatures, or at annealing or “drive-in” temperatures, diffusion can be significant particularly for most acceptor-type species (as noted above). The driving force is the impurity gradient, enhanced or retarded by strain, dislocations, and other sources of free energy. Defects can greately enhance the motion through the lattice by providing open sites for the impurities (Shewmon, 1973; Tuck, 1988). Therefore care must be taken in the diffusion doping process to ensure that the near-surface region is properly prepared and free of contaminants. Owing to the high vapor pressure of most of the groups V and VI elements, the surface may become nonstoichiometric during the process through the loss of arsenic or phosphorus, and create defects which enhance impurity migration. The overpressure of As, or P, is provided in the system to mitigate decomposition of the surface, as previously noted. Diffusion methods are principally used for p-type doping due to the rapid diffusivity of these species (Gosele and Moorhead, 1981; Wada et al., 1989; Tuck, 1988; Yuan et al., 1983); n-type impurities move relatively slowly. The diffusivities for various impurities in GaAs, InP, and other compound semiconductors are provided in Sze (1981, p. 68) and EMIS (1990, 1991). One other feature of most of the acceptor species mentioned above is their propensity for behaving as both an interstitial and a substitu-

51 2

10 Compound Semiconductor Device Processing

tional diffuser. This creates the double diffusion front shown in Fig. 10-10, due to the more rapid diffusion of interstitial species relative to substitutional behavior (Gosele and Moorhead, 1981; Tuck, 1988, Chap. 4). As a result the electrical depth of the junction is difficult to control in diffusion processing. Three significant drawbacks to the use of diffusion doping in compound semiconductors are: 1 ) the lack of a stable native passivating oxide, unlike SiO, on Si, 2) the melting points of the compounds are, in general, much lower than that of silicon, and 3 ) the vapor pressure of the groups 11, V, and VI species are very large at high temperatures which prevents, or complicates, processing above - 300"C-600"C. Since the compound materials do not have stable native oxides, a dielectric film

must be applied to protect the wafer from undesired in-diffusion and to maintain surface integrity. The dielectric films of choice are Si,N,, SiO,, and the mixed "oxy-nitride" films, SiN,O, . To selectively dope the substrate, this film must be patterned appropriately. Due to the lower melting points of the compound semiconductors relative to silicon, these materials are subject to the creation of defects at lower temperatures. This phenomenon can radically alter the indiffusion behavior and electrical activity (site selection). Coupled with the high vapor pressures of the groups 11, V, and VI species, the diffusion must be carried out at relatively low temperatures to ameliorate decomposition and defect formation. This compromise entails extending the diffusion time to achieve the necessary time-temperature product. The protective film may be

"Double Diffusion Front" Behavior

Log (Concentration)

Distance into Semiconductor

Figure 10-10.Schematic diagram of a double diffusion front impurity profile (cf. Fig. 10-4). The net impurity profile results from the sum of the interstitial and substitutional impurity distributions. The electrical activity depends on the activation of these two components and any autocompensation due to site occupancy of the impurities in the host.

10.2 Doping Processes

removed after the diffusion step to prevent further contamination or allow patterning in subsequent processes. Owing to the difficulties in carrying out diffusion-type processes, these methods have been supplanted by ion implantation and epitaxy. Further discussion of diffusion processes is presented in Sec. 10.4.

10.2.3 Epitaxial Methods In the epitaxial growth processes metalorganic chemical vapor deposition (MOCVDI MOVPE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), and molecular beam epitaxy (MBE), or gas-sourcekhemical beam epitaxy (GSE or CBE), the dopant species are normally incorporated during the deposition of the epitaxial layers. Group IV, group I1 transition elements, and group VI impurity species (as noted previously) are added to the melt in LPE, the gas phase in MOCVD and VPE, or effused from a Knudsen-typ cell or gas injector (MBE, and CRE/GSB respectively). In GaAs-based materials, the groups IV and VI elements act as n-type (donor) species, with the exception of carbon which acts as an acceptor, and Ge which exhibits a high degree of amphoterism. The group I1 elements are acceptors MBE crystal growth methods are covered in detail by Parker (1985), and MOCVD is discussed by Stringfellow (1989). See Chaps. 2 and 3 of this Volume for an additional discussion of these crystal growth methods. The range of doping concentration depends strongly on the nature of the impurity species, the purity of the sources, the chemistry of the growth process, the growth velocity, and the growth temperature. These parameters generally determine the background carrier concentration, which sets the lower limits of intentional doping. The thermodynamics of the multi-component system (i.e., solid solubility, ionic interactions,

51 3

misfit strain, point defects, etc.) limits the maximum atom concentrations. In this sense, the epitaxial layers generally achieve somewhat lower carrier concentrations than those of ion implantation processes since the latter approach is not tied so closely to the thermodynamics of the process. Donor concentrations in epitaxially grown material typically range from less than 5x 1015 cm-3 to greater than 5 ~ 1 0 ~ ~ c m - ’ . Acceptor concentrations are nominally in the range 5 - l o x IO’’ cm-3 to greater than l O I 9 ~ m - For ~ . HBT devices hole concentrations of > lo2’ cmW3have been created with carbon doping, although the use of the term “impurity” might be better replaced by “alloy component” at these levels. It should be noted that this is a doping tour-de-force since the electrical and physical properties of the GaAs degrade markedly for concentrations of carbon above 5x 1019 cm-’ (Georgeet al., 1991).Theminimum concentrations are highly dependent on the growth apparatus as the background impurity concentrations and native defect structures in the epitaxial layers determine the minimum detectable change in the doping level. Recently, using gas-source epitaxial (GSMBE) methods, carbon concentrations above lo2’ cm-3 have been realized in GaAs (Abernathy et al., 1989), although the same caveats exist for high doping levels independent of the crystal growth method. Epitaxial growth processes provide significantly better control of the depth distribution of impurities than ion implantation, but, until recently, have had limited selected-area control capabilities. CBEIGSMBE methods are actively being explored for selected area growth (Tu, 1995; Shiralagi et al., 1996). The issues which limit the selected area growth are nucleation and growth phenomena and contamination in the patterned areas, as well as control of the growth rates on the various crystal planes exposed by the

51 4

10 Compound Semiconductor Device Processing

patterning. Recent advances in MOCVD have also shown some capability for controlled selective area growth (Linden, 1991 ) . As was shown in Fig. 10-7, the device transfer characteristics are significantly better for epitaxy-based devices than for ion implanted structures. This is due to the tightly controlled charge distribution in a heterostructure device. Sidegating and backgating are also better controlled in heterostructure devices, as the charge distribution is readily isolated by etching or ion implantation processes. This latter point is illustrated in Fig. 10-l l . Principally, the performance improvements come from the significant differences i n the charge distributions, the ability to isolate devices (interaction of the chemical species as well as damage), the creation of atomic displacement damage, and the interaction of the substrate and the charge distribution during device operation [see D’Avanzo (1982), Vuong et al. (1990)l. When doping compound semiconductors, many factors must be considered. The

O h

process of ion implantation is of relatively low cost compared to epitaxial layer growth. This cost saving is due to a high wafer throughput relative to all other methods of creating an active layer, which is a significant point for fabrication costs. Also, the uniformity and reproducibility are adequate for most applications, the trade-off coming in the ability to create the tightly-controlled charge distributions required for ultra-high performance devices. However, as high volumes of epitaxial materials are being consumed and manufacturers add epitaxy capabilities, the material prices are falling, so reducing the offset in the final manufactured costs. The performance of epitaxy-based devices is typically far superior to that realized in ion implanted devices for a given set of design rules and circuit configuration. The performance advantage and yield improvements offered by epitaxial materials easily offset the higher costs of processing epitaxial materials for a number of applications. Furthermore, epitaxy-based heterostructures such as HBT, HEMT, VCSEL,

Ids 200rm

100

a0 <\

Figure 10-11. Experimental results of sidegating effects in heterostructure FET devices.With optimized isolation at the device periphery, very large potential differences may be applied to adjacent devices with small interdevice spacing. The sidegating effect in devices that received a shallow isolation implant (dashed lines) relative to those devices that received an additional deep isolation implant (solid lines), within the same wafer. The y-axis is defined by 100 [ f ~ ~ ( V ~ , ) / f ~ ~ ( V ~ ~ = o ) l , the x-axis is the voltage applied to a side-gate contact at the distances noted in the figure. Sidegating effects are mitigated to a great degree with the deep isolation implant. [Figure from Vuong et al. ( 1 990).] 0 1990 IEEE.

10.3 Isolation Methods

and others cannot be fabricated by ion implantation or any other methods. Additionally, it has been argued recently that the cost of producing a GaAs die on 150 mm substrates is substantially less than the cost of producing BiCMOS (silicon) devices on 200 mm substrates (Tomasetta, 1998).

10.3 Isolation Methods Electrical isolation is required to prevent interaction between devices in an integrated circuit. The objective is to limit or eliminate interdevice current flows and electric field effects to levels below those which affect the device operation. Circuit parasitics may be reduced by proper application of isolation techniques so that higher performance may be realized. Capacitances, inductive coupling, and leakage currents can be mitigated by appropriate isolation practices. In addition, electrons and/or holes may be better confined within the transistor cell. The use of isolation leads to more reproducible electrical characteristics, better control of the charge distribution in active devices, and similar control over the electrical characteristics of passive components such as resistors, inductors, and capacitors. There are two principal approaches to isolating devices in a compound semiconductor integrated circuit: ion implantation and “mesa” or “trench” etching. Each

515

method has its own advantages and drawbacks. Mesa/ trench isolation was developed first, and involves removing material to create an island or moat around the device. This approach can create substantial topological relief, which may complicate further wafer processing steps. As substrate material quality and device fabrication processes have improved, ion implantation has become the method of choice for isolation. Implantation permits a desirable planar morphology and the creation of finer device geometries which are needed in order to fabricate high density circuits with high yields and reliability. However, effective isolation of very shallow, or highly doped, layers often proves difficult in practice due to the Gaussian distribution of the ion implantation process. Implanting through photoresist or other capping layers can circumvent this problem by placing the peak of the ion distribution in the near-surface region.

10.3.1 Mesa Etching Mesa or trench isolation is an effective method for isolating discrete devices and active regions in integrated circuits. The technique involves defining regions surrounding the active devices with a photoresist layer or other masking materials, and subsequently etching away the exposed material to form isolated islands or “mesas” in the surface (Fig. 10-12). The etching can be

Figure 10-12. An illustration of an n-channel FET isolated by an etched mesa process. The areas between adjacent devices may be ion-implanted or covered with a passivation layer to further enhance the isolation.

51 6

10 Compound Semiconductor Device Processing

carried out using “wet” or “dry” chemistry methods (see Sec. 10.5 and Chap. 6 of this Volume). Mesa etching generally relates to a large low aspect ratio structure, whereas trench isolation refers to a high aspect ratio structure. A key requirement of the mesa definition process is to produce a morphology that is compatible with any subsequent processing steps. Excessively deep trenches, reentrant edges, or sharply sloped side walls will impair the creation of fine features, and may give rise to poor or nonexistent coverage of subsequent metal layers or dielectrics. Smooth features and rounded or gentle tran-

sitions at step-edges are generally preferred. Some of the key features of mesa isolation are illustrated in Fig. 10-13. If the trenches or mesas are incorrectly formed, as shown in Fig. 10-13 a, metallization layers and dielectrics will not deposit properly, leading to device failures (e.g., short or open circuits, leakage paths). Mesa-type structures such as those illustrated in Fig. 10-13b are desirable. The anisotropy of compound semiconductor materials becomes evident in the morphology created by the interaction of the etchant and the crystal structure, as shown in Fig. 10- 14. Thus it is imperative to under-

Figure 10-13.Cross section of an FET hith mesa isolation. In ( a ) the mesa is undercut excessively. Dielectric coverage and integrity are compromised. In ( b ) the mesa edges are optimally formed and the dielectric coverage is uniform.

10.3 Isolation Methods

c1 oo>

51 7

<011>

Direction

Direction GaAs Substrate

cl oo>

<111> Direction

Direction

GaAs Substrate

stand and control the etching process to produce the desired mesa or trench configuration. Etching characteristics, substrate crystallographic properties, and device implications were discussed, for example, by Lee (1982). Etch stop technology, as implemented in epitaxial materials, can be used very effectively to assist in the formation of isolation structures. An effective etch stop layer can provide precise location of the mesa ledge or trench bottom resulting from arresting the etch process, and provide extremely robust processes, for example, greater than 10000 to 1 selectivity in the InGaP-GaAs system (Ren et al., 1995). The ability to force the etchant into very fine features, i.e., liquid surface tension or gas pressure/density effects, limits the minimum spacing between devices and features. Similarly, to remove the reaction products or to dilute the etchant and arrest the etching process is particularly difficult for high aspect ratio, or closely spaced, features. (Details of etching chemistries and

Figure 10-14. Anisotropy of GaAs as revealed by chemical etchants. The limiting crystal planes are of [ 11 1 ] type, with arsenic or gallium planes exposed. This results from the nature of the zincblende crystal structure.

processes are presented in Sec. 10.5) As a result, devices must be separated to accommodate these process limitations at the expense of valuable semiconductor area. Thus the packing density and the integration level of the circuit are generally more limited when mesa isolation is used as opposed to ion implantation processes. Redeposition of the host materials or masking materials may occur during the etching process, which may inhibit the formation of well-controlled mesa morphologies, creating curved or corrugated surfaces, nonuniform mesa definition, leakage paths, etc. These effects must be avoided to successfully isolate devices with mesa technology.

10.3.2 Ion Implantation Isolation With ion implantation, the object is to render the material semi-insulating or highly resistive by the formation of deep levels and recombination centers resulting from the ion bombardment. Use of this

51 8

10 Compound Semiconductor Device Processing

technique has the powerful advantage of maintaining surface planarity, which makes the definition of very fine features and multi-layer metallizations relatively straightforward. Thus better process integrity and greater complexity can be achieved with ion implantation as opposed to mesa etching methods. For successful isolation selection of the ion species. control of the ion flux, beam purity, and the ion energy are critical. The ion penetration depth is proportional to the ion energy, ion mass and host lattice atomic structure, molecular weights and composition. The concerns associated with ion implantation, as discussed in Sec. 10.2.1. are ion channeling, straggle, and tailing of the depth profile. However, for isolation processes it is usually desirable to extend the isolation as deeply into the substrate as possible, thus tailing may be a desirable feature

in this case, as shown in Fig. 10-15. The efficacy of the isolation is a function of the chemistry between the host and the implanted ions as well as the formation of defects. Some of the important ion implantation ranging data are summarized in Table 10-3 for a GaAs host crystal. Boron, hydrogen (protons), and oxygen are very effective species for ion implantation isolation. The isolation effect is created by the displacement of host-lattice atoms, the creation of a myriad of defect complexes, and the reactions of the host species with the implanted ions (e.g., A1-0 complexes in AlGaAs) (Donelly, 1981; Short and Pearton, 1988). Commonly used ions are oxygen, boron. and protons (H+) (Pearton et al., 1987; D’Avanzo, 1982). It is generally desirable to use heavier ions for the isolation implant, as greater atomic displacement occurs in the host. However, a significant com-

Figure 10-15. Ion implantation isolation schematic diagram. The peak of the ion range (R,) is the approximate position of maximum isolation. The displacement damage peak (maximum atomic displacement) will be some what shallower or deeper than R,. depending on the host and implanted species atomic numbers, the dose and the energy of the implantation. The approximate extent of the isolation is shown. Additional displacement occurs at the end-of-range. increasing the effective isolation depth.

519

10.3 Isolation Methods

Table 10-3. Ion-implantation ranging data for selected ion species in GaAs single crystal material Energy (keV)

20 50 100 1 so 200 300 380

Element

0.21810.099 0.480/0.144 0.86610.181 1.233/0.205 1.60710.275 2,42310,262 3.16 110.292

0.04410.034 0.12410.070 0.25510.1 15 0.38210.145 0.50410.170 0.73310.207 0.90510.229

0.03910.030 0.101/0.060 0.20810.098 0.31310.125 0.41 510.147 0.60610. 182 0.75110.203

0.03010.022 0.07510.045 0.1.5410.076 0.23310.100 0.31610.121 0,46210.152 0.56710.172

0.018/0.013 0.04210.025 0.08510.044 0.12910.061 0.17410.074 0.26310.100 0.33310.117 ~~

Gibbons et al. (1975); data are in micrometers; data are presented as depthlstandard deviation.

promise in the achievable depth arises for heavy ions at practical ion energies. Light ions, particularly protons, can be used for very deep isolation requirements if relatively high doses are required. The implanted ions may create a variety of atomic displacements in the crystal lattice. It is desirable to create defects which act as recombination centers to prevent or inhibit the transport of charge between devices. As mentioned in Sec. 10.2.1, these defects consist of atomic displacements, vacancies, interstitials, a variety of defect complexes, and antistructure (resulting from atomic site exchanges). Each defect alters the electrical characteristics of the host material, and in the aggregate serve to create the insulating regions between devices. At very high doses the lattice may be disordered to the point of amorphization. This can occur in GaAs at fluxes greater than l O I 5 cm-* for oxygen or boron; protons require much larger doses (greater than 10l6 ~ m - ~ “Softer” ). materials such as InP amorphize at slightly lower doses; hard materials like GaP or S i c require higher doses. Excessive damage can create a conductive region instead of insulating characteristics. In this case, extensive annealing may be required to recover the damage. It should be

noted that there are significant tradeoffs in the dose-energy relationships in the implantation process: simply increasing the dose or energy may actually enhance the interaction and leakage between devices, and also increase surface leakage due to excessive damage. The large density of states created with high dose implants may permit hopping conduction and tunneling processes for charge transport. A light dose implant may not create sufficient recombination centers to be effective; a low energy may create insufficient displacement damage or too shallow an isolation region (current flows underneath the isolation region). Each ion species has a unique “signature” in the isolation process. For example, B+ ions remove up to 200 electrons per ion when implanted into GaAs at 1 MeV (Davies et al., 1973). Oxygen ions, while less effective than B at removing electrons on a per-ion basis, have proven to be extremely effective at isolating GaAs and particularly AlAs or AlGaAs-containing structures (Favennec, 1976; Pearton et al., 1987; Short and Pearton, 1988; Ren et al., 1990). Oxygen produces a deep level in GaAs (Fig. 10-3, Sze, 1981, Chap. l), which captures electrons and may create a high resistivity characteristic with sufficient dose. In the Al-

520

10 Compound Semiconductor Device Processing

GaAs material A1-0 complexes are formed which are highly effective recombination centers (Pearton et al., 1987; Short and Pearton, 1988). Protons are the ion of choice for deep isolation schemes (D’Avanzo, 1982). Being of low mass, the proton may be injected deep into the lattice even at modest energies, e.g.. beyond 2 p m at an energy of 250 keV (Gibbons et al., 1975). It is interesting to note that the damage profiles do not generally coincide with the ion profiles due to the large mass differences between the host and most implanted species. This discrepancy is greater as the mass difference between the ion and the host atoms increases. Owing to the approximately Gaussian nature of the ion and damage distributions i n the lattice, multiple implant se-

quences are generally needed to achieve a relatively smooth, total ion damage profile into the depth. This is illustratedin Fig. 10-16. When properly placed within the host lattice, multiple implants create a quasi-uniform, high resistivity volume in the implanted region. The drawback with the use of multiple implants is that the surface damage can be extensive, particularly at high doses or high energies, as well as extending process times and increasing macroscopic surface defect densities. The surface damage can lead to surface leakage paths or nonstoichiometric surface regions. For example, surface resistivity has been observed to fall by more than three orders of magnitude when very high energy isolation implants are carried out in GaAs (Liu et al., 1980).

Figure 10-16. Multiple implant isolation profile. I n this case. ion implantation cycles are carried out at different energie5. The deeper implants are performed at higher energies. End-of-range damage increases the isolation effectiveness and helps to smooth the net damage profile. With a large ion flux some amorphization or damage of the surface region may occur. A mild thermal anneal may be required to recover the crystal structure and stabilize the displacement damage profile without recovering the isolation effects.

10.3 Isolation Methods

One very powerful advantage of ion implanted isolation is that selected areas with complex geometries can be readily formed by patterned masking. Use of the selected area ion implantation methods for active region and isolation region formation allows for optimizing layout compaction and device isolation in the integrated circuit. To withstand very high energy ion bombardment, very thick blocking layers must be deposited on the surface, which can limit fine feature definition. Suitable ion blocks are thick photoresist layers, or photoresists with combinations of dielectrics or thin metals. Photoresist layers of 2-4 ym in thickness are typically employed to block 0, B, or H implants at energies of 100 keV to - 800 keV. With lighter ions, such as protons, the displacement of lattice atoms is significantly less than that obtained with heavy ions. Therefore the recovery of lattice disorder may occur with lower driving forces. For example, the damage created by H' implantation in GaAs anneals out at temperatures above about 400 "C. Protons create only small lattice displacements, and hydrogen diffuses rapidly out of the host leaving few electrically active defects (Pearton et al., 1990), The behavior puts significant constraints on processing temperatures and the viability of proton isolation for all but the lowest thermal budget processes. For most isolation processes a minimal thermal anneal is desirable, typically below -500°C for relatively short times. This "gentle" anneal prevents complete relaxation of the lattice, but eliminates some of the marginally stable atomic displacements and potential leakage paths while maintaining the high resistivity of the isolated region. On the other hand, for ion implantation doping it is necessary to anneal at temperatures in the range of 750"C-9OO0C to permit site selection by the impurities (activation) and

521

to remove electrically compensating displacement damage. This raises a conflict between the processes required to form the active layers and the need for isolation. For example, isolating underneath ohmic contact pads is not possible with present ion accelerator technologies. It should be noted that as the implantation process involves charged species interactions and significant energy is transferred to the lattice, the possibility of radiation damage and heating of the lattice during bombardment exists. The energy impinging on the wafer is of the order of hundreds of watts per square centimeter in a high-current implanter. If the wafer temperature rises above - 150-200 "C, the effectiveness of the isolation process may be compromised as lattice displacements can anneal out during the implantation cycle. To minimize the self-heating, it is prudent to implant at the lowest practical beam current and ion energy, or control the substrate temperature during implantation. Electron bombardment can be used for isolation, but the damage created is subject to annealing out at very low temperatures. The annealing of electron-induced damage in GaAs has been observed to occur in two stages: 150-200°C and 200-300°C (Aukerman and Graft, 1967; Vook, 1964). This makes electron irradiation unsuitable for isolation as temperatures in wafer fabrication typically exceed these levels. Neutron damage is another method for isolating regions in compound semiconductors. The typical array of point defects and defect structures are produced by neutron irradiation. The damage induced by neutrons has been found to recover in two stages in a manner similar to electron-induced damage: at 200-300°C (minor displacements), and then recovers fully at 600-700°C (Lang, 1977). Thus the isolation created by neutron bombardment creates a stable isolation re-

522

10 Compound Semiconductor Device Processing

gion only if processing temperatures are maintained below - 500°C. Beam blocking materials are generally transition metal layers in order to obtain sufficient stopping power for the neutron flux. One additional variation of ion implanted isolation is the creation of an isolation “box” for devices. For example, in devices utilizing n-type implants, a p-type implantation can be placed beneath the tail of the donor distribution. This buried-p layer creates a p-n junction isolation condition. By carefully selecting the dose and energy, the ptype layer can be nearly fully depleted, leading to minimal capacitance, a sharp n-type charge profile, and mitigation of short channel effects (Finchem et al., 1988; Matsunage et al., 1989; Onodera and Kithahara, 1989; Sadleret al., 1989).Typically, the buried p-type implant is used only under the channel region. However, it may be connected to an external bias to enhance the back-plane isolation with a depleted p-n

junction. An additional isolation implant or mesa processing may be used to create the “walls” of the box, thereby completely isolating each device, as illustrated in Fig. 10-17.

10.3.3 Sidegating and Backgating Sidegating and backgating are terms describing the interaction between devices in an integrated circuit laterally and from the back-plane region, respectively. These phenomena have plagued GaAs-based devices for many years (Vuong et al., 1990; D’Avanzo, 1982; Smith et al., 1988a; Lin et al., 1990), and arise from the electric fields induced in the material when the circuits are biased. The effects are realized as a modulation of the transistor channel current or the current flow in channel-resistors (Gray et al.. 1990; D’Avanzo, 1982; Goto, 1988). The problems associated with sidegating and backgating are greatly influenced by the circuit layout, and, in particular, the spacing

Figure 10-17. A cross section schematic diagram of an FET isolated by ion implantation processing (or mesa etching). The device has a buried-p layer connected electrically to the low potential of the device. This addition serves to mitigate sidegating effects. The buried-p layer must be contacted through an additional p-type ion implantation adjacent to the nc contact implant (or diffusion). The gate is offset in the channel to reduce source resistance.

10.3 Isolation Methods

and differential voltages between nearby devices and the condition of the back-plane (biased or grounded). Additional phenomena in sidegating and backgating effects are the transient charging and discharging of deep states. Electric fields, such as those created in p-n junctions, implanted isolation regions, ohmic contacts, depletion regions (e.g., Schottky barriers), etc., all lead to exposure of the various deep level states (traps), relative to the Fermi level, which lie in the semiconductor energy gap as shown in Fig. 10-18 (see also Milnes, 1973, and Sze, 1981, Chap. 1). As the electric fields are altered first by biasing, then modulated during device operation, the deep traps charge and discharge as the bands bend. This leads to a secondary modulation of the charge transport in the devices, with response transients of sub-microseconds to minutes in duration, and strong temperature dependences.

Semiconductor Surface

523

Several competing processes may arise from these deep levels in or near active device regions: l ) charge domains may be launched from a source (anode) contact under moderately high electric field conditions, and 2) DC and AC electric fields may modulate the deep state charge conditions (Milnes, 1973). In GaAs, for example, charge domains may be created and injected from ohmic contacts when electric fields exceed 500 V cm-' to 1000 V cm-' between nearby devices (Ridley and Watkins, 1961; Ridley and Pratt, 1965; Kaminska et al., 1982). These charge domains travel through the semi-insulating substrate or buffer layer to the collecting contact (cathode or drain in a FET). The motion of these charge packets induces a time-varying electric field under the gate and thereby upsets the channel charge distribution causing a modulation of the device operating conditions (see, for example, Fujisaki and Matsunaga (1988)).

Increasing reverse bias exposes additional deep states

Emitted Charges (Deep Levels Empty) Free charges may be recaptured by deep or shallow states Shallow Donor Level

Fermi Level

N-type Semiconductor

Valence Band Edge

Figure 10-18. Schematic representation of the near-surface band bending in an n-type semiconductor. Shallow donors are partially ionized. Deep levels are occupied within 2 k T of the Fermi level, and filled below the Fermi level crossover points. When the state is lifted above E,, charges are emitted at rates proportional to their respective depths, the temperature, emission characteristics, and rate of band bending. The charges may be recaptured during relaxation processes and re-emitted, leading to an oscillatory condition.

524

10 Compound Semiconductor Device Processing

In the case of field effects there are two main components. The DC contribution involves the equilibration of deep state capture and emission processes. This is typically a very slow process leading to long turn-on transients upon biasing, device latch-up, and an “improper” DC operating state. Depending on the material’s condition, these transients may be of the order of nanoseconds to minutes. The details of this quasi-equilibrium condition are affected by the operating temperature, and the temperature distribution in the device through the capture and emission rates and the concentrations of the deep states. The charge exchange processes can produce additional time constants in the temporal response as the device heats during operation. Localized anomalies may arise as different regions of the device may dissipate varying amounts of heat during operation. The AC effects are essentially resonances of the deep state capture and emission rates with the operating frequency of the devices. For example, i n GaAs there are at least 20 known deep levels of electron- and hole-like characteristics in the energy gap (Martin et al., 1977). Thus, for a given temperature, electric field strength (biasing condition and voltage swings), active layer configuration, and circuit layout, a number of traps may be exposed within a device as shown in Fig. 1018. As the device changes state in response to an input, the trap exposure about the Fermi level is altered, and the emission or capture of charges by the trap(s) may be stimulated. This leads to the “resonance” condition. The electrical manifestations of deep levels may be observed as long time constant effects, impaired transient responses, “ringing” in the device characteristics. or an apparent lack of device gain (Lin et al.. 1990; Vuong et al., 1990; Smith et al., 1988b). Similarly, the back-plane or substrate bias can modulate the channel charge distri-

bution in FETs through the electric field created between the back-plane and the channel, thus upsetting the threshold and current-carrying capability in the devices. Again, as the electric fields are modulated, the channel charge distribution responds with multiple time constants determined by the trapping behavior of the exposed deep levels, particularly those at the bufferinterface (epitaxial layers) or in the tailsubstrate of the implant profile. These effects are not subtle: sidegating and backgating phenomena, either static or dynamic, can lead to collapse of the transfer characteristics, or pinch-off resistors and transistors, as illustrated in Fig. 10-19. In extreme cases, sidegating can impact devices separated across an entire 3” (76 mm) wafer (Gray, 1989). The typical manifestations are devices operating well below expected performance levels, or the intermodulation effects as devices switch to different states and the electric fields are altered. These phenomena are well known and relatively well

10. 8-

SIDEGATE 2 pin

-8

10.4 Diffusion

understood (D’Avanzo, 1982; Vuong et al., 1990; Smith et al., 1988a; Ridley and Watkins, 1961; Ridley and Pratt, 1965; Milnes, 1973). A highly effective method for isolation in GaAs devices has been discovered: a “lowtemperature buffer” (LTB) grown by MBE (Smith, 1988 a). This approach capitalizes on the extensive defect structure created by epitaxial crystal growth at low temperature under strongly nonequilibrium growth conditions. The material produced by this process is nearly completely inactive, both electrically and optically (Kaminska et al., 1989). Smith et al., 1988b, has found that the DC isolation and DC sidegating immunity are greatly improved: negligible interactions are found for DC electric fields in excess of 10 kV cm-’. However, unless other measures are taken to displace device active regions well away from the LTB, the high-frequency performance of circuits fabricated on these buffer layers is drastically affected. It has been found that integrated devices operating at - 1 GHz, as fabricated with “standard” processing methods, are slowed to the kilohertz regime when constructed with the LTB structure without having sufficient isolation from the LTB (Lin et al.. 1990). This effect was attributed to electron trap-related charge capture and emission with very long time constants. To circumvent these problems, a second relatively thick standard buffer layer must be grown on top of the LTB to minimize the effects on charge transport behavior in transistors (Smith et al.. 1988 a,). Subsequently, the devices must be laterally isolated to prevent or mitigate the normal sidegating effects. “Low temperature” buffer layers have been greatly improved in the latter part of the 1990s, and are commonly used in epitaxy-based fabrication processes (Wang et al., 1997). The importance of controlling or eliminating interactions in compound semicon-

525

ductor-based devices continues to drive investigations into the trap-related, semi-insulating characteristics of GaAs and analogous effects in other III-V semiconductors. At the present time, there are methods for mitigating the sidegating and backgating effects, but it appears unlikely given the nature of the compound semiconductor materials and their defect structures, and the desirability of the semi-insulating behavior, that these problems will be totally eliminated.

10.4 Diffusion Diffusion and impurity redistribution are of great importance and consequence in device fabrication processes. Diffusion has been the subject of extensive investigation (Tuck, 1988). The intentional diffusion of impurities is required in numerous fabrication steps. Often, however, the diffusion of impurities and the interactions amongst the various materials present on, and in, the wafer are highly undesirable. As examples, p-n junctions generally become less abrupt and the electrical and physical (chemical) junctions may shift when the impurity species diffuse, or when mixed chemical species interdiffuse, such as with a GaAs : AlGaAs heterointerface. In heterostructure bipolar transistor (HBT) structures, the “misalignment” of the electrical and physical junctions strongly compromises the device electrical characteristics and device performance (Ali and Gupta, 1991). Rapid in-diffusion of gold in an ohmic contact region may cause device failure via punch-through (“spiking”) or lateral migration (Zeng and Chung, 1982). Silicon donor redistribution in HFET devices will alter the channel charge distribution, shift the device threshold voltage, the transconductance (g,), and affect the current carrying ability of the

526

10 Compound Semiconductor Device Processing

channel (see Daembkes, 1991 and references therein, and Schubert, 1990). The diffusion behavior is characterized by a parameter known as the diffusion coefficient, and is controlled principally by the chemical potentials of the host and impurity atoms in the lattice, and the impurity concentration distribution(s). Defects, such as vacancies, interstitials, impurities, and the relative physical sizes of the host lattice atoms and the impurity, the bond strengths and the dimensions of the lattice interstices all affect the atomic mobilities and the diffusivity of the impurity atoms. Diffusion processes are mathematically represented by several empirical relationships known as Fick’s laws. The first of these laws considers the flux of a diffusing species (in one dimension), J , through a plane in a direction x, at any time (f):

(IO- 1) where C is the concentration, dC/dr is the concentration gradient, and D is the diffusivity. Equation ( I O - 1 ) describes the driving force behind diffusion: a concentration gradient, i.e., a chemical potential difference which, from thermodynamic arguments, must become negligible as the system reaches equilibrium. Equation (10- 1) is illustrated schematically i n Fig. 10-20, The relative ease with which a given species moves in the lattice is embodied in the magnitude of the diffusivity. Fick’s second law relates the change of the concentration profile with time [taking the derivative of Eq. ( I O - l ) ] ( 10-2)

Equation (10-2) describes 1 ) how rapidly the material will redistribute in the host lattice, and 2) the concentration profile as a

I t

Characterized by:

Doe - EanT

Distance into Semiconductor Surface

Figure 10-20. Schematic diagram of a “erfc” diffusion profile, represented by a single-value diffusion coefficient, D o , and a unique activation energy, E,; k and T have their usual meanings.

function of time and distance. Using the grad operator, Eqs. (10-1) and (10-2) may be extended to accommodate the real threedimensional behavior of the diffusion process in the crystal lattice. Implicit in these descriptions is the temperature sensitivity of the diffusion process, which is accounted for in the diffusivity. The diffusivity is defined as

D = Do exp (- E , / k T )

(10-3)

where Do is the diffusion constant, E, is the activation energy for the diffusion process, k is the Boltzmann constant, and T is the temperature (K). In addition, the diffusivity of an impurity is sometimes dependent on the concentration, typically being enhanced at higher concentrations. Therefore to realize a high degree of stability against elevated temperature processing, it is desirable that an impurity species have a large activation energy, a small diffusion constant (see, for example, Tuck, 1988 or Shewmon, 1963, and be present in reasonably low concentra-

527

10.4 Diffusion

tions (- 100 ppb to 100 ppm) to minimize impurity-impurity interactions in the lattice. The segregation coefficient k for an impurity species is a measure of the tolerance of the host lattice for the impurity atom. It is defined from solidification processes as the ratio of the concentration of the impurity incorporated into the solid relative to that in the liquid phase during crystal growth. With respect to the solid state, the segregation coefficient can be interpreted in terms of the additional driving force for diffusion: A small value of k implies a relatively large energy for redistributing the impurity in the host. [n compound semiconductors most impurities have segregation coefficient values of less than one which represent an additional driving force for the out-diffusion behavior. The crystal lattice is distorted by the presence of the impurity atoms due to size and/or the chemical incompatibility. The extra energy available tends to drive the impurity species from the lattice. The free surfaces, or those surfaces and interfaces under strain due to mismatched physical properties (e.g., heterostructures, dielectric layers, metals, etc.), will also provide added energy for diffusion, and may act as sinks for the diffusing species. Also, the solid solubility limit places an upper limit on stable concentrations of impurities in the lattice: concentration above this level will increase the driving force for redistribution, precipitation, size exchange processes, and electrical compensation. In GaAs it has been observed that the diffusivities of the groups IV and VI donor type species are generally small, whereas the group I1 acceptor species tend to diffuse much more rapidly. Carbon, a group IV acceptor, is a notable exception, being extremely stable in most compound semiconductor lattices (Schubert, 1990; Schubert et al., 1990).

Two additional concerns for the processing of compound materials at elevated temperatures are the increased vibration frequency of the lattice atoms and the dissociation of the compound semiconductor material. The motion of the atoms in a compound semiconductor lattice can create a variety of electrically active point defects (Hurle, 1977; Van Vechten, 1975), and diffusion may cause an undesirable redistribution of the impurity atoms. As a result, the electrical properties of the material may be altered in an uncontrollable manner. For the compound semiconductor materials GaAs and InP, the dissociation rate is significant for temperatures above - 600 “C and 475 “ C , respectively (Panish, 1974), and similarly for GaP and some 11-VI compounds. This is due to the high partial pressure of the group V (or group VI) species over the host material, as illustrated in Fig. 10-21 [after Thurmond (1965)l. The key point in this figure is the region around the congruent decomposition pressure. By controlling partial pressures of the various species the decomposition may be suppressed. Without some mechanism for protecting the surface region during high temperature processing, either with a cap layer or an overpressure of the group V species, the surface rapidly decomposes creating a metal-rich surface, enhanced dissolution of the surface layers, and destruction of the semiconducting properties. It is therefore critical to maintain a minimalistic approach to the thermal processing of most compound semiconductor materials. RTA (rapid thermal annealing) cycles or “low thermal budget” (i.e., lowest possible temperatures and minimal times) processing are needed to maintain the impurity profile and materials integrity in the near-surface region. For successful device fabrication, knowledge of the stability of the donor and acceptor species in the lattice is critical. The dif-

528

10 Compound Semiconductor Device Processing 1200 1100 I

lo00

900

800

“C

lOVT, 1M

Figure 10-21. The equilibrium vapor pressure (in atm.) of As, Ga, As2 and As, over GaAs as a function of IO‘ T-’. The total arsenic pressure (referred to As,) is approximately 1 atm. (IO’ Nm-’) at the melting point, 1238°C. [Reproduced from Thurmond (1965). Reprinted with permission. 0 1965, Pergamon Press.]

fusion coefficient values for most usable impurities are in the range of 10-3-10-6 cm2 s-’ at the temperatures used for epitaxial crystal growth, ion implantation annealing, and wafer processing, and thus most species move quite rapidly in the lattice (Tuck, 1988, Chaps. 4,5;Shewmon, 1963). For example, one advantage of an epitaxial-grown MESFET device process sequence is the ability to minimize the thermal budget, leading to a limited redistribution of the donor impurities. In contrast, in a similar ion-implanted MESFET process, the thermal budget and maximum temperatures are extremely critical to the impurity distributions and activation. The resulting charge distribution, and the final device characteristics

are greatly affected by processing times of the order of seconds or tens of degrees, particularly for the ultra-thin, ion-implanted structures required for high-speed or low noise operation. On the other hand, high-temperature furnace or rapid thermal annealing of selfaligned MESFET and HFET devices is necessary and readily accomplished when refractory gate metals are used. The limited reactivity and stability of the refractory metals with most compound semiconductors permits the temperature to be raised above 800°C (for GaAs) sufficient to anneal the ion implantation damage, restore the lattice disorder, and activate the implanted species (Dautremont-Smith et al., 1990; Yamasaki et al., 1982; Shimura et al., 1992). At the same time, the impurities which provide charge to the channel may diffuse large distances (tens of nanometers), leading to uncontrolled device characteristics and poor performance, emphasizing the need for strict control and understanding of the timetemperature cycle impact. In other processes, if ion implantation is not used for doping, substantially lower thermal budgets may be used. Si redistribution during annealing processes was investigated in GaAs/AlGaAs heterostructure (HFET) materials (Schubert et al., 1988, 1990). It was found that the diffusivity of silicon was roughly ten times higher in AlGaAs than GaAs at 800°C. This places significant constraints on the device structures, particularly for HFET devices which may incorporate a “setback” (intentional spacing of the impurity species away from the channel region) to keep the ionized donors separated from the electrons that reside in the potential well (Sequeria et al., 1990; Baret al., 1993; Danzilio et al., 1992). In a typical annealing cycle the Si atoms may diffuse more then 5 - 15 nm, thereby placing a significant fraction of the Si atoms

529

10.4 Diffusion

in the channel region. This phenomenon will be realized as a reduced electron mobility and somewhat impaired electrical performance. One of the anomalies in the diffusion behavior of most acceptor species in compound semiconductors is the double diffusion front (Tuck, 1988; Gosele and Moorhead, 1981). In this case the impurity appears to have at least two distinct values for thc diffusivity. These phenomena have been explained in terms of interstitialcy and substitutionality of the diffusing species. Interstitials have significantly lower activation energies for motion in the lattice, and therefore larger diffusion coefficients since there is no requirement for atomic site-exchange to allow motion within the crystal lattice (Gosele and Moorhead, 1981; Small et al., 1982). The interstitial atoms may therefore move very rapidly in the host material. The substitutional impurity, on the other hand, requires the presence of a vacancy or the exchange of adjacent lattice atoms to permit motion of the impurity. Such an exchange process requires the addition of significant amounts of energy, and the cooperative motion of several atoms. The activation energy for such a process is relatively large, the probability of site exchange is small, and the substitutional diffusion process is slow. The double diffusion behavior is illustrated in Fig. 10-22 for zinc in GaAs (after Tuck, 1 9 8 8 ~ )It. is clear that there are at least two mechanisms operating in this case, with significant differences in diffusivity values as well as the relative concentrations of interstitial and substitutional impurities. Several investigations have been carried out to understand the behavior of anomalous diffusers such as Mg, Zn, and Be (Small et al., 1982; Cunnel and Gooch, 1960; Gosele and Moorhead, 1981). At the present time, although the mechanisms for explaining the double diffusion from behavior are well-ac-

100

150

Depth

200

250

300

(wm)

Figure 10-22. Experimental diffusion profiles for zinc in GaAs at 1000°C. A, B, C, and D represent the zinc concentration profiles after 10 min, 90 min, 3 h, and 9 h, respectively. Note the two unique regions for the concentration profiles in each case. [Reproduced from Tuck (1988). Reprinted by permission of Adam Hilger/ IOP, 0 1988.1 Note: Ordinate axis label corrected from the original publication.

cepted, the precise understanding of the processes by which the species simultaneously select both types of diffusion paths has yet to be elucidated. As device processing continues to improve, more stable species, such as carbon, are being utilized for acceptor doping. However, carbon is not a panacea as the effectiveness for doping in a number of ternary and quarternary compound semiconductors is very limited. As mentioned above uncontrolled impurity redistribution can seriously affect device performance. These effects are often seen in one of the moore promising device structures, i.e., the heterostructure bipolar transistor (HBT) based on GaAs/AlGaAs epitaxy (Ali and Gupta, 1991). Owing to “band gap engineering” (Capasso, 1987,1990)and the properties of GaAs-based and InP-based ternary compounds, an HBT device in these

10 Compound Semiconductor Device Processing

530

It has been observed that the Be atoms redistribute so significantly in the lattice that this method of doping the p-base region is essentially impractical for use in controlled, reproducible HBT fabrication (Miller and Asbeck, 1985). Streit et al., (1992) claim to have solved the Be redistribution-related degradation problem by controlling certain growth parameters in the MBE growth of HBT structures, although these devices were operated at modest performance levels (Streit et al., 1992). Other p-type transition-metal species also behave in a manner similar to beryllium, but are not generally utilized for this reason. Accelerated device aging tests showed that Be doped base HBTs can be relatively stable to self-diffusion failure mechanisms under low to medium power conditions, as shown in Fig. 10-23 (Yamada et al., 1994). They found failures (under accelerated aging conditions) occurring at - 300 h, 230°C, and an apparent activation energy of - 1.4 eV, which translated to projected operating lifetimes of - lo6lo7 h at a junction temperature of 125°C. Carbon, however, has been found to be very stable in compound semiconductor crystal lattices, and therefore appears to be the practical alternative for p-type doping in

materials is capable of switching in the hundreds of gigahertz, many times faster than the fastest silicon-based counterpart (Nubling et al., 1989; Nottenberg et al., 1989). Many of these HBT devices have been fabricated in MBE-grown epitaxial materials. using Be for the base dopant species (Kim et al., 1988;Miller and Asbeck, 1985; Streit, 1992). Investigations into the performance of Be doped base HBTs and the fundamental processes of diffusion of beryllium in GaAs have shown that this impurity diffuses extremely rapidly (Hafizi et al.. 1990). This poses a difficult problem for the crystal grower and the process engineer, as significant impurity redistribution can occur during crystal growth. During even modest thermal processing, and subsequently during the device operation rapid diffusers can move in the crystal lattice, the latter effect being induced by elevated junction operating temperatures and the extremely high electric fields in the devices (Ah and Gupta, 1991). As a result of the Be redistribution at the emitter-base junction, the p-n junctions shift in an uncontrolled manner rendering the materials unsuitable for device applications (Hafizi et al.. 1990; Yin et al., 1990).

30 0

-30

-60

-90

E 2

-120

9 4

-150

-180 -210

-240

Z15"C/biased 215"C/no bias [hot controll e 25"C/nO bias (controll --t

100

I 200

I 300

400

500

Stress Time (Hour)

600

700

800

Figure 10-23. A plot of the change in output voltage of a HBT-based circuit as a function of stressing time at 215°C. Parts which have not been subjected to current stress are shown as open circles and open squares. Parts which have been biased are shown as closed circles. At 21S°C, the output of the circuit degrades substantially up to 800 h . This indicates a change in the bases emitter junction, or a modification of the emitter contact resistance due to impurity diffusion. (Reproduced from Yamada et al. (1994). Reprinted with permission. 0 1994 IEEE.)

10.5 Etching Techniques

many 111-V materials (Abernathy et al., 1989; Maliket al., 1989; Quinn, 1992- 1993).Carbon may be introduced into the lattice by ion implantation or during crystal growth when carried out with techniques such as metal -organic chemical vapor deposition (MOCVD) or gas-based molecular beam epitaxy methods (chemical beam epitaxy CBE or gas-source molecular beam epitaxy - GSMBE) (Abernathy et al., 1989; George et al., 1991). Several solid-phase carbon sources have been fabricated and used in standard MBE crystal growth (EPKhorus, 1994; Maliket al., 1989). Hole concentrations in HBT base layers exceeding lo2’ cm-3 have been realized without apparent problems with diffusion and redistribution. However, a significant lattice contraction occurs at these high carbon concentrations (above - 3-5x 1019 ~ m - George ~, et al., 1991), with strong reductions in the hole mobility due to scattering events (Quinn, 1992- 1993). The formation of large numbers of line defects in base regions for these high carbon concentrations raises significant questions of long-term device reliability. Owing to the issues outlined in this section, there are only a limited number of solely diffusion-based processes remaining in compound semiconductor technology. For example, the JFET fabrication sequences are hybrid processes using diffusion of the p-type species to create the junction or highly doped p-contact region in an n-type material formed by epitaxy or ion implantation (Zuleeg et al., 1984, 1990; Wada et al., 1989). These diffusion processes are similar to those employed in silicon-based process sequences with the notable exception that they require very sensitive control of the process conditions. This is due to the large diffusivity of zinc or beryllium acceptor species, and the need to prevent dissociation of the host material due to the high vapor pressure of the group V elements.

531

The concern for rapid diffusivities arises also when considering reliability issues significant redistribution of any impurities or defects in the active regions of the devices will degrade performance and lead to field failures (Hafizi et al., 1990; GaAs IC 1992, 1993a). This has been observed in HBT devices, for example, where the performance characteristics decay rapidly as the device is operated under moderate to high stress conditions (Yamada et al., 1994). As previously, noted, the deterioration has been assigned to the redistribution of beryllium atoms in the base region of the device caused by thermal and electric field-aided drift of beryllium ions (Miller and Asbeck, 1985; Hafizi et al., 1990)

10.5 Etching Techniques Material removal may be carried out by “wet” chemistry, or by “dry” (vapor or plasmdsputtering) techniques. Etching processes can be used to delineate the features of active and passive devices, form electrical contacts, gate recesses, and vias, and create isolation trenches. The most critical issue is the ability to create an etched feature which has an optimal morphology compatible with the subsequent processing steps. The choice of wet or dry chemical etching methods depends upon the processing sequence, the required degree of etching control, the materials compatibility, and the availability of a suitable etchant for the target material. In addition, the etchant must not affect the masking or etch stop materials, and the other materials exposed during the etching process. Additional considerations are the control of undercutting of the mask layer (dimensional variation), the creation of anisotropic features, and the permissible process latitude.

532

10 Compound Semiconductor Device Processing

Various etchants and methods may be used in the process sequence for defining device features or general etching processes. Anisotropy and materials selectivity are critical and very useful features of etchants and the different etching processes. The crystallographic sensitivity of the etching chemistry can be utilized to form selectively sloped side walls for smooth metal coverage or to create a controlled undercut to prevent metal continuity where desired (see Sec. 10.9, liftoff processes). At the same time, the undercutting of photoresist layers or other masking materials by lateral dissolution of the semiconductor, dielectric layers, or metals can give rise to very undesirable expansion or contraction of etched features. Reaction products are important in all aspects of etching, i n both wet or dry methods. Such by-products may impede contact between the etchant species and the surface atoms. They can lead to anisotropic effects resulting from build-up on the various exposed crystallographic planes, or block the etching process entirely. Bonding of the reaction products to the surface may further alter the etching characteristics. In wet processes continual solvation of the reaction products into the solution alters the pH and therefore the chemical activity and the etching rates. In a similar manner, with dry etching, the poisoning of the plasma by reacted species may drastically alter the effectiveness of the etching process. Thus it is important to ensure adequate chemical flows in either wet or dry processes. The understanding of all of these competing effects is a critical element in developing a viable. controlled, and reproducible etching process. For both dry and wet etching processes, the main limitation (in typical compound semiconductor (CS) processing sequences) is the inability to readily etch gold, which is one of the principal metals in CS device fabrication. However, ion milling or liftoff pro-

cesses produce excellent results in gold metallizations, even with very fine geometries. It should be noted that significant efforts have been directed to creating aluminumbased metallization schemes for interconnects (Vitesse, 1990, 1995), and the use of titanium or tungsten-based metals to overcome the limitations of the liftoff processes needed for gold metallizations (GaAs IC, 1993b, Dautremont-Smith et al., 1990). Reactive ion etching or sputtering may also be used for the etching of various layers during processing. In this case, the rate(s) of sputtering the desired material(s) relative to that of the masking material(s) is crucial to the success of the process (Melliar-Smith and Mogab, 1978; Chapman, 1980). The chemical anisotropy of the compound semiconductor materials plays an important role in the formation of etched structures. The shape of an etched feature may be strongly influenced by the polar nature of the zincblende-type lattice and the anisotropic behavior of the etchant. For GaAs, anisotropic effects are further complicated by the existence of two standards for the substrate orientation. These two options are denoted “SEMI US” (wedge) and “SEMI E/J” (dovetail) (SEMI Standards, 1989). Both of these specifications adhere to the same electrical and physical characteristics as the SEMI standards, but they are rotated 90” about the (100) with respect to each other as shown in Fig. 10-24. As a result, the same chemical etchant may produce different (rotated 90”) etching features in the two wafer configurations. Thus, it is critical to understand the interactions of an etchant with the surface layers to ensure the formation of a desired morphology.

10.5.1 Wet Etching

To remove undesired material(s) from the surface region, solutions of appropriate

10.5 Etching Techniques

KOH ETCH PIT

533

OF WAF$

Figure 10-24. Crystallographic representations of the two standard configurations for gallium arsenide substrates. The etch pit configurations for each orientation are shown in (b) and (d) and on the central part of the crystal plane image. The etching response of the crystal with respect to the central axis is illustrated by the relative positions of the “V-groove” and “dovetail” etch figures. (a) V-groove option (known as the US standard); (c) dovetail option (known as the E/J standard). Note that the minor flats are 180” in opposition between the two orientations. (Figure courtesy of SEMI, Mt. View, CA, reprinted by permission.)

chemicals (acids or bases and diluents) may be used. The etchant solution must be constantly in contact with the target material, and must typically be stirred or sprayed onto the wafer surface to ensure the constant replenishment of the etchant at the surface and to remove by-product materials (Shaw, 1981; Stirland and Straughan, 1976; Iida and Ito, 1971; Mukherjee and Woodard, 1985). The effects of stirring are typically observed as significant increases in etching rates relative to stagnant solutions, as shown in Fig. 10.25. Without agitation or replenishment, the etchants may produce significant undesired topological changes in the surface. Some means of arresting the etching process rapidly and uniformly must be provided to neutralize the etchant and com-

pletely remove the reacted material(s) in order to ensure reproducibility and control. Wet etching occurs by an oxidation process followed by solvation of the reacted species. The etching solution generally contains both the oxidizer and a solvent, and the CS-oxide species and reactants are preferably readily soluble materials. A complexing or buffering agent may be added to stabilize the etchant chemistry, and deionized water is commonly used as the diluent. A key issue in wet etching control is the boundary layer at the interface between the solution and the semiconductor surface. The schematic representation of the boundary region is shown in Fig. 10-26. The boundary layer controls the etching process through the exchange rates of the oxida-

534

10 Compound Semiconductor Device Processing

Temperature

Figure 10-25. Etch-rate dependence on temperature and forced convection. The etchant is H,SO,-H2O2-H20 (8 : 1 : I ) , with an addition of 50 wt.% citric acid. The ratio of HzOz (3070) to 50 wt.% citric acid is 1 : I by volume ( k = 1 in the figure). It can be seen that the effects of stirring are dramatic, as is the importance of temperature and therefore temperature control of the etchant and the etching rate. [Reprinted from Howes and Morgan ( 1 985). Reproduced with permission. 0 1985 John Wiley and Sons, Ltd. Figure caption modified by author (original data after Iida and Ito (1975). and Otsubo et al. (1976).]

("C)

100

Solution

*\.

x.\

Slirrinq

4 f

k =1

.-C

c V

103/T ( K - ' )

Substrate

ConvectiveTransport Region

Material

Turbulent or Laminar Flow

I Msrokcd Specha into Solvent Bulk

I I I

I I

tion-dissolution cycle, i.e., the removal rate of the surface materials relative to the arrival rate of fresh reactants to the surface. For extremely critical etching processes such as gate etching (FETs) or the emitterbase junction (HBTs), a weak oxidizer may be applied first, followed by a solvent solution so as to remove only a very thin surface

Figure 10-26. Schematic representation of the region adjacent to a semiconductor interface during chemical etching. The diffusion boundary layer is the controlling region for the transport of species to: and out from, the interface. A similar diagram can be utilized for gas-phase chemistry, with varying mean-free-path lengths and very high convective velocities in the bulk gas phase.

layer rather than maintaining a constant etching process. Repetition of the process results in a step-wise approach to the final gate trough depth and shape. While timeconsuming, this approach can provide an extremely high level of control. Table 10-4 presents a number of liquid etchants suitable for compound semiconductor materials.

10.5 Etching Techniques

Table 10-4. Common etchant compositions for compound semiconductors. Chemical formulation NH4OH

H,02

: H,O

H>SO,: H,O,: H,O

HCI : HNO,

H3P04: H,02 : H,O

Br - MeOH

Ratio

Reference

I : 2 : 20 Shaw (1981) 3 : 1 :50 Gannon and Neuse (1974) Adachi and Oe 5 :1:1 (1983) Shaw (1981) 1:8:40 Adachi and Oe 1: 3 (1983) Adachi and Oe (1983) Adachi and Oe 5 : 1 : 20 (1983) Mori and 1.9.1 Watanabe ( 1 978) Adachi and Oe 1 : 100 (1983)

Choice of a specific chemistry depends on the morphology and degree of control desired in the fabrication sequence. There the two basic limiting mechanisms in wet etching: diffusion-controlled and reaction-rate-limited processes. In the diffusion-controlled case, the transport of reactant to the interface and the transport of the reacted products away from the interface are moderated by the diffusion boundary layer. Material transport limits the etching rate as diffusion coefficients in liquids are typically in the range of lop5cm2 s-’. Therefore it may take a significant time for materials to reach the bulk liquid where convective flows (- cm s-’ velocities) dominate. Additionally, there may also be an “incubation period” for etching initiation, Le., the time required to come to a steady-state etching condition due to impeding surface layers or interfacial chemical imbalances. Typical wet etching rates are in the range of a few nanometers per minute to tens of micrometers per minute depending on the etchant agitation and dilution factors. For example, in

535

a gate etch process where control is crucial, the etch rate employed should be very slow. In contrast, for a backside via-etch a very high rate is needed to etch through (25 p m (- 1 mil) to 350 pm (- 14 mil) of substrate, while at the same time, a high degree of anisotropy is important to prevent lateral spreading and undercutting. Diffusion-limited etchants are relatively isotropic in general, as the surface reaction rate is orders of magnitude shorter than the residence time in the diffusion boundary layer. Agitation greatly affects the etch rates of diffusion-limited processes, as the diffusion boundary layer thickness is easily modulated by forced convective flow (see Fig. 10-26). Thus care must be exercised in wet etching processes to ensure stable, uniform and reproducible etching conditions. In the reaction-rate-limited case, the dissolution rate is determined by the rate of chemical interactions at the interface. Typically, reaction-rate-controlled etchants are anisotropic since the surface reactions are modulated by the density of atoms on the surface planes, and the availability of free electrons at the surface. Etching is therefore dependent on the surface atom density, the electrons configuration, the doping concentration, and any surface reconstruction. Convective flow generally has a minimal effect on reaction-rate-limited etchants, as the transport rate of etchant to the surface does not generally affect the reactions unless the solutions are highly dilute. Reaction-ratecontrolled etchants may either preserve the morphology existing at the initiation of etching, or more often, develop anisotropic shapes as crystallographic effects influence the local etch rate (exposing planes of higher or lower atom density). Reaction-rate-controlled etchants that exhibit strong anisotropy are very desirable for defining gates, mesas, vias, troughs, or other high-aspect-ratio features, but are

536

10 Compound Semiconductor Device Processing

highly unsuitable for planarizing the surface or pre-crystal-growth surface preparation. In either case the formation of a remanent oxide layer can inhibit the interfacial reactions and affect material transport, thereby affecting the etch rate in both diffusion and reaction-rate-limited processes. Wet chemical also generally very sensitive to temperature, as illustrated in Fig. 10-25, and may also be sensitive to above bandgap light exposure (electron-hole pair generation), Etchant reactivity is nearly always enhanced by an increase in temperature, although depletion or exhaustion of the etchant solution accelerates at higher temperatures (Otsubo et al., 1976). Reaction-ratelimited processes are much more temperature-sensitive than diffusion-limited solutions. During the etching process, the reactions at the surface involve the breaking of many chemical bonds, and therefore energy is evolved. The temperature rise associated with the etching process can upset the local as well as the global etch rate, depending on the etching rate and the net free energy liberated in the reaction. Therefore it is optimal to provide relatively large volumes of etchant, and to provide temperature control to ensure stable etching conditions. The sensitivity to light is manifest through the creation of electron- hole pairs in the surface region, which may affect the charge exchange processes at the semiconductor-etchant interface. The presence of near or above bandgap energy may increase etching rates or create anisotropic effects from surface charge density differences. Thus care must be taken to control illumination of the wafers, the light intensity, and the spectral content, to ensure reproducible etching processes; etching in the dark is preferable. A difficulty with wet chemical etchants is maintaining the reproducibility of the chemistry and reaction conditions. Several

problems can arise in wet chemical etching processes: sensitivity to the etchant, temperature, the pH of the solution, chemical depletion, the presence of light, passivating layers, and the methods of application, e.g., immersion, agitation, spray and spin, etc. The etchant solutions deplete with usage (buffering may slow this process) and age (chemical breakdown during storage, heat, or exposure to air). Recirculating solutions, while reducing some waste handling issues may be more troublesome to control, because the solution chemistry is constantly changing. During use, the chemical potentials may be altered (the pH changes) and diluent species (water and other contaminants) are formed during the reactions, thereby diluting the solution. Light of an appropriate wavelength can increase the etching rates may-fold by creating electron-hole pairs at the surface or assisting in the breaking of bonds. The presence of an increased charge density (dopant species) will nearly always increase the reaction rates at the surface. Wet etching solutions often produce gaseous by-products (e.g., H,, O,, Cl,, Br,, or other volatiles). The formation of bubbles and bubble streaks on the wafer may inhibit or accelerate the etch rate depending on the nature of the surface reactions. This bubbling phenomenon may lead to nonuniform etching across the wafer surface, and can damage the surface morphology. For example, spiking at mask edges and openings can occur due to stagnation of the etchant material (Shin and Economou, 1991). Agitation or stirring can alleviate some of these problems. The use of spray etching methods avoids the difficulties of immersion-type etching baths, and can produce vastly superior terms of reproducibility and control of the etching process (Grim, 1989, 1990). However, the application rates must be sufficient to prevent etchant depletion, and uni-

10.5 Etching Techniques

formity can be more difficult to control with diffusion-controlled etches. Anodic etching is another “wet” method for removing the surface layers in a controlled manner. Here the wafer is fitted with an electrical contact, immersed in an etchant solution, and then biased to create a depletion region of the surface. The anodic oxidation reaction creates an interface charge which balances the impressed electric field. As etching proceeds, the surface potential is gradually equalized over the wafer surface, i.e., a relatively uniform surface oxide is created. Subsequently, this oxide may be removed by a suitable solvent and the process repeated until the desired amount of material is removed. In principle this method is well-controlled. In practice, significant problems arise with localized variation in the surface potentials, nonuniform current distribution, effects of localized charge (e.g., n- or p-type regions, semi-insulating regions, etc.), the impact of residues and surface contamination, and the presence of metals, which greatly complicate control of the etching uniformity. The high resistivity substrates of GaAs and InP commonly used in IC fabrication also cause problems owing to the limited current flow permitted with reasonable bias voltages. Furthermore, the etching occurs in discrete steps which creates a “digital” thickness change with each step and protracts the etching cycle greatly. Some of the additional problems associated with wet etching are the undercutting of the surface layers or masks due to capillary effects and chemical anisotropy. Surface tension, viscosity, anisotropy, solubilities, and convective flows all conspire to reduce the control over the critical dimensions, the morphology, and the uniform arresting of the etching process. The capillary effects may be realized as “blow-out’’ or expansion of the feature peripheral dimen-

537

sions, and contraction (undercutting) of interior features. These phenomena also affect the control of the etching end-point when rinsing the etchant from the surface. Crystal lattice and etchant anisotropies, as well as flow-related effects and surface tension effects, can radically affect the shape of the etched feature. Some illustrations of different feature shapes are shown in Fig. 10-27. Once the desired chemistry is determined and understood, wafers may be routinely processed with wet etching methods. The etching of gates, vias, mesas, and channels are quite similar processes, the aim being to create a hole in, or a mesa on, the surface for the purpose of forming the gate trough, holes for interconnect vias, and isolation between devices, respectively. The selectivity of wet etchants can be exploited during fabrication by including etch stop layers in the epitaxial materials. With these materials, differential etch rates of 10000 to 1 can be realized (Ren et al., 1995). Wet etching may be used to subtractively define resistors or capacitor plates on or in the surface layers, although dry techniques are generally preferred for this process (see Sec. 10.5.2). In addition, wet chemical processes are typically used for the preparation of the substrate surfaces prior to crystal growth or processing. For additional information, see Williams (1990, Chap. 5 ) . 10.5.2 Dry Etching Dry etching of compound semiconductor materials encompasses the generic methods of plasma-based surface decomposition; sputtering, plasma etching (PE), reactive ion etching (RIE), reactive ion beam etching (RIBE), and electron-cyclotron resonance etching (ECRE). All of these etching technique involve the creation of excited or reactive chemical species which selectively

538

10 Compound Semiconductor Device Processing

Figure 10-27. A schematic illustration of various etched shapes which can be created by wet or dry etching techniques. In a ) a strongly “undercut” shape is shown. This morphology would be ideal for a metal liftoff process. but undesirable for metal or dielectric coverage. In b), the crystal anisotropy has dominated the etching process, producing an etch morphology that has been limited along the [ 1 1 I ] crystal planes. Figure 10-27c illustrates a method by which very small features may be created: undercutting the masking material. Here a feature substantially smaller than the mask line is formed as material is removed from the exposed sides of the desired material. Depending on the etching conditions, anisotropy, and chemistry, vertical side walls, selectively curved side walls, or undercut features may be created, or highly selective etching may be carried out.

physically sputter, or react with, the target material(s) while minimally affecting the masking agent and those desirable materials that remain. Successful dry etching processes require careful selection of the reactive species, etching conditions, duration, control of the gas mixture. and the temperature Dry etching is typically carried out in a reduced pressure environment. High-volume vacuum pumps (for maintaining a low pressure), high-tension power supplies and field plates for developing a confined high electric field, controlled injection of the apnrnnriate gases. an ion source (if needed),

and monitoring of the process are required. Many configurations exist for this apparatus. but all systems contain the same basic components. A generalized system configuration is shown in Fig. 10-28. Dry methods are suitable for etching most of the materials present in a compound semiconductor integrated circuit process sequence. As with wet etching, gold is not etched by plasmas, although it can be sputter-etched, or ion-milled. Dry etching processes have excellent spatial resolution and the uniformity is typically very good, variation being of the order of a few percent across a 3” (76 mm)di-

10.5 Etching Techniques

539

Figure 10-28. A schematic illustration of a generic plasma etching system. The plasma, containing a strongly reactive ion, is generated by RF excitation, with optional DC biasing. The reactive gas is injected into the plasma region and maintained in a dynamic vacuum condition. In this configuration, ions may directly bombard the water surface and induce damage in the semiconductor. A carrier or ballasting gas may be used to modulate the reactivity and etching rates. Rotation may be used to enhance the uniformity ofthe etching process. Heating may be used to accelerate or control the etching rate. Exhaust treatment may be required to handle toxic by-products.

ameter wafer in a well-controlled process (O’Neill, 1991). Plasma etching processes have been used to define laser facets, gate troughs, and isolation mesas, as well as to form top or through-wafer via structures. These methods have been used to define submicrometer gates (Sauerer et al., 1992), large diameter through-wafer vias (Chen et al., 1992), and achieve etch rates of 50 pm per hour (Kofol et al., 1992; see also Sec. 10.12). There are several mechanisms that remove material during all types of plasma etching: physical sputtering, chemical etching, and reactive ion etching. Complicating the reactant removal and promoting continued surface reaction are problems associated with the formation of reaction byproducts, surface and gas-phase polymerization, and other reaction inhibitors. These by-product materials act as contaminants in the plasma, as diluents in the gas stream and may block access of the surface to new reactant species or tie-up the reactant species in the gas phase through the formation of

complex molecules or other polymeric species. Chlorine-, fluorine-, or bromine-containing compounds are preferred for the etching gas. Such species as CC14 (Sato and Nakamura, 1982; Inamura, 1979), C1, (Donelly and Flamm, 1981), HC1 (Smolinsky et al., 1981), SiC1, (Sato and Nakamura, 1982), CF, (Schwartz et al., 1979; Harada et al., 1981),CCl,F2 (Hosokawaet al., 1974; Smolinsky et al., 1981), and BCl, (Tokunaga et al., 198 1 ; Hess, I98 1) are commonly used in plasma or reactive ion etching systems. The etching rates of various materials can be balanced or controlled with additions of ballasting gases, such as argon or helium, and the total system pressure may be modulated to alter the plasma density and the impingement and interaction rates at the surface. A process utilizing these types of reactive chemical species is relatively hard on the apparatus, readily attacking the system components in the chamber, the gas control valves, feeds, injectors, pumping systems, pump fluids, and exhaust systems and waste

540

10 Compound Semiconductor Device Processing

treatment facilities. The selection of system components and their exposure to the plasma or gas streams is critical for mitigating contamination of the semiconductors. Exhaust scrubbing and waste treatment is often required to prevent the polluting effects of the effluent gases. The excitation voltage and total RF and DC energy input to the plasma controls the ion creation rate and determines the ion energy distribution. There are frequency-dependent effects in the plasma, excitation being carried out typically at either -300455 kHz or 13.6 MHz (frequencies that do not interfere with communications bands) which alter the ionization efficiencies, ion densities, and energy distributions. The use of 13.6 MHz excitation results in minimal surface damage. while 300-455 kHz excitation tends to severely exacerbate the damage. This can be understood from the point of momentum transfer to the ions: at the lower frequency, ions can travel a significant distance during a cycle, readily impinging onto the surface, causing atomic displacements. At the high frequencies, however, the ions have substantially less time to accelerate into the surface region, and thus have a lower probability of damaging the surface atoms. In addition, the electric field strength and the geometry of the plasma excitation plates have a strong influence on the etching process by affecting the flow of ions to the wafer surface. The system pressure may be controlled over a moderate range which also changes the plasma density, the reactive ion density and formation rate, and thus the etching rate and selectivity (feature shape). Since the plasma contains a significant amount of energetic species, the temperature of the substrates rises typically to -200°C to -300°C during the etching cycle. Heating or cooling of the substrate may be required to control of etching proceqs.

For the various materials exposed to the plasma during etching, the selectivity for removal is determined predominantly by the plasma-materials interactions, but also affected by the system operating pressure (impingement rates). For example, the etching of heterostructure materials (e.g., GaAs/ AlGaAs materials) may be carried out selectively or nonselectively by plasma methods depending on the gas chemistry and relative etch rates. Typical dielectric materials (oxides and nitrides) are readily etched by dry techniques, as are photoresists, the latter are removed particularly well in oxygen containing plasma (“ashing” processes). Nitrides are generally more etch-resistant than oxides. Most metals, except gold, are also etched easily in plasma containing reactive species such as C1, F, or Br (see Williams, 1 9 9 0 ~ )One . major concern in plasma etching is ensuring that the protective coatings maintain their integrity during the etching cycle (etch-rate issues). One difficulty with the phosphorus-containing compounds such as InGaP, GaAsP, or quaternary materials is that these materials do not etch readily in the typical plasma chemistries (Ren et al., 1993, 1995). A key to the successful implementation of plasma etching is controlling the damage induced by energetic ion bombardment of the exposed surfaces. This is especially true for devices using “shallow” p-n junctions or lightly-doped layers in the materials structures. Damage created by the injection or recoil of energetic ions can produce atomic displacements and create donors, acceptors, and deep levels, thereby alterating the charge i n the surface region. The use of high frequency (13.6 MHz) excitation reduces there effects. To mitigate these effects there are parallel plate configurations with differing ratios between the upper and lower plate areas that control plasma confinement (density and impingement rate) and ion

10.5 Etching Techniques

guiding effects, and “downstream” designs wherein the plasma region is confined “upstream” well away from the substrates (Pearton et al., 1991). This latter design approach attempts to minimize the direct ion bombardment of the surfaces. Here the active species formed in the plasma are swept through the chamber and across the wafers by a flowing carrier gas stream. A multitude of other competing variables exist in the plasma system and process: the gas-phase composition, chamber materials, biasing of the substrates, ion damage thresholds for the substrate materials, as well as sputtering of the chamber materials. All of these system variables contribute to variations in the etching rates. Etch rates and profiles are strongly influenced by the pressure of the chamber, the gas chemistry, and even the slightest trace of contaminants in the etching chamber. Sputtering is the process of physically “blasting” atoms from the surface by atomic interactions. Typical sputtering systems have a source of energetic ions created by a DC or AC plasma in a diode configuration. The sputtering rates are controlled by the pressure, gas mixture, current, and voltage in the system. Argon ions are a preferred species as the gas is available relatively pure, is readily ionized, and the ion is massive. Charge separation in the plasma causes the argon ions to be attracted to the negatively charged (wafer) electrode. The ion impact sputters away the surface layers. Sputtering is carried out in relatively small volume chambers with a small spacing between the plates (- 10 cm). These systems are operated at total pressures of to 1 Torr (0.13-133 N mP2). With a small chamber and close proximity of the plates, continuous redeposition may occur as it is difficult to extract the sputtered material rapidly from the center of the chamber. Contamination of the semiconductor material

541

can occur by redeposition and decomposition of the chamber materials, and by implantation by ion bombardment at the surface. “Passivation” of the surface or redeposition may slow the etching process by interfering with the sputtering rates of the desired species and create nonuniform etching profiles over the wafer surface. Etch masking must be quite robust to withstand the continuous ion bombardment in sputtering or plasma processes. Thick photoresist (PR) layers or multiple PR/metal layers may be used to resist the ion flux. A balance of etching rates between the mask materials and the semiconductor is generally the best achievable compromise in practice. Metal layers etch substantially more slowly than the semiconductor or photoresists. Thus relatively thin metal masking layers may be used to assist pattern definition, permitting very fine features to be created. Etch feature side wall definition is generally poorer with sputtering processes relative to other approaches. The high wall angles desired for deep trenching (isolation) cannot be achieved easily by sputtering, due to the limited interaction of the ions with the surface at high incident angles and the high probability of redeposition within the trench. RIE-type etching in much better suited to large-aspect-ratio etched structures. RIE/RIBE/PE processes operate at low pressures, in the range Torr (0.13-0.00 13 N m-*). RIE/RIBE chambers have relatively large electrode spacings, and lower energies (smaller potentials) are impressed, providing a cleaner environment for the etching process and somewhat reduced redeposition rates. The strongly enhanced etching comes from the reactivity of the ions rather than the energy imparted to the etchant species. Unlike plasma etching where the low-energy plasma consists of ions, radicals, and various electrons, pro-

542

10 Compound Semiconductor Device Processing

tons, etc., an ion source ( R E ) or directed ion beam (RIBE) creates a selected set of ionized species to affect the etching. These systems exhibit somewhat slower etching rates than those of sputtering processes, predominantly due to the limitations of the ion sources. Plasma etching tends to be isotropic, whereas RIE and RIBE can be used to control the etched morphology and have very limited sputter damage and redeposition. The latter two points are very critical i n device structures that incorporate field effects for charge modulation (FET-type devices and lightly-doped structures. for example). PE operates at higher pressures than RIE/RIBE, with relatively low power, and etches at moderately low rates. While there is less surface damage created than with sputtering, PE still embodies a significant amount of damage and contamination from the plasma and chamber components. Operating at higher potentials generally leads to greater anisotropy in the etching, but greater damage to the surface due to implantation processes. RIE/RIBE carried out at higher bias voltages can produce near-vertical side walls due to impingement near 90". In RIE/RIBE the etching is caused predominantly by the reactive species rather than all of the particles i n the plasma, as i n PE . The ion source in RIE/RIBE provides a reactive ionized species containing a group VI1 (chlorine. fluorine, or bromine) atom or molecule. For most 111-V materials, the chlorine and bromine compounds produce highly volatile reactants and are therefore preferred over the fluorine compounds (Burton et al.. 1983: Ibbotson et al., 1983). Polymer formation is a concern with any of these compounds, particularly in the presence of photoresists. The objective is to provide selected, low-energy, reactive ions to t h e surface of the wafer where upon they

form volatile complexes with the surface atoms. This volatility limits redeposition as the complexes and compounds do not readily decompose or attach themselves to the surface of the wafer. A variety of halogenated compounds have been used as reactive ion sources: CF,, CCl,, BCl,, CBr,, or other chloro-fluoro carbons. CBr,Cl,, CHCl,, and CJl, have been found to readily form polymeric compounds and by-products, and are generally unsuitable for RIE/RIBE. Construction materials (chamber walls, shields, electrodes, etc.) for RIE/RIBE systems are of critical importance as the reactive species may cause the system components to decompose and contaminate the wafers. RIBE is differentiated from RIE by the use of collimation to create a directed beam of extracted ions from a high-density plasma source. This beam-like ion stream permits variation of the angle of incidence to the surface, thereby affecting the etching rates and morphology (Ide et al., 1992). Surface reactivity is not dependent on the incident angle to the first order, and therefore the side wall angle can be affected through the angle of incidence. The ability to control the interaction of the ions with the surface mitigates the problems of morphology control independent of the ion energy. RIE/RIBE are carried out in a parallel plate system, selecting the reacting ions by gas injection or ion extraction, under appropriate bias conditions. Etching occurs by chemical reaction and subsequent desorption of the reactants. The ability to create nearly vertical side walls at moderate bias voltages is a distinct advantage of RIBE. As with all plasma systems, RIE/RIBE etch rates are influenced by pressure, gas mixture. ion density, and excitation power. Problems may occur with polymerization between certain etchant gases and the reactant species, which can inhibit the etching.

10.6 Ohmic Contacts

543

Figure 10-29. A schematic illustration of an ECR-plasma etching system. The ion plasma, containing a strongly reactive species, is generated by exciting electron-cyclotron resonance of the desired chemical species. The source is located “upstream” from the etching chamber to protect the wafer from direct ion bombardment. A carrier or ballasting gas flows through the ion source and the chamber, assisting in the transport of reactive ions to the wafer. Electronic extraction may be used to pull ions from the source. Rotation or heating may be used to enhance or control the uniformity and rate of the etching process. Exhaust treatment is generally required to handle toxic by-products in compound semiconductor processing.

RIE/RIBE are significantly better than sputtering techniques for most applications, having lower damage due to the lower ion energies and reduced contamination (with proper chamber construction). Electron-cyclotron resonance etching (ECRE) processes involve the selective excitation of an ionized species through a high frequency resonant coupling process (Pearton et al., 1991). Figure 10-29 schematically outlines an ECRE configuration. The excited ions are typically created well away (“upstream”) from the etching chamber to minimize direct ion bombardment damage to the wafer. Ions are extracted from the ECR source by the electric fields and the pressure gradient in the system: The etching processes occur in a manner similar to RIE/RIBE. ECRE has the advantages of “clean” etching as it is carried out in a high or ultra-high vacuum environment, gives very minimal surface damage (with low to moderate extraction/acclerationpotentials), negligible redeposition, and reasonable etch rates (Pearton et al., 1991).

Run-to-run reproducibility is somewhat difficult to control in plasma techniques as there is no convenient and accurate method for monitoring the etching rate. Control of the end point may be enhanced by the incorporation of etch-stop layers, monitoring of the reaction product generation rate, or the presence of specific reacted species (chemical indicators) in the plasma or exhaust gases. These techniques can provide adequate end point detection to determine the completion of the etching cycle. Presently, the best control parameter is tracking of the reactant species evolution by residual gas analysis, optical absorption, or similar methods to determine an end point indication. Further development and refinement of gas-phase sensors will result in greatly improved control of plasma type processes.

10.6 Ohmic Contacts Ohmic contacts provide low resistance current paths and interconnection between

544

10 Compound Semiconductor Device Processing

devices. The creation of the ohmic behavior is, and has been, a source of perpetual investigation and development activity in compound semiconductor materials (Braslau et al., 1987; Matino and Tokunuga, 1969; Schwartz, 1969; Edwards et al., 1972; Ostubo et al., 1977; Kaumanns et al., 1987). The underlying difficulty in creating an “ohmic” contact is that Schottky barriers are formed when most metals are brought into initial contact with the semiconductor surface (Schottky barriers are considered in detail in Sec. 10.7). Therefore some means of eliminating this barrier must be developed. The details of the mechanisms behind the formation of ohmic contacts are not yet fully understood in spite of more than 50 years of work [see Sharma (1981)l. From a theoret-

ical and physical standpoint an ohmic contact begins as a Schottky barrier, as shown in Fig. 10-30. The work function of the metal and semiconductor are initially offset as the Fermi energy is constant across the interface. This band offset creates a barrier to charge flow from the semiconductor to the metal, as attributed to the investigations of Schottky [see Chap. 5 in Sze (1981)], giving rise to a diode transfer characteristic. The Schottky barrier height is defined as the difference of the metal and semiconductor work functions $m-$s=

( 10-4)

As long as the quantity $B is significantly greater than zero, a barrier to charge transport exists, and the flow of charge will not

Figure 10-30. Initial formation of a Schottky barrier prior to annealing to create an ohmic contact. In a) &,is the metal work function, is the electron affinity of the semiconductor, E, is the semiconductor energy gap, and E, and E , are the conduction and valence band energies, respectively. EF is the Fermi energy and q V , is the difference between the Fermi level and relative to the vacuum level. b) As the metal is brought into contact with the semiconductor, charge is exchanged to maintain a constant Fermi energy. This creates a depletion region, W, in the semiconductor to balance the electrons in the metal. The semiconductor energy bands “bend” to reflect the charge distribution in the near-surface region. The Schottky barrier height is &, and the junction build-in potential is V,, at equilibrium (no applied bias).

Metal

Semiconductor

Schottky Barrier

EC EF

EE”

-I

Depletion Width

10.6 Ohmic Contacts

be linear with applied voltage (electric field strength), The formation of an “ohmic” contact to the semiconductor involves metallurgial reactions which create a transition from a Schottky barrier condition to a graded energy band structure with a negligible barrier height (Schwartz and Sarace, 1966; Schwartz, 1969; DiLorenzo et al., 1979). The initial formation of a depletion region (W) with the creation of a Schottky barrier is illustrated in Fig. 10-3 1. The width of this depletion region is proportional to the square root of the doping concentration (in the abrupt junction approximation) governed by the relation (Sze, 1981, Sec. 5.2)

545

conductor so that tunneling and/or field emission processes have a high probability. A model for this latter point was discussed in the light of the depletion width being substantially smaller than the depth of the degenerate layer. Thus tunneling and thermionic emission processes are facile, and the barrier to transport is negligible (Popovic, 1978). Conversely, as the doping density decreases, the depletion width increases and the metallurgical junction must be formed deeper into the semiconductor to affect an ohmic behavior. Also, since there are fewer charges available i n the semiconductor, the conductivity is reduced. All of these effects contribute to higher contact resistances for “lightly” doped materials, and make the formation of a high quality ohmic contact more difficult. There is no consensus on a precise model and understanding for the ohmic contact formation (see Sharma 1981, or Schwartz, 1969). Some investigators consider the interface to be a disordered alloy with “mobility gap” states (Peterson and Adler, 1976), while others interpret the interface as a transition from the metal through an amorphous region to the crystalline semiconductor material (Wey, 1976; Riben and Feucht, 1966). At present, resolution of these arguments remains unclear.

( 10-6)

As the doping level is increased the depletion width shrinks, the interfacial electric becomes greater, and field emisfield (Emax) sion, thermionic emission, and tunneling processes may readily occur. It is desirable to have: 1) a small @B such that k T / q is “large”, or 2) a degenerately-doped semi-

Semiconductor

-4

Depletion Width

Figure 10-31. The creation of a depletion region of width W in the surface region of an n-type semiconductor. E , is the donor energy level relative to the conduction band edge, &, E,, E,, E,, and E , have their usual meanings. V,, is the built-in potential. The depletion width is inversely proportional to the carrier density as in Eq. (10-5).

546

10 Compound Semiconductor Device Processing

Further investigations may some day shed light on the exact phenomena. For a more detailed theoretical development of ohmic contact electrical behavior see, for example, Chap. 5 in the book by Sze (1981). To eliminate the Schottky barrier and produce an ohmic behavior, a metal contact material must generally be alloyed into the semiconductor. The metal reacts with the semiconductor forming multiphase intermetallic compounds, lowering the barrier potential. and stretching the band-bending

into the semiconductor, as illustrated in Fig. 10-32. Electron (or hole) flow is impeded less and less as the alloying process advances. If the condition (10-7)

is met for an n-type semiconductor material, then the contact is considered to be ohmic in nature. For small positive values of @ B (a small Schottky barrier height), significant tunneling and thermionic emission can occur permitting significant current flow with

Figure 10-32. Creation of an "ohmic" contact to a semiconductor. In a ) the barrier height, &,, is very small, presenting a negligible barrier to electron flow. &,.E,, E,, E,, E,, and E, have their usual meanings. In b) the surface region of the semiconductor is doped to an n* degenerate condition (high electron density, Fermi level in the conduction band). The depletion width ia dramatically narrowed. Thus tunneling processes may readily occur Both of thehe processes may contribute to the ohmic behavior.

10.6 Ohmic Contacts

a small forward bias. Thus only a very small resistive component is realized. Surface states and surface charge may also affect the barrier height and charge distribution in the semiconductor, and therefore the I- V behavior (Spicer et al., 1989). This latter point is particularly important for devices which are lightly doped (“enhancement mode”) and therefore very sensitive to changes in near-surface depletion or the accumulation of charge. The contact resistance (R,) is derived from the thermionic I- V theory for an ideal Schottky contact. The definition of R, is

R,=- n k T

at V = O

( 10-8)

94at

A plot of log I vs. V should result in a straight line of slope q / ( n k T) where n is the ideality factor from Schottky junction theory, k is the Boltzmann constant, q is the elementary charge, Tis the temperature, and I,,, is the reverse bias saturation current. Typically, n is in the range 1.0-1.1 for a good ohmic contact; values very near 1.O are most desirable. Values of n greater than 1.1 indicate problems with the alloying cycle, the contact metallurgy, or highly resistive materials. A critical feature of the ohmic contact is the linearity of the I- V relationship: any diode-like characteristics are undesirable. Contact metals must be deposited on clean surfaces to prevent erratic intermixing of the metal and semiconductor during alloying, particularly with reactive species such as aluminum or titanium. Typically, at least one of the components of the metallization is a donor (e.g., Si, Ge, Sn,Se, or Te in ntype, III-V compounds) or an acceptor (e.g., Zn, Cd, Be, or Mg in p-type materials) species in the host semiconductor. This will greatly increase the ease of ohmic contact formation as the effective doping density can create a highly degenerate layer i n the

547

interfacial region of the metal and semiconductor. The alloying process causes intermixing of the metal, the doping species, and the semiconductor, as discussed above. However, many considerations arise in the process of alloying: chemical reactivity or inertness with the host semiconductor, diffusivity of the various species, the phase diagram for multi-component systems, surface tension, processing limitations (thermal and morphological) from previous steps, adhesion, defining geometry (masking), stability of the intermetallic phases, compatibility with the wire bonding metallurgy, etc. The phase diagram and the kinetics of the intermixing process determine, to a large extent, the achievable barrier reduction and thus the conductivities of the interfacial metallic region. It is desired that the contact resistance be as low as possible, typically in the range of 1o-’ to R cm2 for n-type materials, and about ten times larger for p-type materials principally due to mobility differences. The range of interactions generate a large number of compromises in the development of a viable, manufacturable, and stable ohmic contact formation process. The fabrication of ohmic contacts begins with careful surface preparation, followed by deposition of metal(s) and/or metal alloys. There are a multitude of methods and metallurgical systems suitable for the formation of ohmic contacts to III-V compounds (Sharma, 198 1; Schwartz, 1969; Palmstrom and Morgan, 1985). Table 10-5 highlights a number of these metals systems; numerous other alloys have been evaluated. Predominantly, metallurgical systems based on Au-Ge, and more typically Au-Ge-Ni, are the most studied and in general use. For additional information see Sharma (198 l), Howes and Morgans (1985, Chap. 6), Williams (1990, Chap. 1 I ) , and the associated references therein.

548

10 Compound Semiconductor Device Processing

Table 10-5. Ohmic metallizations Metallization

Semiconductor tY Pe

Reference

In Sn

Au-In

n n

Wronski ( 1969) Schuartz and Sarace (1966) Paola (1970) Henshall (1977) f*ckuta et al (1976) Shih dnd Blurn (19721, Kuan et al (1983) Matino and Tokunaga (1969) Shih and Blurn (1972) Ishihara et al (1967) Matino and Tokunaga (1969)

Au-Sn Au-Ge Au-Ge-Ni Ap-In AI Ag-Znn In-Zn

n n

n. P n

P P

Evaporation methods are particularly useful for multi-component metallizations. While heating of the substrate material must be carefully controlled through the deposition rate and intentional heating or cooling of the wafer, control of the thickness and deposition rate are very good. Compositions can be controlled either through multiple deposition steps, co-deposition, or the use of alloys as charge materials. Sputtering and plating-type processes can also be used to deposit the metal on the semiconductor, although plating is rarely implemented for top surface metallizations in practice. Sputtering methods generally have lower deposition rates, can generate substantial damage in the semiconductor, and thickness control is indirect and difficult. On the other hand, sputter damage to the interfacial region may lead to lower contact resistance through the creation of defect states and disorder at the surface. Plating processes rapidly build up layer thicknesses, but tend to be rather “dirty” from the chemical standpoint, and have problems in relation to control of the surface morphology and layer thicknesses. In some processes, such as backside ohmic metallization of bonding pad formation,

where metal thickness control is relaxed but thick layers are desired, plating processes are the method of choice. Ohmic contact topology may be defined by standard photolithographic patterning methods after deposition (see Chap. 4 of this Volume). Liftoff patterning, photoresist or dielectric assisted, is the most common method for the removal of unwanted metal (see Sec. 10.1 1.2), provided the deposition process has not created a completely uniform layer of metal over the photoresist or dielectric surface topology. Ion milling may be employed for patterning gold or goldbearing alloys, or tungsten-based contact materials. Aluminum and other non-gold bearing metallizations may be patterned by dry etching methods such as RIE (as discussed in Sec. 10.5.2). The annealing of most ohmic metallizations used in device fabrication is a very critical step. “Spiking” and other deviations from planarity can occur even with mild over-alloying (Le., excessively high temperatures of extended alloy time), making subsequent processing more difficult (Gyulai et al., 1971; Zeng and Chung, 1982; Palmstrom et al., 1978; Miller, 1980). Spiking of the contact metal in the compound semiconductor systems is quite similar to that observed in the A1 : Si system at edges of contact windows. Lateral spreading has a negative impact on electric field distributions and may cause short-circuiting in fine geometries [see Goronkin et al. (1989)l. Roughness or texturing in the contact region is apparent after alloying especially if “overalloying” has occurred. Even 20-30°C overtemperatures (in the range of -400°C for NiGeAu-based contacts to GaAs materials) or slightly extended cycle times can cause the metals to “punch through” active layers, as shown schematically in Fig. 10-33. Lateral spread of the contact materials may lead to uncontrolled electrical behavior in active

10.6 Ohmic Contacts

549

Figure 10-33. Schematic representation of annealing effects on Ni-Au-Ge contacts to GaAs. In a) the metal regions have been deposited and defined by lithography. I n b) the material has been annealed. The angular structure of the NiAs(Ge) crystal structure, represented by the shaded region, is characteristic of the metal-semiconductor interaction during annealing. This has been observed in several TEM investigations (Zeng and Chung, 1982; Parsey, 1990). Excessive annealing will produce punch-through of the metal below the n-layer. as shown.

and passive devices, such as low breakdown voltages or leaky characteristics. Roughness of the contact sites may also negatively impact subsequent mask alignment, photoresist depositions, and other processing steps. A minimal thermal budget is typically used for alloying processes employing a furnace, “hot plate”, or rapid thermal annealing (RTA) system. The objective is to minimize the metallurgical interaction while maximizing the conductivity of the alloyedcontact region. For n-type materials, using gold-based metallurgy, the alloying process is carried out at relatively low temperatures -400°C) and short times (of the order of tens of seconds to 10 min), or in RTA systems with somewhat higher temperatures (- 500 “ C ) but shorter durations (ca. 30 s) the contact metallurgy is controlled sufficiently to create a reproducible, low-re-

sistance contact to the n-type materials [see Sec. V in Sharma (1981)l. Similarly, the Au-In and Au-Zn alloy families are commonly used for contacts to p-type materials. Owing to the lower carrier mobility, and thus the higher resistivity of p-type materials, a higher doping level is required to achieve low contact resistance (doping levels are usually greater than cm-3) to achieve a highly degenerate region. Even with high doping concentrations, contacts to p-type semiconductors are always of higher resistance than those to n-type materials. It is possible to form “nonalloyed” ohmic contacts to GaAs and other compound semiconductors provided sufficiently high doping concentrations exist in the surface layers, Typically, electron densities greater than 3 - 5 x 1019 cm-3 are necessary for a low resistance, nonalloyed contact to n-type

550

10 Compound Semiconductor Device Processing

ily via tunneling and thermalization processes, as well as requiring only minimal electric fields to drift the charges across the metallurgial junction. Detailed analyses of the ohmic contact and interfacial reactions have been made by numerous techniques, among them, X-ray diffraction (Ogawa, 1988), Auger electron spectroscopy (Robinson, 1975), transmission electron microscopy (Kuan et al., 1983), scanning electron microscopy (Robinson, 1975), and secondary ion mass spectroscopy (Palmstrom et al., 1978). The information obtained has led to a detailed understanding of the interactions and con-

material (Chang et al., 1971). If the semiconductor bandgap energy is small or can be reduced, for example, by the addition of an alloy component. e.g., In in In,Ga,As, the formation of nonalloyed contacts is facile. The use of In, sGa, ,As as a low resistance contact to HBT devices has attracted significant interest (Poulton et al., 1994; Huang et al., 1993). Keys to creating this type of contact are: 1) the relatively small bandgap of In, sGao ,As (approx. 0.8 eV): 2 ) the degeneracy of the semiconductor (high surface doping concentration); 3) the formation of an extremely thin depletion region (< 10 nm) at the surface. Charge flows eas-

Weight P e r c e n t Gallium 0

1208-1

. . ..

.., . . . . . . . . .,

. .'. .

90 100

, . .I

0 ¶

; 0 0 2 -

J--?0

Atomic P e r c e n t Gallium

IO0

Figure 10-34. The Au-Ga phase diagram showing atomic percent (left figure) and weight percent (right figure) relationships. Numerous intermetallic phases can form in the temperature range -274°C to -491 "C, which can greatly affect the morphological and electrical behavior of annealed contacts (after Massalski, 1990, p. 370). Renrinted by permission of ASM International.

10.6 Ohmic Contacts

trol of the alloy process (see Howes and Morgan, 1985, Chap. 6). A number of investigators have studied the interaction of gold and gold-alloy materials with GaAs (Zeng and Chung, 1982; Vandenberg and Kingsborn, 1980) and InGaAsP (Vandenberg et al., 1982; Vandenberg and Temkin, 1984) and found that, as predicted from the phase diagrams, numerous intermetallic compounds form and evolve during the alloying process. For example, in the reaction of gold with GaAs, formation of the Au-Ga alloys occurs with the resulting loss of arsenic from the surface, and the creation of AuGa, and AuGa; p and y intermetallic phases are created, as shown in Fig. 10-34 (Massalski, 1986, pp. 258-261).

551

Contact resistance in most ohmic contact systems has been found to increase if undesirable (high resistivity) phases form. For example, in the Ni-Au-Ge contact, if aAu : Ge or Ni-Ge are created i n significant amounts, or if excess gold diffuses into the semiconductor surface region, the contact resistance will be increased. In contrast, the contact resistance will be lower if Ni-As and the in-diffusion of germanium occurs and Au : Gaforms. Schmid-Fetzer (1988) has recently reviewed the phase relationships and predicted interactions of a large number of metals for potential contacts to GaAs. Contacting thin layers (of the order of a few tens of nanometers) is a difficult task due to the necessity to consume some of the surface

Atomic Percent Gallium

Au Figure 10-34. (continued).

Weight P e r c e n t Gallium

552

10 Compound Semiconductor Device P r o c e s s i n g

material. to form the correct phase(s), and the complication of uncontrolled in-diffusion processes due to surface defect formation. The varied and rapid diffusivity of the various component metals also complicates control of the alloying to very thin layers. Optimum thicknesses of n+ or p+ contact layers appear to be in the range of 25-50 nm.

10.7 Schottky Barriers and Gates A Schottky barrier is the rectifying contact which forms when a metal is brought into contact with a semiconductor material. This structure is a charge dipole which creates a depletion region analogous to a p-n junction diode. Schottky barriers are the heart of most FET-type devices. The charge flow in the transistor is modulated by the bias applied to the Schottky barrier gate metal during device operation. The “barrier

height”, in conjunction with the available charge density, determines the threshold of the switching action and the conduction state of the device at a given bias condition. In Fig. 10-35 the formation of a Schottky barrier is illustrated. The semiconductor material and the metal possess different work functions relative to the vacuum energy levels, &, and @, , respectively. As the metal is brought into contact with the semiconductor, charge is exchanged between the materials so as to balance the chemical potential of the electrons and holes, i.e., the Fermi energy level is constant across the interface. The metal contributes - 1 electron per atom, and the semiconductor typically 1 O-‘ to electrons per atom. Charge exchange creates the dipole layer and charge equilibrium is established. As a result of the imbalance i n the charge density, a depletion region, “W”, is formed in the semiconductor.

Figure 10-35. Schematic energ) diagram of a Schottky barrier. d,,, is the metal work function, ,Y, is the electron affinity. V,, i j the built-in potential. E, is the energy gap, and E, and Ev are the conduction and valence band edges. respectibely. 6 , i s the Schottky barrier height. After a metal is placed on the semiconductor surface, charge is exchanged to equilibrate the Fermi energy ( E k ) .Since the semiconductor contains far less charge than the rneial. the donor state\ (E,) empty producing a depleted region of width W.

553

10.7 Schottky Barriers and Gates

From Fig. 10-35 the relationship

Table 10-6. Schottky barrier heights on selected compound semiconductor materials”,b.

( 10-9)

@rn-xs= 4 B

may be observed. The difference between the electron affinity of the semiconductor, and the metal work function, $,, is the In principle Schottky barrier height, each semiconductor-metal system should have a unique Schottky barrier height based upon the configuration of Fig. 10-35 (see Kahn et al., 1989). In reality, surface states, surface reconstruction, impurities, and defects may all act to “pin” the Fermi energy. Thus the barrier height values are confined to a relatively narrow range, as evident in Table 10-6. This phenomenon is the subject of intense investigation [see, for example, spicer et al. (1980), Brillson et al. (1983), and Williams (1982)], and remains unresolved at present. The current flow in a Schottky diode is described by the relationship

xs,

eB.

I = I , {exp[ q V / ( k T ) ]- 1 )

(10-10)

where q is the elementary charge, V is the applied voltage, k is the Boltzmann constant, and T is the absolute temperature. I , is the thermionic current z ~ = A *T~ exp 1-9

4B/(k~)]}

(10-1 1)

where A * is the Richardson constant, qB is the Schottky barrier height, and the other symbols have their usual meaning. From Eq. (10-9) if 4,>xS,then 4B>0 and the structure will be rectifying. Thus an ideal diode would have an infinitely large value of $ B . In practice the largest possible value for the barrier height would suffice. For further development of the Schottky barrier theory see Simmons and Taylor (1983). Typically, qB is in the range of 0.5 V to 1.4 V for most important compound semiconductor as shown in Table 10-6, clustering around 0.8 V for most metals on GaAs. The observed barrier height is related to the magnitude of the sem-

Metal

A1 Au Ag W Ti Ni Pt

Semiconductor material GaAs

AlAs

InP

GaP

ZnSe

0.80 0.90

1.20

0.52‘ 0.52 0.54 -

1.07 1.30 1.20 1.12 1.27 1.45

0.76 1.36 1.21 -

0.88

0.80 0.83d 0.77d 0.84

1.0

1.40

Values in electronvolts at 300 K; from Sze ( 1 98 I , p. 291); Sharma (1981); Waldrop (1984). a

iconductor band-gap, being about 0.5 -0.6 of E,, lower for materials with a small E,, and higher for wide gap ,materials such as Gap. For materials with small band gaps, such as InAs (0.42 eV), this factor places stringent requirements on device operation, necessitating cryogenic temperatures for viable transistor operation. The value of the Schottky barrier height does not appear to depend strongly on the metal work function, although from the physical description of the barrier formation [Eq. (10.9)] it should be directly tied to $, , The “pinning” of the Schottky barrier height noted above has been attributed to the existence of surface states at the level of -lo’* to 1013cm2. These states can arise from carbon, oxygen, surface defects, or other contaminants chemisorbed or physisorbed on the surface. Numerous interpretations have been put forth to explain these effects. Brillson et al. (1983) have considered that a finite amount of intermixing occurs during the metal deposition process rather than an idealized, atomically abrupt interface. An effective metal work function is defined which integrates the effects of defects, clusters of metal, or semiconductor

554

10 Compound Semiconductor Device Processing

species, etc. This leads to a “pinned” value for the Schottky barrier height. Spicer has postulated a “unified defect model”, depending on surface states from defects (e.g., vacancies) which gives rise to the pinning states. This behavior is discussed further by Williams (1982) and numerous theories exist for these pinning phenomena. Many investigations of the Schottky barrier phenomena have been carried out in an attempt to understand and control the interfacial charge states and the metallurgy of the metal-semiconductor junction so as to provide a stable and reproducible barrier height (Spicer et al., 1980; Pan et al., 1983; Brillson et al., 1983: Waldrop et al., 1982; Williams, 1982). While the barrier heights obtained under near-ideal conditions (e.g., invacuo cleaved surfaces) are relatively wellcharacterized, in practice, the variation induced by the processing chemistry and the materials properties requires significant efforts to provide a “reproducible” Schottky barrier height. However, the precise physical relationship of the energy gap, work function, and q3B is not fully understood. as remarked by many investigators (see review by Schmid-Fetzer, 1988). To form the Schottky-barrier gate structure, a metal (e.g., gold or aluminum) or metalloid (e.g.,WSi, WN, TiWN, etc.) is deposited onto the CS surface and then patterned by standard photolithographic-etching processes. The demands of the fabrication process sequence place constraints on the formation of Schottky-barrier gates: the required thermal and patterning processes determine the permissible gate metallurgy. It is necessary to contend also with adhesion between the gate material and the semiconductor and the impact of subsequent processing steps on the chemical reactivity and stability of the metal-semiconductor system. Therefore the selection of suitable metals and metal alloys becomes relatively

limited (see Table 10-6). These materials may be used in combination to improve properties such as the electrical resistivity, but the barrier height is determined by the metal or metal alloy in contact with the semiconductor surface. The primary metal deposition methods are sputtering and evaporation. As in any deposition process, the surface and the material to be deposited must be extremely clean to prevent uncontrolled interfacial reactions or the creation of metal-insulator-semiconductor (MIS) structures. For most of the refractory metals, their melting points are sufficiently high that sputtering is the only viable deposition method; electron beam evaporation for these materials is either impractical or the deposition process will raise the temperature of semiconductor surface too high to prevent chemical interactions. On the other hand, sputtering readily creates surface damage and thus creates surface states (see Sec. 10.6). As previously noted, the formation of a Schottky barrier is extremely sensitive to the interfacial density-of-states. The corresponding variability in the barrier height, locally or globally, will affect the transistor threshold voltage, operating conditions, and reproducibility. Many of the metallurgical systems presented in Table 10-6, particularly in the case of refractory metals, may create significant stresses during deposition and fabrication, and also during device operation due to a mismatch in the lattice parameters, atomic configurations, and the existence of thermal expansion coefficient mismatch. These phenomena give rise to piezoelectric-type effects, and consequently, the transistor threshold voltage may shift. For example, the grain structure of a Schottky-barrier metallization, as deposited by various methods, is strongly dependent on the deposition rate and the deposition conditions (e.g., vacuum, plasma composition, target materials,

10.7 Schottky Barriers and Gates

etc.). Thus variations in $B may be anticipated. The microscopic details of the grain structure may also affect the gate metal resistivity and the susceptibility to electromigration at high current densities or high temperatures. These issues must be carefully addressed to achieve a stable Schottky barrier process. If the device fabrication process is carried out at relatively low temperatures, gate materials such as Ti-Pt-Au may be utilized (Wadaetal., 1989; Brownetal., 1989).Gold suffers from relatively poor adhesion to most compound semiconductors and also rapidly diffuses in most compound materials, even at low temperatures (ca. 250400”C), as does platinum. Thus there is a need to capitalize on the conductivity of gold, while maintaining process integrity. The Ti-Pt-Au system is commonly used for gate metals on GaAs. In this case, the titanium is used as an “adhesion promoter”. The platinum layer serves as a diffusion barrier to prevent the gold from reacting with the titanium (see Massalski, 1986, pp. 298299) and subsequent gold-spiking into the GaAs (Goronkin et al., 1989). Palladium may be substituted for platinum with similar results. The gold provides a very low resistance path to support a high density current flow. As these metals are relatively compatible from a thermal expansion standpoint there are only small interlayer stresses, and little driving force for intermixing at

555

temperatures below ca. 600 “C, thereby producing a thermodynamically stable contact structure. For fabrication processes that employ nonalloyed or nonannealed contacts, aluminum, titanium, and tantalum have been found to be stable at temperatures up to 300°C. These materials can be used i n the gate structure provided temperatures in subsequent process steps do not exceed roughly 200-250°C and operating temperatures are limited to less than 125-200°C. For devices which utilize an ion implantation and anneal step subsequent to the gate metal deposition (see Secs. 10.3 and 10.1l ) , the gate material must be stable at temperatures at least as high as the annealing temperature, typically in the range of 800 “C to 1000 “C. Self-aligned processes, such as the generalized approach shown in Fig. 10-36, require the use of ion implantation and annealing for defining the gate and channel regions. Several approaches exist for creating the self-aligned gate, among them, the selfaligned implantation for n+ layer technology (SAINT) (Yamasaki et al., 1982) and the self-aligned refractory gate integrated circuit process (SARGIC) (DautremontSmith et al., 1990; Dick et al., 1989). Any variation on this type of technology relies on the existence of a stable Schottkybarrier gate metallurgy. Typically, for selfaligned structures the gate material is a refractory or noble metal such as tungsten (Sze, 1981, p. 290), platinum (Fontaine et

Figure 10-36. Schematic flow of a “self-aligned” process wherein the gate metal layer is used to protect the FET channel from ion implantation and processing damage. Steps 1 and 2 define the channel and gate, step 3 is the self-aligning step. Step 4 provides the device isolation. Steps 5 to 8 define the ohmic contacts, first and second level interconnections, and passivation protection.

556

10 Compound Semiconductor Device Processing

2) Gate metal deposition, Photolithography,Etching or liftoff to define gate

3) N'ion implantation,Anneal

4) Photolithgraphy,Isolation ion implantation

5 ) Photolithography,Ohmic metal deposition, Littoff or etching, Alloying

Figure 10-36. (continued)

10.7 Schottky Barriers and Gates 6) Dielectric deposition,Via etch, Interconnect metal deposition, Patterning

7) Dielectric deposition, Via patterning,Metal 2 deposition, Patterning

8) Passivation and Contact pad via openings

Figure 10-36. (continued).

557

558

10 Compound Semiconductor Device Processing

al., 1983; Sinha and Poate. 1974), Titanium (Matino), or an alloy or bi-layer such as WSi (Dautremont-Smith et al., 1990) W-N (Kikauraet al., 1988),Ti-W-N (Sadleret al., 1989). W-A1 (Inokuchi et al., 1987j, or other similar combinations. These types of Schottky barrier material are relatively stable at high temperatures and exhibit only very limited reactivity with the compound semiconductor surface. However, it has been observed that metals such as tungsten must be treated extremely carefully as layers tend to lift from the semiconductor surface at temperatures above 400-500°C due to thermal expansion mismatch (the ratio of thermal expansion coefficients is greater than 10: 1). Also. all Ti-based gate structures can exhibit “gate sinking” under high stress operation. In this case. the metallurgical junction diffuses into the semiconductor and alters the electrical performance over time. Multi-layer metal-metalloid structures may be deposited to significantly reduce the electrical resistivity of the gate structure. For example, gold over W-Si, gold over TaSi, or tungsten over w-Si. Use of these layered structures is particularly important for device performance as silicide or refractory materials have a much higher resistivity than gold or gold-based alloys. Thus the current carrying capabilities are significantly lower. Electromigration and thermally-induced grain modification may also occur if the current densities are driven above lo5 A cm-? depending on the metals system (Irvin and Loya 1978; Irvin, 1982; Oates and Barr, 1994). Localized heating can occur in a resistive gate structure. thereby upsetting the device operating characteristics and accelerating the degradation processes (see Irvin and Loya, 1978; Irvin, 1982. and references therein). The use of such “bi-layer” or T-gate structures substantially enhances the current car-

rying capability (Maeda et al., 1988) and increases the operating speed of a transistor by lowering the gate RC time constant (Brech et al., 1997). A low-resistance gate is crucial to the performance of devices with submicrometer gate lengths, as the advantages of the small transit time through the gate region can be completely offset by the performance losses incurred from the RC effects of a high resistivity gate stripe. A gate structure known as the “T-gate” or “mushroom-gate” (Yuen et al., 1988; Beaubien, 1992; Wada et al., 1997; Thiede et al., 1998; Pobanz et al., 1998) can be utilized to further reduce the resistance of the refractory of high-resistivity gate structure while maintaining a very small effective gate length. The T-gate configuration is formed by deliberately undercutting the Schottky barrier material beneath the top metallization layer, or by providing a photoresist or other sacrificial layer to shape the top metallization during deposition following the definition of the fine gate feature on the surface. This undercut structure is also useful for self-aligned ion implanted processes to prevent the implanted ions from encroaching on the channel region. In cross section the gate has a T-shape with the current being carried predominantly in the low-resistivity top metal layer, as shown schematically in Fig. 10-37. Here the large, low-resistance top metal extends over the higher resistance Schottky barrier material in a Tconfiguration. Figure 10-38 shows an SEM cross section of a T-gate structure. The physical gate length i n this figure is 100 nm, while the metal width of the cross is -0.5 pm. Wada et al. (1997) described a process for the fabrication of gates with dimensions of under 100 nm. Electron-beam or deep-UV lithography is required to achieve the sub-0.25 pm dimensions, whereas g-line or i-line photolithography is suitable for dimensions larger than -0.4 pm. Many “tricks”

10.7 Schottky Barriers and Gates

559

Figure 10-37. Cross-section schematic diagram of a “T-gate” structure. Numerous combinations of compatible materials may be used for this gate configuration.

Figure 10-38. SEM micrograph of a T-gate structure. The physical gate length at the semiconductor surface is - 100 nm. The width of the body is -0.5 pm. (Micrograph courtesy of Beaubien (1992).)

of interference or multiple pass exposures, intentional misalignment, multilayer resists, shadowing, etc. can be used in either process to achieve very fine gate geometries (Wanget al., 1997).Trade-offs regarding the selection of a fine-line process must be determined vis-a-vis device and process complexity, yield, process cost, and reliability. Devices fabricated with these fine features show superior high frequency performance due to the small RC time constant and a short gate length. A variation on the T-gate was proposed by Tanaka et al. (1997). Herein

they formed a “spike-gate” structure, causing a buried extension of the T-gate to provide an extremely short gate length for power applications. The key to realizing successful device performance lies in the uniformity and reproducibility of the gate formation process, coupled intimately with the materials properties (thickness x doping product, charge profile, charge density, heterostructure etc.). Step and repeat lithographic systems can create minimum dimensions typically in the range of 0.25-0.5 pm in production environments. G-line (dimensions - 0.5 pm), I-line (dimensions -0.25 pm), deep U V (- 0.15 pm), image reversal processes, or Xray flood exposure can be used to photolithographically define the fine features. FiveX or ten-X projection systems permit the writing of finer features than one-to-one projectors or contact aligners. Electron beam methods are capable of achieving 0.1 pm line widths and can perform near this level in a low-to-modest volume production environment, the trade-off being that the systems are relatively slow, expensive, and limited to gate level exposures at the present time. As designers continue to push for higher frequency performance and device dimensions shrink, it should be recognized that processes must evolve that can work macroscopically at the near-atomic level: consider that a 0.1 pm gate stripe is only about 350 atoms wide, while GaAs sub-

560

10 Compound Semiconductor Device Processing

strates are 100 mm in diameter, 150 mm substrates have entered production, and typical print fields i n a step-and-repeat camera are 15-20 rnm by 15-20 mrn.

10.8 Annealing Annealing processes are required for activating ion implanted species, passivating surfaces and electrically active defects, and relieving stresses between layers of dissimilar materials. The underlying principle is to induce controlled atomic exchange within the wafer by thermal excitation. There are two basic approaches to this process: fur-

Time(min.)

nace annealing (FA) and rapid thermal annealing (RTA). The two configurations are illustrated schematically in Figs. 10-39 and 10-40, respectively. Furnace annealing tends to be less stressful to the wafer as the rate of change of temperature is relatively slow, while the time at high temperature is relatively long. In RTA the object is to provide a rapidly changing, high peak temperature condition (typically hundreds of degrees higher than that in FA) to effect atomic level rearrangement in a very short time span. The drawback of RTA is the stress induced by rapid heating: the short time tends to preclude uniform heating and the exposure period is generally insufficient for ther-

______)

Figure 10-39. A schematic diagram of a furnace annealing system. In the upper section of the figure, the time-dependence sequence is illustrated. The key issues are a relatively slow temperature rise and fall, and a lengthy time at the peak temperature. The lower half of the figure shows wafers heating parallel to the gas stream to minimize stresses due to heat retention and radiativekonductive thermal exchanges. Safety systems are mandatory for handling effluent gases when processing most 111-V or 11-VI compound semiconductor materials.

10.8 Annealing

TMaX

56 1

Typical Maximum Temperatures -700-10OO0C 5-60 sec typical

Heating and cooling rates in the range -1 0 to 100’s of degrees per minute Room Temp Time(sec)

Figure 10-40. A schematic diagram of a rapid thermal annealing (RTA) system. In the upper section of the figure, the time-temperature sequence is illustrated. The key issues are a relatively rapid temperature rise and fall, and a relatively short time at the peak temperature. The lower half of the figure shows a wafer constrained between a graphite (or other material) susceptor. This configuration, typical of present commercial systems, can process one wafer at a time. The susceptor acts to supply heat uniformly to the wafer to prevent slip and s t r e w and to slow the actual rates of heating and cooling. Exhaust gases must be treated by combustion or scrubbing for safety.

mal equilibration. The primary difference between these approaches is the nature of diffusion and redistribution of the impurities and defects behavior) due to the different time- temperature cycles. Annealing may be used for repairing the minor atomic displacements associated with ion implantation without causing the recovery of the gross displacement damage, as required for isolation processes: or, with a larger thermal budget, cause the ion im-

planted species to site select (activate) and occupy a substitutional position in the lattice while simultaneously recovering nearly all of the atomic displacement damage: and also, for strain-relieving multi-layer materials structures with dissimilar physical properties, as are found in all integrated circuit fabrication sequences. Passivation may be realized through the “healing” of surface defects, the consolidation of deposited films, and the in-/out-diffusion of mobile

562

10 Compound Semiconductor Device Processing

species such as hydrogen (Pearton and Caruso, 1989). Annealing may be carried out using a variety of heat sources such as stripheaters (Banerjee and Bakar. 1985), furnace-based processes (Woodall et al., 1981; Shigetomi and Matsumaro, 1983; Hiramoto et al., 1985), and RTA methods using lasers (Tsukada et al., 1983), rapid-cycling high intensity heat lamps (various types of IR generators) (Chan and Lin, 1986; Crist and Look, 1990), or arc sources (TabatabaieAlavi et al.. 1983). The processes discussed here involve relatively high temperatures; low-temperature alloying and annealing processes are discussed relative to the formation of ohmic contacts i n Sec. 10.6. On comparing FA and RTA methods, one finds the net thermal budgets to be significantly different. As an example, a furnace anneal cycle at 850" C for 20 min is equivalent to a few seconds at 1000°C in terms of atomic diffusivities. In contrast, a typical RTA cycle may last only 5 or 10 s at 1000°C. During FA, the metastable defects and slightly displaced atoms relax during the heating cycle. While at temperature, longer range interactions take place, and site exchange and diffusion occur. During cooling, more active species continue to move slightly as the wafer returns to room temperature. The surface temperature achieved during RTA processes is not well-characterized as the heat sources (e.g., heat lamps) are operating many hundreds of degrees higher than the actual wafer temperature. Heat is being conducted and re-radiated from the surface region in a very dynamic condition. Also. the wafer topology may be very nonuniform: patterned layers of dielectric, metal, and semiconductor may be exposed, all of which have radically differing thermal and radiative properties. Thus strongly inhom*ogeneous thermal gradients are created in the wafer. It is the increased kinetic energy at

the higher temperature that allows for very rapid atomic exchange and thus for rapid recovery of lattice damage and impurity site selection. Since the time at elevated temperature is so short in the RTA process, typical dopant species diffuse distances of the order of a few nanometers rather than tens or hundreds of nanometers in the case of FA. When a substrate is annealed after ion implantation, the donor and acceptor impurities generally become substitutional in the lattice and charge is provided to the semiconductor. The net amount of charge depends on l ) the number of donor or acceptor species present; 2) site selection probabilities (interstitialcy, autocompensation effects, the ionization state in the lattice), and 3) the degree of lattice recovery (point defect concentrations). For example, n-type regions with electron densities as high as 5 x l O I 9 cm-3 have been created using very high dose implants (- 1015cmP2) and laser RTA techniques (Liu et al., 1980); p-type materials with hole densities up to 7 x lOI9 cm-3 have been formed using pulsed laser annealing (Kular et al., 1978). With furnace annealing processes, the peak charge densities achieved are somewhat lower than those obtained in RTA due to the quasi-equilibrium nature of the furnace anneal process. Typically, maximum n-type and p-type carrier concentrations of 3-5 x 1 0 ' ~cm-3, and 1-2 x l o i 9 cmP3,respectively, are realized i n GaAs with furnace annealing processes. Much effort has been expended in understanding and controlling the annealing process i n compound semiconductors, building on the experience developed in silicon wafer fabrication. Owing to the volatility of the group 11, V, and VI species, thermal annealing of the compound semiconductors poses significant challenges. The behavior of GaAs materials under various conditions of capping and/or arsenic overpressure have been

10.8 Annealing

studied at great length with widely varying results [see, for examples, Woodall et al. (198 l ) , Banerjee and Bakar (1985), Tsukada et al. (1983) Crist and Look (1990), Asom et al. (1988), Look et al. (1986), Parsey et al. (1987)l. Site selection of impurities is affected by 1 ) the statistical nature of the atomic displacements, 2) the exchange processes that must take place to create a substitutional impurity, 3) the competing formation of point defects and defect complexes, etc. Since, i n the compound semiconductors, there are two chemically and electrically distinct lattice sites, the charge state of an impurity can be either donor-like or acceptor-like, and in the case of interstitialcy the charge state may not be well-defined. Variations in activation have been attributed to inconsistencies in substrate properties (e.g., bulk and surface layer stoichiometry, impurities, out- and in-diffusion of both defects and impurities), the efficacy of “face-to-face” vapor exchange processes, and the interaction of the capping layers with the semiconductor surface layers (e.g., stresses, interdiffusion, contamination, etc.). The annealing of compound semiconductor materials may be carried out with or without a protective cap, or a group 11, V, or VI “quasi-equilibrium” overpressure atmosphere. In general, some method for maintaining the surface integrity is required to prevent decomposition of the surface regions due to the high vapor pressures of the group 11, V, and VI species, particularly with the phosphorus- or mercury-containing materials, The surface layers of compound semiconductors are subject to incongruent decomposition during heating due to the strongly mismatched vapor pressures of the respective components, as illustrated in Fig. 10-4 1 for GaAs, Gap, and InP (Panish, 1974). The vapor pressures of the group V species may be in the range of a few Pascal to many kilo Pascal at useable annealing

563

temperatures. Surface losses must be minimized lest the surface become conducting (more metallic) in nature as the surface becomes rich in the less volatile species. This latter effect will occur in the temperature regime about and above the congruent evaporation point. For GaAs-based materials, this is in the range of - 580-620°C (Panish, 1974), and similarly, for InP 480-500°C. The group VI species tend to have lower vapor pressures than the group V elements, and thus somewhat more relaxed annealing conditions prevail for most 11- VI materials, although the same phenomena must be considered. However, in materials such as HgCdTe, the vapor pressure of mercury is extremely high and the vapors are toxic. Great care must be taken to prevent decomposition of HgCdTe and related compound semiconductors. In furnace annealing of GaAs, the initial rate of free-surface decomposition is of the order of a few monolayers per second at 500-6OO0C, depending on the heating rate, temperature, and presence of an atmosphere. In an equivalent RTA process, an uncapped surface decomposes at initial rates of tens of nanometers per second in GaAs; these rates are higher for phosphorus-containing compounds. The use of an overpressure of As, or P, vapor can reduce or prevent the decomposition by balancing the surface dissociation rate, while a cap layer will completely suppress loss of the volatiles, although diffusion into the cap or wafer surface may become an issue. “Overpressures” may be generated by heating solid sources of the host material, from elemental or compound sources, or by injection of the volatile component vapor species. Open tube or closed ampul methods have been used: practical considerations i n the processing of large diameter wafers dictate the use of “open tube” methods, although significant safety measures must be

564

10 Compound Semiconductor Device Processing 104 K/T,(Ga- As, Xn- P

-1

-2

-3 c

-m

-4

-6

- 1

-E

IO4K/T,(Ga-P)

Figure 10-41. A plot of the vapor pressures of arsenic and phosphorous over GaAs, Gap, and InP (solid). The pressure scale is in log(atm0spheres). and the temperature scales are i n 10' T-' (in Kelvin). The vapor pressures are represented as the dimeric form of arsenic and phosphorus. (This figure is reproduced from Panish (1974). Reprinted with prrmis5ion of North-Holland Publishing Co.. Copyright 1974.)

in place for most compound semiconductors (Zuleeg et al.. 1990). Furnace annealing of ion implanted GaAs is carried out typically for 20-30 min or more in the range of 700-900°C. Anneal-

ing processes carried out below about 700°C tend to be very protracted and are subject to large variation and irreproducibility (Henry, 1989-1991). Lower temperatures in the range of 500-700°C are used

10.8 Annealing

for materials containing phosphorus, and yet lower temperatures for materials in the II-VI family (ca. 200-350°C). To prevent or minimize decomposition of the surfaces, the wafers are typically capped with a nitride or oxide film (Nishi et al., 1982; Campbell et al., 1986; Mathur et al., 1985). In some processes, “face-to-face” configurations have been implemented (Woodall et al., 198l), and in others the overpressure methods are employed without capping (Henry, 1989- 1991). Complications arise in each approach: removal of the capping material is a moderately difficult process and may damage the surface layer(s); the face-to-face approach subjects the wafer to yield-reducing damage from scratching and potential cross-contamination, and the overpressure method may have system and safety constraints due to the toxicity of the materials required in compound semiconductor processing. Owing to the relative “softness” of the compound semiconductor materials, the maximum annealing temperatures and the heating and cooling rates are much more critical than those used in silicon processing. For example, GaAs wafers may readily warp when furnace annealed in a vertical configuration at 850°C and withdrawn from the furnace at a rapid rate (effective dTldt of 100- 1000°C per minute). Such warpage renders the wafer unsuitable for any further processing, as modern step-and-repeat or contact photolithography systems cannot focus on a surface with more than a few micrometers of local focal plane variation, or the wafer may fracture when brought into clamp contact with the photomask or other wafer handling tools. Annealing in a horizontal configuration has been accomplished, but consumes large areas in the furnaces, and is subject to the difficulties of maintaining a uniform and reproducible environment in a large volume. In addition,

565

stresses generated by rapid heating or cooling may create slip in the substrate, which can lead to short or open circuits after processing and facile cleavage of the water in post-process steps such as wafer thinning, back-surface metallizing, or dicing operations. The very rapid thermal cycling impressed in an RTA process makes the understanding and control of these stress-induced phenomena particularly important for maintaining wafer integrity. RTA processes, although inducing higher peak temperatures in the host wafer than furnace annealing cycles, essentially affect the same atomic-level reconstructions. RTA process conditions are typically in the range of 850- 1050°C for 10-60 s (Banerjee and Baker, 1985; Tabatabaie-Alavi et al., 1983). They key issue in the RTA cycle is that the net thermal budget for the process is smaller than of the furnace-based processes. Thus, although the atomic-level excitation is greater due to the high temperatures, the short time prevents a significant redistribution for most impurities, defects, and the host lattice atoms, and yet allows the damage and atomic displacements to recover. This latter point is the principal advantage of the RTA annealing procedure relative to the furnace-based processes. As previously noted, greater carrier concentrations can be obtained with RTA processes versus furnace annealing, an effect attributed to the nonequilibrium conditions created in RTA processes (Tiku and Duncan, 1985). Rapid thermal annealing has been investigated for several years with mixed results (Kular et al., 1978; Kasahara et al., 1979; Immorlica and Eisen, 1976; Fan et al., 1982; Arai et al., 1981; Ito et al., 1983). The successful implementation of RTA has been strongly dependent on the configuration of the annealing apparatus and the environment within the process chamber, as well as the details of the time-temperature cycle.

566

10 Compound Semiconductor Device Processing

RTA processes have been developed to anneal the wafers under atmospheres of As, ASH,, P, PH3, H2, N 2 , or Ar to mitigate surface dec o m po s i ti on e ffec t s . The d i ff i c u It i e s i n this approach lie i n developing a uniform and reproducible thermal environment in a wafer with a patterned, and possibly metallized, surface in conjunction with the necessity of maintaining the surface integrity. The low thermal diffusivity of the compound semiconductor materials contributes significantly to the creation of localized temperature gradients i n the wafer. which may be undesirable in terms of stress and electrical property uniformity. The thermal shock induced in the wafer from the extremely rapid rise or fall of the wafer temperature and stresses generated from nonuniform heating due to the varied reflective and absorptive properties of the fabricated wafer, must be carefully considered and understood for successful implementation of RTA processes. Stresses generated in annealing arise from basically two phenomena: differential thermal expansion and physico-chemical interactions. The process of depositing a metal layer may expose the wafer surface to temperatures i n excess of 1000°C in a metal evaporation system, or varying i n the hundreds of degrees for sputtering-based depositions. While the bulk of the material may not achieve this high temperature during the process. the surface layers do realize this thermal insult. Upon cooling, stresses will build up from the large differences in the thermal expansion coefficients between the metal. the semiconductor, and the other layers. such as dielectric films. Typically, this difference in expansion coefficients is of the order of 5 : 1 to 10: 1 between the different materials. If care is not taken in the annealing cycle, this differential contraction/expansion can create sufficient stress to delaminate the structure. fracture

fine features, or induce piezoelectric effects. An annealing process can also be used to relax stresses that arise from the process sequences and the incompatibilities of the multiple layers of dissimilar materials which comprise the fabrication of the device. A furnace anneal at relatively low temperatures (below 45O-50O0C), with an appropriate neutral or protective atmosphere for times ranging from a few minutes to several hours can be used to alleviate stresses. The object of this cycle is to permit some interatomic exchange and relaxation to create a transition region between the dissimilar materials. Crystal slip may occur more readily with RTA processes than furnace annealing, due to the large thermal stresses (i.e., the thermal gradients between the front and rear surfaces, the finite thermal diffusivity of the semiconductor materials, and the metal thermal conductivity, etc. (Pearton and Caruso, 1989)). Slip in the (1 10) crystal directions and dislocations can be generated in the peripheral region of the wafer, due to the large radial and axial thermal gradients enhanced by the radiative characteristics of the wafer edges. The mechanical failure and disruption of the crystal lattice leads to poor performance or failure of devices fabricated in these regions (Miyazawa et al., 1983; lshii et al., 1984; Suchet et al., 1987). Stresses induced i n the RTA process can lead to warping, delamination of dielectric layers, and damage to fine-featured components (e.g., separation of resistor films, cracking of metal traces, etc.), particularly at step edges. By careful design of the heating systems, the use of heat shields, susceptors, cover wafers, or heat spreaders, the RTA approach can be made to produce a viable wafer with minimal deleterious effects. In the deposition of dielectric materials, the chemical compositions may be adjusted to reduce the stress generated in the anneal

10.9 Dielectrics and Interlayer

and thus lead to greater resistance to the effects of thermal cycling. However, even a low-stress film may create tension or compression in the range of - lo9 to > 10” dyn cm-’ (1 O4 to > lo5 N), which is sufficient to alter the device electrical characteristics. This latter point is the result of the polar nature of compound semiconductor crystal lattices and resulting piezoelectric effects. The problem associated with such compositional variation is that the film properties are determined by the chemical make-up and may therefore be in conflict with the design requirements (e.g., the capacitance dielectric value or the isolation and standoff voltage capabilities). In the case of a dielectricover-gate stripe, stresses i n this critical area may shift the threshold voltage, which can lead to erratic circuit performance from thermal cycling effects. The metallization/ dielectric “sandwich” structures, e.g., capacitors or inductors, and multi-level metals, formed when passive components and interconnections are fabricated must also be stable to the thermal cycle. The respective materials properties and compatibility are very important if delamination or blistering resulting from excess stresses at the respective interface is to be avoided. In HBT devices, the breakdown voltage of the emitterbase or collector-base junctions may be reduced by improperly deposited dielectric layers. Interface and deep-level states may be passivated i n compound semiconductors by appropriate implantation processes (e.g., low energy protons), followed by a gentle, low-temperature annealing cycle (Pearton and Caruso, 1989). As hydrogen rapidly out-diffuses from compound semiconductors (Pearton et al., 1987), temperatures in the range of - 300-400°C must be used for the annealing process. Also, with this high diffusivity the thermal excursion and thermal budget of any subsequent process

567

steps are drastically limited if the effect of the hydrogen is to be maintained (see Sec. 10.3). Reproducibility of the annealing process in crucial in order to obtain reproducible device performance. The statistical nature of impurity site selection, and related compensation and defect formation processes, necessitates tight control of the annealing environment. If high temperature anneals are used, such as are necessary for ion implantation annealing, then considerations must be taken of the thermal history of the wafer from previous process steps, the impact on impurity and defect redistribution in subsequent processing, and the ability of the materials to withstand the additional thermal cycling. One of the conditions impressed on the fabrication sequence is that sequential steps must be carried out with continually lower thermal budgets to prevent uncontrolled reactions, undesirable phase formation, and additional in-diffusion and punch through of the junction and contact regions. Therefore, careful planning and a detailed understanding of the material’s properties and the thermodynamics and kinetics of the processes are required.

10.9 Dielectrics and Interlayer Isolation Electrical and mechanical isolation is required between the various layers of semiconductor and metals i n a device. For example, the formation of capacitors requires a dielectric material to isolate the electrode plates. In the case of an inductor the coil runners must be isolated from the substrate or any other metallizations. The formation of a capacitor is illustrated in Fig. 10-42. Typically, this structure is formed as either an n+ layer covered by a dielectric (Fig. 1042a), or as one of the first level metals cov-

568

10 Compound Semiconductor Device Processing

Figure 10-42. Schematic cross sections of capacitor structures. In a) a channel-based capacitor is illustrated. In b) the capacitor is formed from the first and second level metals, with the dielectric between them. The thickness and perfection of the dielectric layer is critical to the leakage and breakdown properties of the structure in both cases. The effective areal dimensions of the capacitor are determined by the lengths of the upper level metal pad.

ered by a dielectric, followed by an upper level metal which defines the capacitor area (Fig. 10-42b). In this application, the properties and perfection of the dielectric layer are critical to the reproducibility and yield of the capacitors. An inductor may be formed as a spiral in a single layer of metal with a bridge or via to connect the center of the coil. Stacked inductors are also possible using multiple metal layers and vias. The complexity of modern circuit designs demands multiple metallization layers to interconnect the devices and the signal transmission lines, provide for power bus routing, and to permit adequate circuit comDaction. Each of these metal layers must be

isolated with a dielectric layer. The dielectric material must possess a suitable dielectric strength and dielectric constant, uniformity of thickness and physical properties, and be deposited with a high degree of layer integrity to minimize short circuits. The dielectric layers also play a critical role in controlling the density of surface states and pinning of the Fermi level at the semiconductor surface. These properties may affect the value and control of the device thresholds in MESFET, HFET (MODFET), and MISFET-type devices fabricated on GaAs, InP, and other compound semiconductor materials [see Daembkes (1991), and articles and references therein].

10.9 Dielectrics and Interlayer

The dielectric material serves to reduce surface leakage by “tying up” dangling bonds and passivating the surfaces. A dielectric layer may also be used to protect the compound semiconductor from chemical attack and contamination during processing, and to provide mechanical protection of the surfaces. An encapsulating dielectric film may be used to prevent surface decomposition during annealing procedures. This is a crucial application in most III-V and I1 -VI compounds due to the volatility of the component species. To assist in the formation of air bridge metallizations, dielectric layers may be used to form the post-andbridge structures. Thus understanding of the dielectric material, the deposition process, and potential interactions at the interfaces are critical for achieving reproducible device characteristics. It is an unfortunate fact that the compound semiconductor materials do not have the strong, stable native oxide available in silicon technology. For example, in GaAs the native oxides Ga20, and As20, ( y = 3.5) are very weak, being readily soluble in a variety of liquids. The suboxides (Ga,O and As,O) are quite volatile at common processing temperatures. These oxides, which form rapidly in air, are one source of interfacial states as the surface bond configuration and chemistry are strongly modified by the oxidation process. The native oxides also tend to be inhom*ogeneous in their properties due to strong local variation in the chemical composition and bonding (Watanabe et al., 1979). In part, this is due to the large difference in vapor pressure and reactivity of the constituent elements. Other oxide layers, for example those formed with glycol-based solutions, have been found to be electrically inferior to most deposited dielectric materials and have therefore received little attention (Hasegawa and Hartnagel, 1976). Dissolution of the group I11 and

569

group V oxides may readily be carried out with HCl- or NH,OH-based chemistries. This is convenient for surface preparation, but emphasizes the limited utility of the native species for integrated circuit applications. Thus alternative deposited dielectric materials must be used for CS device fabrication. For most applications, the suitable dielectric materials are SiO,N,, Si,N,., and SiO,. Device performance criteria dictate the optimum value of the dielectric constant. The dielectric constant depends strongly on the chemical composition; the composition of the materials is determined by the deposition chemistry and the apparatus configuration. It should be emphasized that these materials are rarely, if ever, stoichiometric. Therefore, care must be exercised i n deposition to achieve a hom*ogeneous, uniform and low-stress film. The application of a dielectric layer embodies many compromises. Optimally, it is desirable to have a low dielectric constant for high-speed operation. The tradeoff in the use of SO,, Si,N,, and SiO,N, is the value of the dielectric constant: nitride films are best for capacitors, but the oxide is optimum for runners due to the lower dielectric constant and a resulting lower capacitance. Mixed oxy-nitride materials have dielectric constants intermediate between SiO, and Si,N,, which permits a compromise in the circuit fabrication-performance relationship. For example, the dielectric constant for SiO, ( x - 2 ) is significantly less than that of Si,N,. ( x - 3 , y-4) as shown in Table 10-7, along with other interesting dielectric materials. Alternative dielectrics have received some attention during the late 1990s for special applications. Circuit designers recognize certain advantages of “high k” dielectrics, but design and layout constraints may force impractically small dimensions, which obviate the advantages.

570

10 Compound Semiconductor Device Processing

Table 10-7. Values of dielectric constants for selected dielectrics. Material

GaAs SiO? Si,N, Poly imide Ta20, TiO: SrTiO, Ah03

Dielectric con\tant (relati\e)

Reference

13.1 1-5 5 5-1 5 -3.5 20-25 1-1- I I O 50- IO0

Sze (1981. App. HI Williams (1990. p . 295) Williams (1990. p. 295) CRC (1978) William3 (1990. p. 295) CRC ( 1978) Nish*tsuji et al. (1993) CRC ( 1986)

A lower capacitance may be realized with SiO.,, a highly desirable feature for highspeed circuits. However, much thinner SiO., dielectric layers must be deposited to achieve a given capacitance value (relative to materials with larger dielectric constants) or, alternatively, large areas of the circuit must be committed to these devices with the resulting cost increase and yield reduction. In the case of very thin layers, the integrity of the film becomes a yield-limiting factor. Most of these dielectric layers can be deposited with relatively low stresses, if the process is carried out under optimized conditions. Typical stress levels are in the range of 1O9--1O” dyn cm(10‘-106 N).Valuesof 10’ dyn cm ( 10‘ N ) or less are considered strain-free. while those above 10“’ dyn cm ( lo5 N ) can create problems with yield and reliability (layer adhesion. thermal cycling effects). Another issue with stress is the piezo-electric (PE) effects arising from the polar nature of the compound semiconductor lattice. Interlayer stresses may generate significant anisotropic threshold shifts due to the PE effects; thus the gate orientation with respect to the substrate crystallographic orientation becomes important. In Si.,N, films on GaAs, stress typically increases with increasing Si fraction. At the

same time, the dielectric film resistivity varies with the silane concentration in the deposition atmosphere, making the electrical isolation less effective, i.e., higher leakage currents may be observed. Hydrogen incorporation also increases with lower deposition temperatures. Excessive hydrogen content may cause dielectric “blistering” during subsequent high temperature processes. An optimum balance of the properties in silicon nitride materials has been obtained with “near-stoichiometric” film compositions (see Williams, 1990, Secs. 8.3.1, 13.3, and references therein). A caveat to the use of dielectric materials is the mechanical incompatibility between most such materials and the compound semiconductors. The thermal expansion coefficients of dielectric materials are typically quite different from metals or the host semiconductor. Thus deposition of the dielectric layer can increase the levels of stress during thermal excursions. Thermal cycling caused by device operation can produce failures in metallization lines and contacts from cyclic fatigue, particularly at steps and edges. This effect is illustrated schematically in Fig. 10-43. Cyclical stresses can also give rise to shifts in device characteristics arising from the PE effects in the compound semiconductor. The PE effects and the fabrication process-related phenomena. as they affect the device threshold and operation, must therefore be clearly understood to achieve proper and reliable circuit operation. The deposition of dielectric films may be carried out by a variety of techniques. Evaporation methods for dielectric material deposition are well understood but have limited applicability for compound semiconductor processing. This method suffers from exposure of the substrate to very high temperatures, dielectric composition control is very difficult. and variation in the film composi-

10.9 Dielectrics and Interlayer

571

Figure 10-43. Detail of a metal line over a dielectric step. With continued thermal cycling, the differential expansion may induce fractures and microcracking in the metal lines. Similarly, dielectric over-layers may crack due to expansion of the metals beneath. Steps and edges are most susceptible owing to the concentration of stresses.

tion occurs with time due to depletion of the various components from the source charge at varying rates. The control of stoichiometry and the materials properties are also complicated by the fact that elemental and molecular evaporation rates are very difficult to balance i n a high vacuum (HV or UHV) deposition environment. Sputtering methods may be used for deposition but surface damage can be significant unless great care is taken to optimize deposition processes. Stoichiometry is generally variable throughout the film on the microscale, which may affect the physical properties as well as the etching characteristics. Aging of the sputtering target(s) may also cause a gradual shift i n the dielectric composition and properties. Lattice damage can occur from ions and surface atoms being driven into the surface region: resputtering of surface atoms also occurs during deposition. It is critical that no low frequency (e.g., 455 kHz) excitation is implemented in these systems as the plasma will severely

damage any exposed semiconductor surface regions. Hydrogenation of the surface region is also a problem, especially with the use of silane, hydrogen, and/or ammonia feed gases. The incorporation of hydrogen in various forms alters the dielectric properties in an uncontrolled manner and produces a time-varying effect in the film, due to out-diffusion of the hydrogen species during subsequent processing, or even during device operation (Pearton et al., 1987). Standard CVD processes require relatively high deposition temperatures to drive the gas phase reactions. Typically, deposition takes place at temperatures greater than 500- 1000°C,which is incompatible with most metallizations used for ohmic contacts and interconnects. Temperatures in this range are also too high for most compound semiconductor materials: surface decomposition may occur during the deposition cycle, as the vapor pressures of the group V species, e.g., PA, and P,, for example, are significant at these processing temperatures

572

10 Compound Semiconductor Device Processing

(see Fig. 10-4 1 , and Panish ( 1984), for example). The deposition method of choice appears to be plasma-enhanced chemical vapor deposition (PECVD). This is due to the relatively low temperatures (- 175-400 “C) developed in these processes, and the enhanced controllability of the reactor systems. The plasma serves to create energetic reactive species, with the energy imparted by electrical excitation rather than direct thermalization. The plasma may be generated with DC or AC fields, in a variety of system configurations: each approach has its proponents (Gupta et al.. 1983; Tsubaki et al., 1979). In PECVD processes the pressures are Torr (0.13 N typically of the order of m-2). The excitation in the plasma imparts energies in the range of a few hundred electronvolts or less. Thus there is only minimal surface damage due to free electron or ion bombardment (Meiners, 1982). The chemically reactive species are generated at low effective temperatures with the plasma. Only a very small fraction of the available molecules are ionized by these interactions: most of the plasma is neutral and therefore relatively “cool” and unreactive. The substrate may be heated or cooled, but it is necessary to raise the substrate surface temperature to only 150-300°C for high quality deposition. The self-heating effects during deposition can raise the substrates into this temperature range; active cooling may be desirable for process reproducibility. The low temperature of this process generally allows direct monitoring of the gas-phase reactions, reaction species, and by-products by the characteristic emission or absorption energies (Havrilla et al., 1990), or analysis of the exhaust stream by RGA techniques. These type of measurements can be readily adapted to process control or end-point detertinq.

The PECVD method offers great flexibility: the dielectric density, composition, refractive index, and dielectric constant can be varied by controlling the deposition conditions. The PECVD processes can be used to create layers of AlN, Si,N,. , SiO,, Ta,O,, TiO,, and other materials. AlN appears to be a promising new material for use in GaAs and related materials. It possesses a thermal expansion coefficient well matched to GaAs, but the deposition-related damage is presently significant and the material is rather hard to remove without creating additional damage to the surface (Gamo et al., 1977). Growth rates in PECVD tend to decrease with increasing operating pressure or higher deposition temperatures, while the refractive index generally increases with a higher deposition temperature. Suitable gases for deposition and etching are reactive species: chlorines, fluorines, ammonia, silane, hydrogen, oxygen, and nitrogen-containing compounds. Noble gases such as argon may be used as diluents to moderate the deposition process. The major drawback to utilizing PECVD processing is that the process has many variables: gas pressure, chamber and substrate temperatures, flow rates, gas compositions, etching rates, the evolution of by-product materials, the electrode geometry, the excitation method (DC or RF and excitation frequency), the input power, the plasma energy density, the system configuration, substrate rotation, etc. (Gupta et al., 1983). These variables present a formidable obstacle to process development, and complicate process control. For process consistency, contamination from pumps, leakage at vacuum seals (processes are not operated in UHV conditions), chamber materials, and residual species such as Si, 0, H, C, N, etc. must be considered. As a result, a stable, robust operating condition can be difficult to achieve and sustain. Another concern in the PECVD

10.9 Dielectrics and lnterlayer

method is that deposition occurs over the entire chamber, complicating the control and stability of the process. Careful maintenance and consistent cleaning are required to maintain process integrity refully designed experimental methods‘and the application of statistical process control monitoring, a robust and reproducible process may be obtained (Havrilla et al., 1990). Barrel (or plate-type) PECVD reactor designs can be used for deposition (or etching) processes (Fig. 10-44). In a barrel reactor the electrode plates in the chamber may be neutral or floating relative to the ground potential. Various susceptor and chamber configurations are possible. Biasing the wafer plate can enhance or retard the deposition process, or alter the selectivity of the deposition. A low energy ion flux is thus created between the upper plate and the wafer surface. Local perturbations in the electric field on the wafer surface can readily deflect the incoming ions. It is generally more difficult to control an etching process on a fine scale in this type of system, due to the low ion energy and small accelerating field strength. This makes a barrel-type reactor best suited for relatively coarse processes, e.g., deposi-

573

tion of thick, noncritical layers, etching of large features, or ashing of photoresist layers, due to problems associated with localized and nonuniform electric fields on the metallized and/or patterned wafers. Controlled gas flows, critical to achieving a uniform etching process, are also difficult to maintain uniform in a barrel design due to nonuniform and nonsymmetric heating effects, convection, and generally asymmetric injection and pumping of the effluent species in commercial systems. Radial flow, rotating susceptor reactor designs have proven quite good for achieving uniform film deposition. A generalized configuration is shown in Fig. 10-45. New commercial systems, such as those developed by ElectroTechTM,or PlasmaThermTM, are capable of 1?k control of thickness over a 3”(76 mm) diameter GaAs wafer (O’Neill, 1991). In this configuration the electrode temperature can be controlled, if desired, to enhance or retard the surface reaction rate. Reactant gases and ion species are much better distributed in the radial reactors relative to the barrel-type designs which leads to improved film characteristics and thickness uniformity. In a radial reactor the plasma is

Figure 10-44. A schematic illustration of a RF-excited, barrel-type configuration for PECVD of dielectric films. The plasma above the wafer creates the active species for deposition. The energy of the excited species may be quite high and cause damage to the semiconductor surface. Susceptor rotation may be incorporated to improve uniformity. Heating and bias may be supplied to the wafers to assist deposition

574

10 Compound Semiconductor Device Processing

Figure 10-45. A Achematic illustration of a high-performance. radial flow configuration for PECVD of dielectric films. The p l a m a is generated above the wafers. creating the active species for deposition. A radial flow is set up by the injection and exhaust configuration. improving the uniformity of the deposition. As in most plasma-type sy5tems. the energy of the excited species may he quite high and cause damage to the semiconductor surface. Susceptor rotation may be incorporated to improve uniformity. Heating and bias may he supplied to the wafers to assist deposition

confined between the excitation plates, with a quenched region adjacent to the plate surfaces (space charge region). Ions are accelerated through the space charge region by the electric field and impinge on the wafer surface. Several investigators have introduced "downstream" ( indirect ) systems . wherein the plasma excitation and active species are generated "upstream" (with respect to the location of the substrates and the gas flow), well removed from the deposition region. The reactive materials are extracted from the source cell with the gas stream, and flow across the wafers. Deposition occurs on the wafer surface if the thermal conditions are appropriate. This configuration is shown in Fig. 10-46. It has been found that the use of such a downstream deposition process greatly reduces the plasma-induced ion damage in the surface regions (Meiners,

1982). A limitation to this approach is the total reactive ion current extractable from the source and the lifetime of the ionized species in the gas stream. Another approach to CVD deposition is photo-stimulated CVD. In this embodiment, a CVD chamber is fitted with windows to permit selected-wavelength light to impinge on the gases and/or the substrate. The added stimulation generates the desired species with reduced electrical energy input. The technique has advantages similar to PECVD: low deposition temperatures as well as a great selectivity for the excitation of specific molecular species by choice of the optical excitation energy (Peters, 1981). Photo-enhanced CVD induces less surface damage than the standard PECVD techniques, and by utilizing a downstream type configuration direct ion bombardment damage of the surface can be avoided.

10.9 Dielectrics and lnterlayer

575

Figure 10-46. A schematic illustration of an ECR-plasma CVD system. The plasma is generated by tuned electron-cyclotron resonance of the desired species in a cell well removed from the deposition region. A carrier gas flow or extraction potential transports the active species to the wafers. Minimal damage is imparted in the wafer in this configuration. Rotation of the wafers may be provided to improve the uniformity of the deposition. Heating or bias may be supplied to the wafers to assist deposition.

Electron-cyclotron resonance (ECR) is a relatively new method for creating a plasma while mitigating the damage induced by the ion and electron bombardment (Kondo and Nanishi, 1989; Takamori et al., 1987; Sugata et al., 1988). Here the plasma excitation is provided in the usual manner with the addition of a very high frequency RF excitation signal. Selective excitation is achieved by choosing the excitation frequency to resonate with the desired ion species cyclotron frequency. These selected ions absorb the energy and create the plasma for deposition. A relatively high excitation power is required in this approach, and therefore the downstream configuration is used for obvious reasons. Another class of dielectric materials are polyimides. These materials are polymeric organic films with relatively low dielectric constants: typical values are - 3.5. Polyimides are very stable dielectrics: some compositions are capable of tolerating exposure to temperatures greater than 500 "C (Dupont, 1976). These materials are best suited as an encapsulant or capacitor dielec-

tric, for inductor isolation, or for isolation of second (and higher) metal levels. These materials are also useable for the standoff of metal runners in air bridge configurations, although the large capacitances may present a problem at very high frequencies. Moisture absorption and swelling can be an issue with polyimide materials. Incorporation of those layers must take packaging integrity into account to ensure long term reliability. Polyimides may be deposited with dispensehpin systems, as are used for photoresist coating. The major drawbacks to the application of polyimides are: 1) the extended curing time required to drive off the solvents and crosslink the polymer chains (ca. 1 h or more at elevated temperatures), and 2) control of the thickness owing to the high viscosity of the liquid phase. Following the curing, the polyimide film can be patterned with standard photolithographic methods. However, only specific etchants and some plasmas will attack polyimide materials. They can be etched with oxygen plasmas (asher), or with strongly basic solutions. Appropriate solvents or alcohols

576

10 Compound Semiconductor Device Processing

may also be used for pattern development, but care must be taken to minimize softening or other damage to the film. One great advantage of the polyimides is their dielectric strength: typical values are - IO6 V cm-'. This property, coupled with the high dielectric constant, makes these materials very attractive for use in high voltage circuits or for achieving very fine feature sizes. In PECVD and related deposition methods, film growth rates are i n the range of 10-50 nm min-', and useful films are typically 50- 1000 nm thick. The polyimide film thickness is controlled through the fluid viscosity and the spin speed and acceleration program i n the spinner system. Very thin films (< 100 nm) can be deposited, but integrity generally suffers. All types of dielectric films can be evaluated with standard ellipsometric instruments to determined thickness and the dielectric constants. Other instruments, such as interferometers, are used to determine the compressive or tensile stress conditions in the deposited films. Pinholes or failures in the film integrity are a continual problem resulting from wafer surface contamination, the formation of large clusters or particulates i n the plasma and on the chamber surfaces, or difficult surface topology. Multiple process cycles can be used to alleviate or minimize this problem. The impact of dielectric films and surface states on the channel saturation currents (J,,J, the device threshold voltage ( Vth), and reverse breakdown voltage ( Vbr) effects are poorly understood. Sputtering of PECVD typically produce ion damage depths less than 50- 100 nm, but can have a damage depth in GaAs up to twice the expected ion range under improper deposition conditions (Williams, 1990, Chap. 9). Significant surface depletion effects occur from this damage, and can result in erratic device behavior. The surface state effects are especially

important for enhancement mode or lowcurrent devices, where the charge is very close to the gate or of low density, and thus the conducting channel is more sensitive to local perturbations in the surface electric field strength. Post-growth annealing may help stabilize the dielectric film properties by equilibrating the interface charge balance and the interfacial chemistry, and also relaxing built-in stresses (Weiss et al., 1977). All of these issues are crucial to the fabrication of high-performance, high-reliability integrated circuits in compound semiconductors, and are the subject of continuous investigation and development.

10.10 Resistors Biasing networks, feedback control, voltage and current dividers, load terminators, and balancing applications all require the use of resistors. Resistors may be formed utilizing the conducting channels (active regions) in the surface of the wafer, or constructed as separate thin film layer structures. The channel-based resistor structures may be formed using the n-layer to the n/n+ layers (ion implanted or epitaxially grown layers), as illustrated in Fig. 10-47a. This approach demands tight control of the sheet resistances in the layer(s) for a controlled resistance value. A thin film resistor is typically deposited above the first dielectric layer, as shown in Fig. 10-47b, but may be placed in any convenient location within a multi-layer metal scheme. A resistor requires a conductive stripe and at least two contacts. A channel-type structure will require some form of peripheral isolation to define the resistor body dimensions. Thus the fabrication of resistors must be carefully considered when planning the process sequence. Either a trench, mesa, or ion implantation scheme must be used to

10.10 Resistors

577

Figure 10-47. In a) a cross section of a channel-based resistor is illustrated. The effective length of the resistor is “I”. Ohmic contacts define the effective length. The width is determined by perimeter isolation [mesa or implant (shown)]. A dielectric layer is used to protect the resistor body during subsequent processing steps. Figure IO-42b illustrates a resistor structure made with a thinfilm resistor material. The layer is deposited on a dielectric as shown, and patterned by photolithographic methods. Metal contact pads are deposited and patterned on the ends of the resistor. Taps may be placed along the resistor body, if required. The effective length of this resistor is I , with the width determined by the lithography. Controlling the thickness or the chemical constituents in the film provides a high degree of control over the resistor properties.

define the body of the resistor and to isolate the contact region for channel-type resistors; deposited film resistors may be defined by photolithography and etching or lift off processes. Greater latitude is permitted for the deposited film structures built on dielectric layers, as the resistor bodies can meander over the surface (with some restrictions) without consuming valuable active area. A larger range of resistivity values is accessible to the thin process relative to the channel-type structures. The processing asso-

ciated with the resistor fabrication must not exceed the thermal constraints of the preceding processing sequences. The resistance value ( R )achieved in a resistor is defined by the relationship (10-12)

where p is the resistivity of the conducting medium, L is the length, and W is the width of the resistor body; t is the layer thickness, implant thickness (- 2 A R J , or the total ac-

578

10 Compound Semiconductor Device Processing

tive epitaxial layer thickness, 2 R, is the sum of the contact resistances, and W, is the effective contact width. A resistor structure is shown in detail i n Fig. 10-48. If multiple conducting layers are used in the resistor stripe, such as in an n+-n layer structure, Eq. (10-12) is modified to accommodate parallel conduction effects. For practical resistor structures, the contact resistance will be negligible (typically much less than one percent of the resistor value), and well within the resistor process variations. Resistors formed with the semiconductor conducting layers are relatively easy to implement. No additional mask levels are needed as the channel can be patterned with the process sequences of ohmic metallization and isolation. Typical resistivity values are in the range of 100- 1000 R/ 0 , but this range may easily be extended with additional ion implantation and annealing steps. If the resistor is isolated with a mesa etch, then additional process steps may be necessary. The topology and design rule limitations with a mesa configuration must be considered in light of subsequent process steps and consumption of semiconductor area (cost). The implementation of channel-type resistors has several drawbacks: surface depletion (surface states) can affect the charge in the resistor stripe, surface potential offsets may arise with dielectric deposition, a relatively large temperature coefficient of

resistivity exists (bandgap energy coefficient, impurity ionization, mobility effects) saturation of the current-carrying capability can occur, heating or cooling effects alter the charge density and carrier mobility, and slow domain oscillations and high frequency (Gunn-type) oscillations can arise from charge injection into the substrate. All of these effects, described below, compromise the performance of such a resistor structure. Careful layout (with respect to power distribution busses, proximity to critical nodes, etc.) is necessary to minimize interactions with the resistors and other circuit components. The realities of device fabrication manifest themselves in resistor structures in the following manner. Surface depletion can decrease the available charge in the resistor stripe, and generally leads to higher resistance values than expected. Owing to process-induced variations in the layer thicknesses, charge density, dimensional tolerances, surface states, and surface contamination effects (leakage currents), the resistance may actually increase or decrease in an uncontrolled manner. Layers of high sheet resistivity, with their correspondingly low-charge density, are more susceptible to these variations. The application of a dielectric film will tend to ameliorate the effects of surface states, but can aggravate control of the resistance owing to the generation of stress and piezoelectric effects.

Figure 10-48. Detail of a resistor structure showing the critical dimensions and features. The contact resistance is predominantly at the interface of the metal and the semiconductor. The bulk resistivity determines the dimensions of the resistor relative to the needs of the circuit design. W , is the effective contact width, W is the effective width of the resistor stripe, t is the effective thickness of the layer, and L is the effective length.

10.10 Resistors

The magnitude of these effects in subject to the dielectric film composition, surface preparation, and deposition conditions. Thermal effects must also be considered, as carrier mobilities decrease with heating (proportional to T-3’2). Thus the resistor value increases when significant power is dissipated in the circuit or the resistor. In addition, when temperatures are very high (> 100 “C), the effects of band-gap narrowing may also begin to influence the transport properties, again altering the resistivity. This behavior is of importance to the designers, as compensation networks may have to be build into the circuit to accommodate these changes in resistance. Since the resistor body in this configuration is essentially the transistor conducting channel, it is subject to the same current saturation limits as the transistors. For most compound semiconductor materials, channel saturation occurs at electric field strengths of - 1000-5000 V cm-I (Sze, 1981d, pp. 44, 325). While these effects can be mitigated by careful design and control of the voltage drop across the resistor, it presents an additional restriction for the device designer and process engineer. Attempts to exceed the saturation values will lead to excessive heating and accelerated failure. Critical field effects may arise from both DC and AC operating conditions when the resistors are biased. Above the critical field strength, charge may be injected into the regions surrounding the resistor (isolation regions or the semi-insulating substrate). Selfoscillations may then occur in the compound semiconductor material. These oscillations may be realized as “slow domains” (Ridley and Walkins, 1961; Ridley and Pratt, 1965; Kaminska et al., 1982, and Sec. 10.3.3) or high frequency, Gunn-type oscillations (Sze, 1981, Chap. 1 I). In GaAs slow domains can be created when the electric field strength exceeds roughly 500- 1000 V

579

cm-I (Kaminska et al., 1989); Gunn oscillation are created at a field strength in excess of roughly 3000 V cm-’ (see (Sze, 1981 d, Chap. 11). The oscillations will add to the dispersion in the device characteristics. A major consideration in the use of channel resistors is the heat dissipation. The thermal conductivity ( K ) of GaAs is only - 0.48 W cm-’ K-’ (EMIS, 1990, Sec. 1.8), and the thermal diffusivity is only -0.27 cm2 s (EMIS, 1990, Sec. 1.9). In InP these values are 0.56 W cm-’ K-I and - 0.4 cm2 s, respectively (EMIS, 1991, Sec. 1.8 and 1.9). Therefore care must be taken to avoid excessive local heating and thermal runaway conditions, particularly if a resistor body is adjacent to an active device. The last concern for channel-type resistors is the large distributed capacitance which arises from the depletion effects along the length of the resistor. The capacitance is of particular concern for “long” resistor stripes (high-resistance values), which can lead to intractable RC time constant problems and a significant reduction in device operating speeds. Inductive parasitics also arise with long meandering resistors, which again can limit high-frequency operation and create unexpected operating instabilities. Thin film resistors may be constructed on the semiconductor surface (with implant isolation beneath the resistor body and contact regions), or above the first or subsequent dielectric layer(s) by the deposition and patterning of thin layers of Cr, Ni-Cr (nichrome), TaN, or other materials (see Table 10-8). These resistor films have specific resistance values in the range of - 10-1000 R/O which provides a suitable range of resistor values. The deposition and patterning of these films on the semiconductor surface are subject to many of the effects that affect the channel-type structure de-

580

10 Compound Semiconductor Device Processing

value. a trimming capability (laser trimming or focused ion beam (FIB) repair), reduction of the distributed capacitance, and design and layout flexibility at the expense of an additional masking level. The thin films are typically less than 100 nm thick, and therefore have a limited impact on the topology. Evaporation and sputtering processes are the deposition methods used for resistor fabrication: plating processes are insufficiently well controlled. A caveat with these thin film structures is that continuity is strongly affected by pinholes and inhom*ogeneities in the film. Therefore, a robust, high integrity film must be produced (slow deposition rates and multiple passes are recommended). High current densities in the thin film resistor can result in electromigration problems, localized heating, and catastrophic failure, particularly at the junction of the contact pad and the resistor body. These effects are similar to electromigration failures in drain/source or gate metallizations. This failure mechanism is illustrated schematically in Fig. 10-49 (see Magistrali et al.. 1992). The adhesion of the resistor film to the semiconductor or dielectric material is a critical issue. This problem is typically surmounted by the deposition of a dielectric layer over the resistor to protect the thin film layer from damage, stresses, and confine the film. Control of the resistance value is in-

Table 10-8. Thin film resistor materials". Metal

Resistivity range

(R/O 1

Temperature coefficient (ppm K-' )

~ _ _ _

Cr TI NiCr TaN

I? 55-135

60-600 280

3000 2500 200 - 180 to -300

From Willmrn5 (1990. p 306)

scribed above. The formation of a thin film structure involves depositing a uniform layer of the resistor material, then photolithographically defining the appropriate pattern. Etching of the exposed material is carried out using plasma-etching techniques. Lift-off methods may also be implemented, using photoresist or dielectric-assisted techniques. Contact metals are then deposited on the resistor stripe as desired, patterned, and annealed to alloy the contact to the resistor body. Tapped resistor structures can be readily fabricated. These tapped resistor structures may be used for tuning high-frequency response or circuit gain characteristics, using laser ablation or current pulses to break the film at a desired 10cation. By depositing the thin film layer on the dielectric, numerous advantages are gained: relatively easy control of the resistance

Region of Failure

Material Migration Material Pile-up

Current Crowding

Figure 10-49. A schematic picture of film resistor failure. The electromigration-induced transport of material ("electron wind") causes a high resistivity region to form near one contact. Some material is transported to the oooosite end of the resistor. The loss of material creates a "hot spot" which ultimately fails catastrophically.

10.11 Metallization and Liftoff Processes

fluenced by the variations in film thickness, defined width, and film composition. Film resistors may be trimmed by laser ablation methods to “fine tune” the resistance value at the time of testing. More recently, with the advent of the FIB techniques, the resistor stripes may be repaired, or built-up, albeit this approach is presently limited to very costly circuitry. Fringing capacitance effects are minimized by the use of deposited film resistors, as the charge in the semiconductor is well removed from the resistor stripe. The dielectric constant of the dielectric layer may be optimized and a minimized capacitive coupling may be effected with a thin film structure. This can lead to significantly reduced RC time constants relative to channel-type resistors. In principle, the limit to current flow in a thin film resistor is the maximum current density supported by the material. This is constrained practically by electromigration phenomena, the heating-related effects, the materials’ temperature coefficients, and the maximum power dissipation of the resistor and substrate materials. As the dielectric materials are well behaved, there is little concern for charge injection, oscillations, and nonlinearity in the thin film structures deposited on dielectric layers even when operated at high bias levels.

10.11 Metallization and Liftoff Processes A metallic conductor is required to provide the interconnection of devices, interlevel and back-plane connections (vias), and for electrical and thermal conduction paths to the external environment. The conductor material must have the following properties: a high electrical and thermal conductivity, be electrically and mechanically stable, be chemically inert yet paternable by fabrica-

581

tion-compatible chemistries, possess good adhesion characteristics, be corrosion resistant, ductile, and compatible with the processing sequences which follow the deposition and definition steps. The key issue for metallization and interconnect processes is minimizing the electrical resistivity in runners and vias to prevent excessive power dissipation and the concomitant loss of signal, as well as the operating speed limitations due to RC time constants and heating effects, while utilizing minimal geometries. Au, Al, Ti, Ta, W, Ge, various silicides, and numerous gold-based alloy materials are compatible with most compound semiconductor processes (Howes and Morgan, 1985, Chap. 6; Williams, 1990, Chap. 11). However, to prevent undesired chemical and metallurgical reactions, many of these materials must be used i n a “multilayer” configuration, i.e., a barrier layer and high conductivity “bulk” metal(s). In addition, the interconnection metal must be stable to electromigration processes which arise at current densities above - lo5- lo6 A cm-2 (Davey and Christon, 1981; DiLorenzo and Khandelwal, 1982, p. 345; Williams, 1990, Chap. 20; Irvin, 1982). Furthermore, this stability must be maintained under highly stressful testing and operating conditions, e.g., accelerated aging, testing and operation at elevated temperatures, high bias, and high humidity. Only then can a material be called suitable for use i n compound semiconductor devices. Unlike the aluminum metallization common to silicon-based products, metallizations for CS devices must be stable for tens of thousands of hours at very high operating temperatures, ca. 200 - 250 “C. Metallization schemes are a major issue in IC interconnects. A “two level” process prevents minimal dimension devices from being fabricated due to the dominant problem of power routing. Thus lower perfor-

582

10 Compound Semiconductor Device Processing

mance, lower yields and higher cost circuits would be realized. Three-level (Lee et al., 1989) and four-level (Vitesse, 1990, 1995; TriQuint) interconnect schemes provide for flexibility in signal and power routing, and allow for significant circuit compaction and optimization of the signal and power distribution. In multi-layer metallization schemes, the control signals are typically carried in the lower layers, while the power distribution and ground connections are handled in the upper layer(s). Vias are used to complete the interlayer connections. A commercial four-layer metallization process is illustrated schematically in cross section i n Fig. 10-50. In this figure. the interconnection is made from an upper metal layer to a lower level metal directly. The multi-layer configuration shown i n Fig. 10-51 is a "post-andrunner" structure. The interconnect layers would be created by sequential metallization over dielectric, patterning, and some form of via-fillhelected-area metallization. The interconnect runners are formed by aluminum or gold-based metal deposition

v Passivation Dielectric

processes, and photolithographic patterning techniques. The posts may be formed during the interconnect metal deposition or, for example, selective-tungsten CVD processes (Wilson et al., 1993) as shown in Fig. 10-52. Each subsequent metal layer is generally printed with a slightly larger critical dimension as a result of circuit topology constraints. A substantial amount of planarization may be realized as a side benefit of the larger dimensions. However, as is evident in Fig. 10-52, this is not always required. So far. chemical-mechanical polishing has not been necessary in CS device processing. This is due partly to the greatly relaxed geometries necessary to obtain extremely high performance in CS devices, and the somewhat lower integration levels common to CS applications. The number of mask levels in CS processing rarely exceeds 13- 15 plates, even for highly complex circuits in the range of 100000 to 500000 gates (Brown et a1.,1998; Vitesse, 1995), whereas a bipolar silicon process might have 28-30 plates, or more, giving rise to very rough to-

Mask levels

Technology

4 Layers of Aluminum Interconnect

Conventional state-otthmrt Silicon Interconnect

GaAs

Proprietary to Vitesse

MESFET

Figure 10-50. A schematic cross section of a four-layer interconnect metal scheme. Aluminum is utilized for the upper level metal layers i n these MESFET ICs. (Figure courtesy of C. Gardner, Vitesse Semiconductor Corooration. Camarillo. CA.)

10.1 1 Metallization a n d Liftoff Processes

583

Figure 10-51. Details of a “post-and-runner” multi-level metallization scheme. Two levels of metal are shown above the ohmic contact. The via plug may be formed by selected area chemical vapor deposition or by blanket deposition and etching. A substantial amount of planarization may occur in this type of structure as the dielectric layer tends to smooth out height variations and steps. This structure may be continued above the two layers by successive depositions and patterning.

Figure 10-52. An SEM cross section micrograph illustrating the details of a four-layer “post-and-runner’’ metallization process. The via plugs are selected-area CVD tungsten, with a titanium adhesion layer and gold main metal on each tungsten plug. The magnification marker is 1 p m ; the via diameters are approximately 1 p m , and the interconnect metal layer thickness is approximately 400-500 nm. (Figure courtesy of Dr. M. Wilson, Cray Computer Co., Colorado Springs, CO.)

pology. In any case, the larger dimensions of the upper level metallizations have the distinct advantage of a higher current carrying capacity, ideal for low-loss power distribution busses. A four-level “post-andrunner” metal interconnect scheme is shown in a SEM micrograph (Fig. 10-53). This type of multi-layer process has proven to be reliable and manufacturable with high yields (Mickanin et al., 1989; Wilson, 1989). The circuit compaction permitted by multi-level metallization allows for significantly improved high-speed performance. This is achieved predominantly by optimizing the routing through various levels of interconnect and minimizing the distance between critical nodes in the circuit. At present, the use of fourth metal-level power

584

10 Compound Semiconductor Device Processing

Figure 10-53. An SEM micrograph of a four-layer "post-and-runner" metallization process with interlayer dielectric removed. This figure illustrates the beauty and utility of the multi-layer metallization process. The fine geometry lines are gate fingers of nominally I p m i n dimension. The increasingly larger metal lines are evident at higher levels. (Figure courtesy of Dr. W. Mickanin. TriQuint Semiconductor, Inc., Beaverton. OR. 1

routing with relaxed design rules can approach 50% surface area utilization for both power and ground distribution lines (Vitesse, 1990). Since adding an additional metallization layer only requires relaxing the critical dimensions (due to surface topology). a via process, and a dielectric layer, there is no theoretical limit to the number of levels of metal. The performance requirements of up to 50- 100 GHz and a million or more devices do not demand development above four or perhaps five metal levels. 10.11.1 Metallization

In the manufacture of compound semiconductor devices, the interconnect metallizations are still predominantly gold and gold alloy based. Aluminum-based metallization processes are being introduced to fabrication sequences (see Vitesse, 1990), but the use of aluminum and aluminum allow. while well understood i n the silicon in-

dustry, is subject to the same constraints as are found in silicon processing: e.g., the formation of Au-A1 intermetallic compounds with undesirable high resistivity (e.g., "purple plague", see Irvin and Loya, 1978; and Irvin, 1982), and concerns for long term reliability from alloying materials such as copper, modest current carrying capability, and wire-bonding issues. To minimize the metallurgical reactions and rapid in-diffusion of gold, barrier metals such as Pt, Pd, W, or Ti must be used between the contact layer (semiconductor or metal) and the gold interconnect layers. While there barriers perform the function of blocking the intermixing of the contact metals, they add complexity to the process sequence, and ultimately act only to slow the eventual intermixing process. Numerous metallizations have been tried in the compound semiconductor field. The reader is referred to Sec. 10.6, and Howes and Morgan (1985, Chap. 6), for additional supporting discussions. As the processing of compound semiconductor devices matures, aluminum alloys are being used in an increasing number of applications. Aluminum and aluminum alloys have the distinct advantage of being patterned readily by reactive ion etching, ion milling, or lift-off methods, as well as relatively low cost. Gold can be effectively patterned by lift-off or ion milling processes. Submicrometer features may be patterned readily in any of the common metallization systems used in compound semiconductor device fabrication. The aluminum layers are commonly alloyed with copper to stabilize the material against electromigration failure. In silicon devices, copper has not been found to affect device performance. For GaAs, copper is a deep acceptor with at least four deep levels in the lower half of the energy gap (see Fig. 10-3) (Kullendorf et al., 1983). This can give rise to slow transients and erratic de-

10.11 Metallization and Liftoff Processes

vice behavior under certain bias or operating conditions (strongly related to device design and structure). For GaAs digital applications, the AI-Cu system (with barrier layers) appears to be suitable. In the case of RF or mixed signal applications, the process sequences and device structures and operating points are significantly different, and may result in compromised device performance. In InP materials, copper has at least three deep acceptor states, and, in fact, high concentrations of copper give rise to a semiinsulating characteristic and copper precipitation (Leon et al., 1992). Thus great care must be exercised when using AI-Cu metallizations. Gold-based interconnects, on the other hand, are problematic in the silicon case (carrier lifetime-killer centers), but are highly effective for compound semiconductor devices, and have been field-proven as reliable for more than twenty-five years. Typically, gold-based gates and interconnections are utilized in processes that do not use ion implantation beyond the formation of the junction, isolation, and contact layers. This is due to the rapid diffusion and metallurgical reactions which occur at temperatures of - 350-500°C in most compound semiconductors. A common interconnect metallization used in GaAs device fabrication is the Au/Pt/Ti system (Niehaus et al, 1982). Here the titanium layer is used to enhance the adhesion. The platinum layer acts as a diffusion barrier against gold interdiffusion, and to mitigate the reaction of titanium and gold which occurs at -200°C. Since gold and platinum have high conductivity, this “sandwich” structure produces very low resistivity interconnects. An interconnect for higher temperature applications is based on Ti-W/Au. The Ti-W layers are used to contact the semiconductor and provide a diffusion barrier to the gold, while the gold layer carries the majority of the current. This contact has been found to be stable

585

to - 50O-60O0C, although adhesion problems due to differential thermal expansion (stress), and degradation mechanisms are not yet completely controlled. In addition, sputter deposition must be carefully controlled to prevent leakage currents due to surface damage (Kohn, 1979; Day et al., 1977). Interdiffusion is a problem with a number of desirable materials due to the reactivity of GaAs and InP with a wide range of metals. These reactions are well understood through the phase relationships for these systems. For example, aluminum on GaAs interdiffusion has been observed at - 250°C andextended times (Mukherjee et al., 1979; Sealy and Surridge, 1975). It should be noted that for aluminum-based metallizations, 250°C is quite near the “2/3 melting point” criteria used in metallurgy for defining stability to interdiffusion, and thus such interactions are expected. For further understanding of potential intermetallic phase formations, see Massalski (1986). As previously discussed, barrier metals or alloying elements can be used to improve the stability and minimize interdiffusion in the contact regions. High temperature interconnects and metallization are used when the wafer may be subjected to high processing temperatures as required for ion-implantation annealing. These materials were discussed in Sec. 10.6 in the context of gate formation. Such interconnect configurations are typically constructed from refractory metals such as Ti-W, W-Si, Ti-W-Si, W-N, Ta-N, and Ta-Si (some of these materials may also be used for thin film resistor stripes). It has been found that these materials withstand temperatures well in excess of 850 “C without significant interdiffusion [see Dautremont-Smith et al. (1990)l. There are significant limitations in the metal line widths, achievable by different patterning methods. The electron beam

586

10 Compound Semiconductor Device Processing

(e-beam) writing system has achieved dimensions below 100 nm in the laboratory, but this is a very daunting proposition for the fabrication line where control. low cost, and reproducibility are required. An example of a -0.1 pm e-beam-exposed. T-gate structure was shown in Fig. 10-38. Typically. gate dimensions as small as 0.35 pm are printed by step-and-repeat systems (Williams, 1990; Wilson et al., 1993), whereas “0.25 pm” or smaller technology is implemented with e-beam methods (Danzilio et al., 1992). Smaller gate features require multi-layer offset photoresist patterning. electron beam, or other short wavelength processes such as deep ultraviolet exposure. Owing to instrument throughput constraints, the e-beam is only used to write the finest gate features. not the general metallization patterns. The step-and-repeat systems can control line widths down to 0.4 pm using the G-line, and 0.3 p m using the I-line, from high intensity mercury vapor light sources. Figure 10-54 shows a 0.36 pm gate feature defined by G-line exposure. Finer features can be produced by careful control of the photoresist thickness, exposure conditions. multi-layedmulti-exposure photoresist and metal thicknesses. Figure 10-55 schematically illustrates a method of offsetting multiple photoresist layers and implementing directional metal deposition to achieve finer metal line geometries. In the upper metallization levels there are fewer constraints in the metal line dimensions, but patterning and dimensional control may be complicated by the topology. Partial planarization by dielectric deposition can relieve these problems. Ion milling or sputtering methods may be used for metal pattern definition. This process requires a high vacuum system and appropriate high current ion sources or plasma excitation systems. In the ion milling process. a high flux ion source is used to sput-

ter the unwanted metal atoms from the exposed surface. In sputtering processes, an ion plasma is created above the wafer surface which removes metal atoms by physical sputtering processes. Argon, or chlorinecontaining compounds, are typically used for the source gases. Nitrogen gas may be added to ballast or control the ion milling rates. The patterning of fine features is limited by the spacing of adjacent metal runners due to shadowing of the ions by the topology of the metal and the pre-existing wafer surface. The photoresist or other defining layer (e.g.. a second metal, a dielectric layer, or a combination of photoresists and metals or dielectrics) add to the topological relief. Ion milling is relatively slow compared to liftoff processes, although it leaves a very smooth surface and is not subject to edge burring and adhesion-strength limitations. Sputtering is relatively rapid and can be used to etch fine features. One of the concerns in ion milling or sputtering is that in

Figure 10-54. A SEM micrograph showing a recessed gate opening. The magnification marker is I p m . The trench dimension is 0.356 p m at the bottom. printed by G-line photolithography. This dimension represents the limit to G-line lithography with single pass step-and-repeat exposure systems, and standard photoresists. (Micrograph courtesy of P. A. Grasso, S . E. Lengel. A . F. Williams, Lucent Technologies. Inc.. Reading, PA.)

10.11 Metallization and Liftoff Processes

587

Figure 10-55. A schematic view of a method for creating fine features with process-limited photolithography. a) A layer of photoresist is deposited and exposed at a controllable dimension. A second layer of photoresist is deposited on the wafer and exposed with a specific offset to the original pattern. Clearing the exposed photoresist leaves a bilayer offset feature as shown in b). Subsequent metal deposition, preferably at a substantial angle. produces a fine metal feature of dimension much less than the photolithography limit, if desired.

the process of etching, residual ion damage and redeposition of sputtered species may occur, which can lead to surface-state-induced electrical effects or leakage paths in devices. In most process tools, only a single wafer or a few wafers can be etched at a time, leading to a limited throughput in the apparatus. The topic of ion etching was discussed in Sec. 10.5 in a more general context. The criteria and utilization presented therein are applicable to metallization patterning.

10.11.2 Liftoff Processes Liftoff procedures are implemented when metallizations are incompatible with chemical etchants, when rapid, high throughput processes are desired, or when ion-based patterning is undesirable. The as-deposited metal layers are required to be ductile and adherent in order to permit the selective separation of the unwanted metal from the wafer surface. In addition, the control of step, edge, and side-wall coverage is critical for

5aa

10 Compound Semiconductor Device Processing

providing a “weak link” to permit separation of the metal film. Metals that are deposited by evaporation or plating meet these criteria and are generally quite well suited for liftoff processes. These patterning methods are particularly effective for gold or gold-based materials. as deposited gold layers are nearly “dead soft”. Sputtered metal layers, and particularly refractory metals, are more difficult to liftoff successfully due to high adhesion to all surfaces, relatively good conformal coverage of steps and edges, and their tendency to be harder in the as-deposited state. Liftoff processes involve the creation of high aspect ratio trenches or undercut pattern features in the patterned photoresist or

dielectric layer(s), coupled with a “directional” type of metal deposition process. The metals are deposited over this patterned sacrificial film. Then the metal layer and sacrifical film is stripped off by mechanical, chemical, or chemo-mechanical means, so “lifting” the unwanted metal from the surface. To successfully carry out the liftoff process, complete, full thickness metal coverage at the edges of the photoresist or dielectric layers is highly undesirable. Electron beam or resistance-heated evaporation methods are best suited to the deposition of metal layers due to the highly directional nature of the evaporation process, resulting in “poor” edge/sidewall or corner coverage, as illustrated by Figure 10-56.

Figure 10.56. A schematic illustration of an optimal liftoff metal coverage. a) The key to a clean metal liftoff lies in the thin or nonexistent coverage of the side walls of the gate or metal trench feature. b) The thin lines of metal part readily form the main metal line when the photoresist of patterning material is removed from the wafer. leaving the desired metal line pattern.

10.1 1 Metallization and Liftoff Processes

Other methods of metallization, such as sputtering or plating, tend to provide a more uniform surface coverage, and thus are less well suited to liftoff techniques, unless the sacrificial layer is shaped to create a thin parting line in the metal. The thickness of the dielectric or photoresist, and the edge definition, play a critical role in the perfection of the liftoff procedure by influencing the thickness of the metal coverage during deposition. The metal at step edges and corners is typically much thinner than the bulk regions of the metal film. Therefore the edges are much weaker than the bulk and easily parted at these sites. Ideally, there is no metal film continuity and the undesired material will liftoff without residue. The thinning or lack of coverage at the feature edges is also important for the prevention of burring and the elimination of interlayer short circuits. However, great care must be exercised in lifting off the metal, as many desired metal traces have steps and edges in their topology. Several methods of “lifting” the undesired metal are available. All of the methods rely on a solvent (water or organic chemicals) or an etchant to dissolve the sacrificial layer. Typical photoresists are quite soluble in acetone or other organic solvents. Sacrificial dielectrics films may be dissolved with HF or other suitable acids or bases. This latter approach has been used for large area liftoff of epitaxial films (Fan, 1990; Yablonovich et al., 1990) by utilizing sacrificial AlAs or AlGaAs layers. Subsequently, the unwanted metal and the sacrificial layer are floated or “scrubbed” off the surface of the semiconductor wafer with agitation, a high pressure fluid spray, or other mechanical means. As uncontrolled physical/mechanical scrubbing can be quite damaging to the remaining metal, most processes use deionized water or other solvents at moderate pressures and flows to remove

589

the metal and residual photoresist or dielectric materials. Metal recovery systems are used to reclaim precious metal wastes in these processes. Static electricity can be an issue with solvents or other chemistries flowing over a highly resistive substrate, leading to circuit damage. Surfactants or other materials may be added to the fluid streams to reduce static charge build-up. The adhesion of the metal to the desired surfaces must be strong in the as-deposited state or the metal layer may be removed from undesired areas during the liftoff. At the same time, poor adhesion of the metal to the sacrificial dielectric or photoresist layer is highly desirable. In addition, relatively thin metal layers must be used to prevent tearing of the metal or lifting off of the desired layer. Edge lifting and undercutting may occur if the adhesion to the desired contact region is insufficient. Burring can be a problem with liftoff processes owing to the ductility of the metals in the as-deposited state. The liftoff processes may tear the metal at the parting lines if there is incomplete separation of the deposited metal film. This result could be due to excessive metal coverage or thickness variations, grain structures anomalies, adhesion variations, particles, etc. Small burrs will be left along the edge of the metal line in this case. This problem is illustrated in Fig. 10-57. The burrs can protrude through the next level of dielectric causing short circuits between the metal layers. Careful preparation and wellcontrolled deposition conditions are required to ensure clean removal of the unwanted metal. Figure 10-58 illustrates a “clean” edge definition on a multi-fingered air bridge structure created with liftoff methods. The air bridge was constructed by a sacrificial layer post-and-runner process. At present there is no solution for complete amelioration of the problems of edge lifting and minor tearing/burring of the

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10 Compound Semiconductor Device Processing

Figure 10-57. An illustration of a burr formed on a metal feature due to improper trench edge definition or excessive metal layer thickness. In this case the burr may extend along the metal line or be an isolated fine point. This may cause interlayer shorting due IO poor dielectric coverage in subsequent process steps.

metal layer. Good process methodology and process control can produce excellent. reproducible results with liftoff processes. A minor amount of yield reduction may occur from open circuits, electrical contact resistance variations. burring, and short circuits. While these drawbacks can be quite serious, many materials cannot be successfully etched or ion milled, thus liftoff processes are the only viable alternative. It should be noted that commercial liftoff-based processes are quite robust, and presently operate with high yields.

10.12 Backside Processing and Die Separation Backside processing is carried out when the wafer must be thinned or if a back-surface metallization layer is needed. It is highly desirable to thin a compound semiconductor wafer to improve device performance from both the thermal and electrical standpoint. For example, thin wafers and the use of backsurface ground planes are critical to the R F performance of microwave devices. The spacing of the top surface conductors to the ground plane (back surface), i.e., the wafer thickness, creates a controlled

59 1

10.12 Backside Processing a n d Die Separation

Figure 10-58. Secondary electron micrographs of air bridge structures formed by liftoff methods. The marker is 10 p m in both images; the span dimension is approximately 25 pm. In a) a “sea” of approximately 125 air bridges over interconnect metal lines is presented. I n b) a high magnification image of a few air bridges is presented. Note the moderate take-off angle of the bridge, leading to high strength and high reliability, and the elimination of electrical shorting. Bridge structures such as these readily withstand backside processing. (The micrographs are courtesy of P. A. Grasso, S . E. Lengle, A. F. Williams, Lucent Technologies, Inc., Reading, PA.)

impedance condition for transmission lines, which is required for stable microwave performance. It may be necessary to link the top surface ground lines to the back surface ground plane, Le., through-wafer vias are required. Source or emitter vias (for FET or HBT devices, respectively) provide low im-

pedance connections to the ground (Furukawa et al., 1998). In addition, thinner substrates and through-wafer vias permit vastly improved heat extraction from the devices. As the thermal conductivity of GaAs and InP is significantly less than that of silicon, this is a critical issue, as shown in Table 10-9. Thus by thinning the wafer, greater power may be dissipated per unit area for a given temperature rise, permitting compact, high-power devices without compromising performance. If no backside processing is required, the wafer would pass to die separation, as described in Sec. 10.12.2. One of the key issues in the backside process flow is attention to detail; the importance of this point cannot be over-emphasized. Since the front side process is now completed, it becomes an extremely expensive proposition to damage the active circuitry while thinning and metallizing the back surface. There is a great amount of handling in the backside process which can subject the wafer, in a relatively weak condition, to significant abuse. Breakage, contamination, and physical damage (e.g., scratches and chips) may occur at each of the mounting, grinding, polishing, cleaning, etching, metallization, and demounting steps, which encompass the backside process sequence (Fig. 10-59). In comparison to silicon fabrication, compound semiconductor materials are much “softer” (the hardness of GaAs is approximately one-tenth that of silicon), and have facile cleavage, which emphasizes the importance of careful handling to avoid Table 10-9. Thermal conductivity of selected semiconductors“. Silicon ISh

Gallium arsenide

Indium phosphide

0.48‘

0.56d

Values in W cm-’ K-’ at 300 K; Sze (1981, App. H ) ; ‘ E M I S ( I 9 9 0 , S e c . 1 . 8 ) ; d E M l S ( 1 9 9 1 , S e c .1.8).

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1 0 Compound Semiconductor Device Processing

Thickness I

Mount to Substrate

Grind (oneor two-step)

PhotdiTraphy Through-wafer IR Alignment

1 Scribe-and-Cleave

i Cleaning

inspection

Inspection

Polish (chemical or mechanical) Substrate

Figure 10-59. An example of process flow options for creating back surface metallizations, through-wafer vias, die separation, and the selection of viable devices

chips and breakage. Finished die costs are highly dependent on the success of this final process step. Very little information on the complete backside processing sequence has been made available in the public domain, as it is considered highly proprietary. The process flow description herein is drawn from the authors’ experience and discussions with other experts, and represents a “hybrid” view of the backside issues.

10.12.1 Backside Processing The process involves a multitude of steps to complete the wafer process flow as shown in Fig. 10-59. The principal tasks to be accomplished are: mounting, grinding, cleaning, polishing, and if required, masking, via etching and finally, metallization. Following these processes the wafers will be electrically tested and optically inspected, the useable die separated by various means, and the die passed to assembly and packaging.

Mounting involves fixing the wafer topface-down onto a supporting substrate to facilitate the grinding or lapping processes and subsequent handling in a thinned condition. This mount must be physically strong, stiff, extremely flat, and not damaged by the thinning processes. Sapphire or quartz mounts, ground and polished to optical flatness, are suitable for this task. Silicon wafers or other materials may be used if back-to-front alignment is not required. The wafers may be affixed to the mount by an IR-transparent adhesive (e.g., paraffin, beeswax, or other readily soluble, noncontaminating materials of low melting point). Adhesive tape products, such as NITTO tape are also suitable for mounting. It is critical to ensure that the mount is free of particulates and that the wafer is parallel to the mount surface. The wafer must not be subjected to excessive stress or pressure during the mounting procedure, and great care must be taken to prevent damage to the front side structures. This latter point is particularly

10.12 Backside Processing and Die Separation

important when air bridge technology is employed. Wafer thinning is a slow, labor-intensive process even with automated apparatus. The initial grinding or lapping of the back surface may remove up to - 95% of the original thickness, with an accuracy of a few micrometers (-0.1 mil). The wafer may be ground to a thickness slightly greater than the final target value, and then chemically polished or etched as desired. The etching step removes grinding damage and achieves the final thickness and surface quality suitable for via etching and/or metallization. High precision grinding apparatus is required for this task, with well controlled stock removal rates to prevent damage to the wafer and to ensure accurate thickness control. Fine diamond grit (1 - 10 pm nominal) grinding wheels can produce a good surface flatness at economical grinding rates without generating excessive damage to the substrate. Commercial vertical spindle/horizontal pass grinding units can achieve very good control and reproducibility of the thickness and surface quality (Lapinsky, 1991). Following the grinding procedures, the wafer and mount are carefully cleaned to remove grinding residues. This step involves a detailed inspection of the wafer to identify any surface damage, fractures, or chipping of the edge. The wafer may then be chemo-mechanically polished to the final thickness, removing the gross damage from the grinding and preparing the surface for metallization or masking and via definition. The final polish chemistry is typically based on NaOCl or NH,OH etching solutions as they are anisotropic and produce a superior surface finish (Stirland and Straughan, 1976). For InP substrates, mixtures of bromine and methyl alcohol are typically employed (Chin and Barlow, 1988). Chemomechanical etching tends to slightly round

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the wafer profile as polishing occurs. Therefore care must be taken to maintain the flatness and parallelism of the wafer surface. In addition, the polishing systems must be well-characterized to achieve an accurate final thickness as the material removal rates vary strongly with polishing pressure and solution pH. In a well-controlled process, variation can be maintained within 2.5 pm (0.1 mil) to 5 pm (0.2 mil) for a final thickness ranging from 100-250 pm (Lapinsky, 1991). Wafers for certain microwave or high power applications are thinned to as little as 25 pm (1 mil) (Niehaus et al., 1982). At this thickness the wafer will readily conform to corrugations in the NITTO mounting tape. The mounted wafer is now ready for backside metallization. As shown in Fig. 10-59, there are two paths: photoresist deposition and exposure of the via pattern to create the front-to-back contacts, or, if vias are not required, the mounted wafer is cleaned and passed to metallization. Typically, a 4 mil (100 pm) or thinner wafer will not be demounted as cleavage is quite facile in compound semiconductor materials; 250 pm (10 mil) thick wafers can be carefully handled without a carrier. Thorough cleaning is again critical to the success of the process, as adhesion of the photoresist and the initiation of etching are strongly influenced by the surface condition. The photoresist masking layer for backside processing must be significantly thicker that required for the front surface processing. Owing to the very extended etching times needed for opening vias through hundreds of micrometers of substrate, the masking layer must be much more robust, although the precision of the critical dimensions is more relaxed than for front side processes. Multi-layer masking techniques may be used to minimize via “blowout” (expansion significantly beyond the

594

10 Compound Semiconductor Device Processing

patterned dimensions) and damage to the substrate (edge lifting, pinhole leakage, etc.). For example, additional layers of photoresist, or metals such as Ni or Cr, could be applied on top of the base photoresist layer. In this case, the photoresist layer may be only a few hundred nanometers thick, and the metal layer of the order of 50 nm thick. Exposing a through-wafer via pattern requires a “front-to-back” infrared aligner system. In this apparatus the front surface metallization pattern is imaged through the carrier and wafer using sub-bandgap infrared light The alignment of the via mask pattern is referenced to the target contact pads on the front surface. Exposure is carried out as with normal photoresist techniques (see Chap. 4 of this Volume) with the exception that very extended or multiple exposure times may be required. In multi-layer processes several passes through this sequence are necessary. The through-wafer vias are etched in a manner described in Chap. 6 of this Volume and Sec. 10.5. Reactive ion etching is becoming the preferred method, as the morphology and aspect ratio of the via may be controlled through the etching conditions (pressure and gas compositions). With wet chemical methods, the vias tend to expand laterally as vertical etching proceeds even with highly anisotropic etchants, although very smooth via walls result with wet chemistry methods. It is difficult to control the final “over-etching” of the target areas and minimize the damage to the front surface if etchants leach around the metal contact pads. Also, the aspect ratio of the via and the side-wall structure is critical to the metallization process: severely undercut edges, re-entrant corners, or curved side walls (Fig. 10-60a), or vertical side walls and sharp corners (Fig. 10-60b), will prevent or complicate successful metallization coverage, leading to unsatisfactory continuity, high resistivity, and poor reliability.

Metallization steps are carried out after careful cleaning of the etched wafer. Residues are often left on the surface due to polymerization or overheating from the ion plasma during RIE, or residual by-products from the chemical etching procedures. It is crucial that any foreign materials are removed as the metallization quality may be affected or inhibited entirely. There are several approaches to backside metallization: 1) deposit a thin layer of metal(s), form a plug in the via hole, and then deposit a thick, full surface metal layer over the entire wafer: 2) deposit a thin metal layer for contacting, and then use a “solder” flow process to fill the vias and provide the full surface metal cover age. Many variations of these general approaches exist. Metallization may be carried out in two or three steps: the first to provide an intimate conformal seed metal layer to ensure ohmic contact to the exposed (back surface) metal pads on the front surface (Fig. 10-61), then to “plug” or “fill” the vias, and the third step to completely contact the surface and the vias creating the ground plane. The via may or may not be completely filled. The final process entails the addition of a planarization metal deposition or the application of a thick back surface metallization. The first metallization may be an adhesion promoting layer (e.g., titanium), or a layer of gold or gold alloy. The plug process should appropriately fill a via and be relatively planar. When the final metal layer is formed it must be adherent, uniform in thickness, and planar. Examples of the plug process are shown in Figs. 10-62 and 10-63. In Fig. 10-62 an SEM micrograph shows a view of a via hole. The morphology of the wall of the via is apparent. A series of via plugs with top surface contact pads is shown after etching away the substrate in Fig. 10-63. The surface morphology of the via perimeter is evident on the gold plugs. It is clear that the

10.12 Backside Processing and Die Separation

595

Figure 10-60. Illustrations of undesirable via morphologies. In Fig. 10-60a, the effects of undercutting or re-entrant corners are evident. Metal coverage and continuity are compromised by these conditions. Figure 10-60b highlights the additional problems of sharp corners and vertical side walls. Here the filling of the via may be compromised by the vertical wall, and the sharp corners enhance stress localization.

Figure 10-61. Schematic illustration of a well-defined through-wafer via. The corners of the via are rounded to enhance continuity and minimize stresses. The seed plating is continuous and the filling metal shows only limited underfilling. A planarization metal layer is shown (optional). The final back surface metal layer provides the continuous back-plane conductor.

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10 Compound Semiconductor Device Processing

Figure 10-62. As SEM micrograph of a via hole after etching. The diameter of the via is approximately 100 pm. Note the gentle curvature of the top region of the via. (Figure courtesy of Dr. A . Colquhoun. Daimler-Benz Research Center, Ulrn, Germany.)

acteristics. Solder-fill approaches can provide a via fill at relatively low cost. The plug metallization must be compatible with plated or evaporated gold or gold alloys typically used for the ground plane formation, and subsequent die attachment processes. The back surface metal plate-up is normally many micrometers thick and uniform in coverage to ensure uniform electrical and thermal contact, low resistance, and to withstand the alloying and reaction that occurs during mounting of the finished die to the package. For this reason, plating methods (electro or electro-less) are optimal, although evaporated or sputtered metals may be used. The key issue during the metal deposition process is to keep the wafer temperature below the softening point of the adhesive material (the wafer is still mounted on a carrier). Plating may be carried out at temperatures below 100"C, which is compatible with most adhesives, whereas evaporation may expose the wafer to very high surface temperatures, and sputtering methods can raise the temperature to well above 200°C. To circumvent the heating problem, evaporation or sputtering may be carried out in steps, although there are penalties in system throughput, the metal film qualities, and the cost associated with this type of process sequence. Active cooling may be necessary to help control the temperature rise. As in front surface metallizations, an adhesion promoter such as nickel or titanium may be used to improve the adherence of the back surface metal. When using electroplating processes it is difficult to produce a uniformly thick metal layer owing to the high resistivity of semi-insulating substrates (GaAs or InP) and the finite electrical contacts. A metal seed layer is required to initiate the plating process. Current flow necessary to induce plating is inhibited in the substrate, and current spreads through the

Figure 10-63. An SEM micrograph of a series of through-wafer vias after removing the GaAs substrate. The top surface contact pads form a cap on the filled via metal. Via diameters are slightly larger than 100 pm. These vias are used to form a ground plane for 2 20 GHz device operation. (Figure courtesy of Dr. A . Colquhoun. Daimler-Benz Research Center, Ulm, Germany.)

shape of the via hole is critical for achieving continuity between the back plane and the front surface contacts. Plugs may be formed by selected area filling with gold, gold-based alloys, or other metal solders, or bv dating processes with good filling char-

10.12 Backside Processing and Die Separation

seed layer from the electrical contacts. The metal build-up generally occurs more rapidly in areas close to the contact(s), especially if high plating currents are used. The use of highly conductive, adhesion-promoting layers and substantial seed metal thickness can greatly reduce this problem by increasing the in-plane conductivity. There is additional concern for interactions of gold with GaAs and InP with respect to long-term stability under severe operating conditions. Barrier metals such as nickel, platinum, or palladium may be incorporated in the back surface metal layers to reduce the interaction of gold or solder metals with the GaAs substrate (Parsey et al., 1996). However, it has been shown that gold-based metallurgy is very stable under high-stress reliability testing (Irvin, 1992). References such as Massalski (1986) should be consulted for further understanding of the relevant phase diagrams. At this point the wafer may be demounted from the supporting plate. The wafer is now quite fragile and easily damaged by mishandling. Several cleaning steps are required before the wafer may be passed to testing and evaluation. The adhesive materials and any undesired materials that were placed on the front surface as a protective coating must be removed. As before, no residues may be left on any surfaces as they will impede electrical contact to the back surface as well as the bonding pads on the front surface. The wafer may be transferred to a supporting carrier such as a NITTO tape handling system (Nitto). Here the wafer is gently pressed onto a polymer film which is supported by a tensioning ring carrier. The film and ring are capable of supporting the wafer mechanically during testing, die separation, and “pick and place”. As the polymeric film is plastic, separating the die is accommodated by expanding the film after the “streets and alleys” are cut or formed.

597

10.12.2 Die Separation The wafer must now be electrically tested to identify the good die. After testing and marking (ink dot or X - Y die location map) the die must be separated for mounting in packages. Several methods exist for separating the die: scribe-and-cleave (diamond scribe or laser ablation using varied mechanical stresses to cleave the wafer along the scribe lines) and sawing (typically with diamond blades). The first approach is best suited to wafers with thin or no backside metallization, although if the metal layer is less than a few micrometers thick this tends not to be an insurmountable problem. The latter method is required for very thick backside metallizations because of the malleable nature of gold. With diamond or laser scribing, a groove is scored or ablated, respectively, in the “streets and alleys” between adjacent die. The groove acts to focus the mechanical stresses when the wafer is flexed on a suitable pad by a roller-type device or impacted by a cleaving bar. The use of a roller-type method is not well suited for devices using air bridge metallizations unless great care is exercise in the scribing and the mechanical handling: the air bridges are easily crushed. Also, detritus from the diamond scribe or laser ablation processes may be lodged around the air bridges leading to short circuits or other damage, unless the surface is encapsulated. Recently, an apparatus for “scribe-andcleave” processes has been introduced to compound semiconductor technology (Dynatex). This instrument uses an automated diamond scribe system coupled to a precision impact bar which rides below the backside of the wafer is indexed in two dimensions while the impact bar is snapped up to the back surface at each scribe line The sharp impact breaks or cleaves the wafer

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10 Compound Semiconductor Device Processing

without excessive force, and has been found to be suitable for die separation when air bridge metallizations are used, although the cautions of contamination apply due to use of the diamond scribe. It is important to note that these processes perform best when photolithography is carried out aligned to the preferred (1 10) cleavage directions in the compound semiconductors. Attempting to die separate along other crystal directions generally leads to failure and low yields. The second method of separation is diamond sawing (AT, Disco). In this approach, the wafer is placed on a precision indexing table and then moved beneath a rotating diamond wheel to cut a groove in the “streets” on the wafer surface. The blade width is typically -10 pm (0.0004 in) to - 100 p m (0.004 in), creating a cut roughly 25% wider than the actual blade dimension. Diamond sawing is the “least clean” method to separate the die. As noted above, the wafers should be encapsulated to protect the surfaces from damage and contamination. However, this may be i n conflict with the testing and evaluation sequence. Use of the diamond blade, the coolant/lubricant fluid, and the generation of chips and other rubbish creates significant contamination of the wafer surface and necessitates careful cleaning procedures to remove the residual materials. After the “x” and “y” groove pattern is cut, the wafer may be mechanically stressed to cleave the substrate along the grooves, as noted above. The same constraints apply here to the use of the mechanical flexing approach for cleaving the wafer. In some cases the wafer may be sawn completely through the back surface metal. Great precision is demanded in the cutting process to avoid excessive damage to the substrate carrier film layer. Vibration imparted into the wafer during sawing is of substantial detriment to GaAs and InP materials, as they are quite brittle. Edge dam-

age, fractures, and undesired cleavage can readily occur during the sawing operation. One step remains before the die may be selected: physically separating the die. In the case of NITTO tape or similar materials, this step is effected by stretching the polymer film. The spacing between the separated die is expanded to allow mechanical chip handling devices to remove the chip from the film, or to permit human handling, without damage to adjacent die. Exposure to chemicals or UV light may be used to reduce adhesion between the wafer and the carrier to facilitate the removal of the die from the film. “Pick-and-place” is a process of selecting the good die and locating them in a chip carrier or package cavity. This is done either manually or with automated systems. Vacuum pickups are employed to avoid the damage and yield losses associated with tweezers or mechanical clamping devices. In the case of expanded film carriers either method may be used. Solid wafer carriers (e.g., sapphire or quartz) do not lend themselves to effective die separation, and therefore require manual chip selection in the latter case, further cleaning processes may be necessary to remove residues. The identity of the die and the location within the wafer are known from the testing sequence and may be maintained prior to assembly. Following completion of the pick- and-place operation, the die are subjected to additional visual inspection with the survivors passing to assembly and test.

10.13 References Abernathy, C. R., Pearton, S . J., Caruso, R., Ren, F., Kovalchick, J . (198Y), Appl. Phys. Lett., 55, 1750. Abrokwah, J., Huang, J. H., Ooms, W., Shurboff, C., Hallmark, J., Lucero, L. (1993), in: 15th Guns IC Symp., Tech. Diye.rr. New York: IEEE; pp. 127130.

10.13 References

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11 Integrated Circuit Packaging

Daniel I Amey E . I . DuPont de Nemours Inc., Dupont Electronic Materials. Wilmington. DE. U.S.A.

List of Symbols and Abbreviations ........................................ 11.1 Introduction ..................................................... 11.2 Package Functions ................................................ 11.3 Integrated Circuit Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Die Attachment .................................................. 11.5 Microinterconnect Methods ........................................ 11.6 Wire Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7 Tape Automated Bonding (TAB) .................................... Flip Chip or Solder Bump .......................................... 11.8 Package Sealing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.9 11.10 Rent’s Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.11 Thermal Management ............................................. 11.11.1 Thermal Resistance ............................................... 11.11.2 Cavity-Up/Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.12 Package Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13 JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.1 Dual In-Line Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.2 Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.3 Chip Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.4 Small Outline Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.5 Grid Array Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13.6 Hybrid Circuit Packages .......................................... 1 1.14 Package Attachment .............................................. 11.15 Electrical Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.16 Other Package Selection Considerations .............................. 11.17 Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.18 Multichip Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.18.1 Introduction ..................................................... 11.18.2 Multichip Packaging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.19 Change and Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.20 Change Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.21 Repair Links ..................................................... 11.22 The Future ...................................................... 11.23 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

608 610 610 612 614 614 615 616 618 619 620 621 621 624 624 624 626 626 627 628 628 630 631 633 635 636 637 637 637 640 641 642 644 645

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11 Integrated Circuit Packaging

List of Symbols and Abbreviations 9

P P TI T2 E, QC,

0, 0,) QJ2

QJ3 QJ.4

QJC

0, ATAB BGA

c4 CERDIP CMOS CQFP DIP ECL EIA EIAJ FQFP FRU IC IEC IEEE

I10 ISHM JEDEC LCC LFPM LGA LIF LSI MCM MCP

number of logic gates number of pins dissipated power average die junction temperature ambient air temperature relative dielectric constant case-to-air thermal resistance thermal resistance of the die thermal resistance of the heat sink material thermal resistance of the die-to-package interface thermal resistance of the package-to-heat-sink surface thermal resistance of the heat-sink-to-air (film resistance) junction-to-air thermal resistance junction-to-case (exterior) thermal resistance thermal resistance of the package material TAB ball grid array ball grid array chip carrier controlled collapse chip connection ceramic dual in-line package complementary metal-oxide semiconductor ceramic quad flatpack dual in-line package emitter coupled logic Electronics Industries Associa tion Electronics Industry Association of Japan fine pitch quad flat pack field replaceable unit integrated circuit International Electrotechnical Commission Institute of Electrical and Electronics Engineers input - output International Society of Hybrid Microelectronics Joint Electron Devices Engineering Council leadless chip carrier linear feet per minute land or leadless grid array low insertion force large scale integration multichip module multichip packaging

List of Symbols and Abbreviations

Iv SI P-3GA Pc 3A PXC P‘bVB Q FP QUIP SI MM s1P S’vlTA S”k4TPGA Sc 1 SC >J sc >P S ( IT S‘>OP T. I B Ti :E TCM Tc )FP T‘jOP v LSI Z F Z P

medium scale integration plastic ball grid array pin grid array plastic leadless chip carrier printed wiring board quad flatpack quad in-line package single in-line memory module single in-line package Surface Mount Technology Association surface mount pin grid array small outline SOP with leads in a J configuration small outline package small outline transistor shrink small outline package tape automated bonding thermal coefficient of expansion thermal conduction module thin quad flatpack thin shrink small outline package very large scale integration zero insertion force zigzag in-line package

609

61 0

11 Integrated Circuit Packaging

11.1 Introduction A package as defined in JEDEC Standard No. 99 is “An enclosure for one or more semiconductor chips that allows electrical connection and provides mechanical and environmental protection”. A wide variety of package types exist having different shapes, materials, styles, terminal forms, terminal pitch and terminal count. Terminal count is a general, generic term referring to pins, leads, pads, solder bumps, etc., and is often used interchangeably with the term which describes a specific configuration. Thousands of package variations exist, each meeting specific application requirements. Designers selecting an integrated circuit (IC) are faced with an “alphabet soup” of package types - BGA, PGA, LGA, LCC, TSOP, TSSOP, QFP, MQP, etc., etc., etc., - from which to choose; but it has not always been this way. In the 1960s the choices were few, with the dual in-line package (DIP) the most popular type. Since then, each decade has seen a doubling of the number of basic package types available to the designer, thus making the choice of a package type more difficult and critical to the success of the overall packaging approach. Packaging and interconnection has limited, and will continue to limit electronic system performance. It is rare for a package type to disappear from the scene. This is illustrated in Table 11-1. The DIP quickly replaced the TO5 style package for ICs; but after 30+ years, the DIP still remains in widespread use in electronics packaging. Package types and variations evolve without replacing existing types, resulting in the proliferation we have today. Some of this is due to the early identification of the potential or need for a new type, the long gestation period for a package to become widely applied due to the establishment of the infra-

structure to apply the package (asssembly equipment, test tools, etc.), and investment in both the factory and the field. But, due to rapid change, the required investment is not just the investment in the new approach but also that of the prior packaging approach. This investment drag on technology insertion is one of the major reasons the D I P has enjoyed such a long life. Packages have changed and will continue to change to develop denser, thinner, lighter single chip packages and proliferation of types will continue. As has long been the case, no one package type can suit the needs of the many and varied applications in the electronics industry.

11.2 Package Functions Semiconductor circuits continue to place new demands on circuit packages and interconnections for eficient circuit packaging. Package trends are toward increasingly higher terminal counts, higher thermal dissipation, higher packaging densities (more interconnections per square inch) and multichip packaging to improve electronic system performance with increased functionality and capabilities. In the 1950s and early 1960s discrete semiconductor devices and electronic components such as transistors, resistors, and capacitors with axial and radial lead terminals were predominant. As semiconductor technology improved, and more and more components could be put on a silicon chip, the number of pins on the TO-type semiconductor packages were not sufficient. ICs used circular TO5 packages with 10 and 12 leads in a circular pattern, the pin limit for the package and the printed circuit interconnect technology for that time (about 1963). This resulted in the need for, and introduction of, the D I P and the D I P has

61 1

11.2 Package Functions

Table 11-1. Integrated circuit package types. -

P ickage type

Dual in-line package Fidt pack C iip Carrier LLladless chip carrier Pldstic leaded chip carrier Grid array Pin grid array L(,adless (land) grid array Sriiall outline or small outline IC Sryiall outline J lead Ti,pe automated bonding

In -line packages Si,igle in-line package Zig-zag in-line package Q .lad in-line package Single in-line memory module

Q.iad flat pack Molded ring carrier Fine pitch quad flat pack Tliin quad flat pack SI-rink small outline package Tliin small outline package Tliin shrink small outline package

Acronym

1960s

1970s

1980s

19905

DIP FP

0 0

LCC PLCC

0 0

PGA LGA

0 0

SO or SOIC SOJ

0 0

TAB

0 0 0

0 0 0 0

SIP ZIP QUIP SIMM (SIP)

QFP TAPEPAK * FQFP TQFP SSOP TSOP TSSOP

0 0 0 0 0

BGA PBGA ATAB SMTPGA

0 0 0 0 0

G,-idarray Bi.11 grid array

P1,istic ball grid array TtiB ball grid array SL.rface mount pin grid array Metric TAB M ultichip module MCM pin grid array MCM ceramic quad flat pack Shrink DIP Memory cards L; rge IjO SIMMs

TAB MCM MCM PGA MCM CQFP

SIMM (SIP)

served as the workhorse package for many years and will continue to be a primary semiconductor package type for many, many years to come. However, in the mid-I970s, as the semiconductor technology advanced into

0 0

0 0 0

0 0

0 0 0

medium scale integration (MSI) and large scale integration (LSI), more and more components and capabilities became possible on the silicon die or chip, but there were not enough pins or terminals in the DIP or other in-line styles to practically

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11 Integrated Circuit Packaging

support the logic that could be fabricated on a single die, This led to the need for different package types; the large pin (or terminal) count packages such as chip carriers and pin grid arrays (PGAs), the fine pitch QFPs and now ball grid arrays (BGAs) and multichip modules (MCMs). It is a fact of life that more pins can always be used. Multichip packaging is the latest direction for packages and modules. Multichip packaging is not new for it has been applied in both military and commercial applications for over 25 years. Ceramic hybrid technology, the original MCMs, provided the functional equivalent which the state-of-the-art semiconductor technology could not economically provide as a single die. As semiconductor technology advanced, those functions in the multichip package were, or were capable of being, replaced by single-chip functions with higher performance or capability. Yet, there was still the need/desire for capability beyond what single chip packaging could provide in the military and high performance markets which continued the growth of the hybrid industry and the same needs are now moving multichip packaging in ceramic, thin film and printed wiring technologies into the mainstream. More on that later. Single chip package types are still the basis for multichip packages and single chip packages will continue to be used in high volume. Multichip functions will become single chip functions or packages as semiconductor technology continues its relentless speed and density advancement. In the foreseeable future few barriers are predicted to limit this advancement. MCMs are another package technology evolving to further expand the packaging engineering toolbox. Proliferation of variations will continue and the complexity in choosing the “right” pack-

age will become greater and continue to drive interconnection technology. It must be emphasized that no one package or packaging technique can satisfy all applications. Each packaging approach has its advantages and disadvantages which must be considered in a system analysis of the complex technology, application requirements, manufacturability, maintainability, and cost tradeoffs typical of an electronic system as well as the unique, companyspecific practices (and biases) which exist in any company.

11.3 Integrated Circuit Processing It is important to understand the microinterconnect technology used in semiconductor packaging. Figure 11-1 depicts the major integrated circuit fabrication steps (for wire-bonded circuits) from the unprocessed wafer through the masking and wafer processing steps, also referred to as “front-end processing”, and the packaging steps from wafer mounting through sealing or encapsulation, the “back-end processi -.”. The wafer, with its hundreds or thousands of identical circuits, is mounted on a carrier with a heat releasable adhesive or wax. Wafer dicing is the sawing of the wafer to create the individual die,or chip, that will be packaged. Die attachment or die bonding is the physical attachment of the die to the package or substrate for mechanical attachment and heat conduction. Electrical contact is sometimes a function of the die attachment. The interconnection from the die to the package, leadframe, or substrate is shown as wire bonding (tape automated bonding steps are shown in Fig. 113) and interconnections at this stage are sometimes referred to as the “microinterconnect” to distinguish them from the interconnections external to a package. Note

11.3 Integrated Circuit Processing

61 3

AND LAYOUT

k4 MASK MAKING

& VERIFICATION

WAFER PRXESSING

PROBETEST

4 WAFER MOUWING

WAFER SAWlNODlClNG

DIE SEPARATION

OPTICAL INSPECTON

PACKAGES OR LEADFRAMES

DIE 83NDING

PRE-CAP OPTICAL INSPECTION

LOAD IN WAFFLE PACK

SEALING OR ENCAPSULATION

. IDS OR PLASTICS

FINALTEST

th it flip chip or solder bump microintercorinection does not use the die attach step fo the solder bumps serve to both attach and electrically interconnect the die. Sealing or encapsulation provides for the protecticln of the die from the environment. Note th 3 various points where test is performed. W tfers are tested in a probe test where eat:h individual die in the wafer is tested to

Figure 11-1. The major integrated circuit fabrication steps.

determine if it is functional. Typically only key DC characteristics are tested. Faulty circuits are identified with a spot of ink to indicate to subsequent assembly steps that the die is not functional. The final test, after all the packaging and assembly operations are complete, is the stage where full functional and AC testing and sorting for electrical and environmental performance is

614

11 Integrated Circuit Packaging

accomplished. Testing at intermediate packaging stages is not practical so that a great deal of value is added between the last two test steps. The packaging represents a significant portion of the overall cost of a circuit.

11.4 Die Attachment There are four primary ways for the physical attachment of the die to the package or substrate: alloy or eutectic bonding, solder attachment, low temperature glass frits, and adhesive bonding. Dice that have been separated from the wafer may be in a “waffle pack” (a plastic case with a square array of pockets with a die in each pocket) for manual bonding to a package or substrate or they may be mounted on a releasable carrier that keeps the dice in a precise, uniform position (as they were fabricated) after the dicing operation for use in automated attachment equipment. Typically the equipment is pick-and-place style with a heated vacuum tip collet that picks up the die and moves it to the package or substrate which is on a heated platen. The collet has a mechanical action scrubbing the die on the package surface and a eutectic bond is formed between the silicon die and the gold plating in the package die attach area. For a larger die, a solder or gold alloy preform in the form of a thin (about 1 mil, i.e., -25 pm) wafer is placed between the package die attach area and the die. The back of the die is metallized with gold and the die attach area is also gold. The assembly is heated in the 300°C range where the preform flows and attaches the die to the package. Low temperature glass flowing in the 300-400 “C range is also applied with ceramic packages. Epoxies are also used, particularly in hybrid circuits and MCMs. When epoxies are

used there are organics present in the package that may be of concern for some applications where contamination may result. The epoxies are typically one-part materials and may be filled with metallic particles for good thermal and electrical conductivities. One criterion for acceptable die attachment has been established for the amount of material around the perimeter of the die. Typically military packaging requires a good fillet between a minimum of three sides of the die and the package base. This has been established for mechanical attachment but does not necessarily give an indication of the overall integrity of the die attachment, which is important in high dissipation circuits. X-rays and acoustic microimaging are means to examine the die attach to determine void free attachment for good thermal properties (DiGiacomo, 1989). Diodes with dedicated leads for thermal sensing and thermal resistance test equipment are also used. All of these test or analysis techniques can add significant cost to a circuit and should be carefully applied to any design or product specifications. Thermal performance is, however, an increasingly critical parameter that affects reliability and electrical performance, so the extra cost of insuring die attach integrity may be well justified in high performance, high price circuits. See the section on thermal management (Sec. 11.11).

11.5 Microinterconnect Methods Figure 11-2 shows three microinterconnect attachment or bonding methods: wire bonding, flip chip (also called solder bump or “C4” for controlled collapse chip connection), and tape automated bonding (TAB). The left side of the figure shows the orientation of the die with respect to the

11.6 Wire Bonding

61 5

r WIRE

‘-LEAD

FRAMEJ

METALLIZATION

SOLDER BUMP

COPPER (GOLD) BUMP

COPPER LEAD

-,-

BONDING

PLASTIC CARRIER

Figure 11-2. Integrated circuit die interconnection alternatives.

package mounting surface. In wire bonding the die is oriented “face-up”. The input/ o ~tput ! (I/O) terminals, and active surface of the die are up and away from the package mounting surface and are connected to th.: die and package by thermocompression, thermosonic, or ultrasonic bonding. The solder bump technology has a “facedown” orientation, where the active surface with its plated bumps is down and ad lacent to the mounting surface. A solder bL.mped die is attached by reflow soldering to interconnect the die to the package. IBM developed the technology in the 1960s for high volume automated assemblv, and the technology is used throughout their product line. They recently began licensing their technology and it has been licensed to a number of semiconductor mmufacturers. TAB technology is primarily a face-up technology with bumps plated on the die terminal pads. The bumps are thermocom-

pression bonded to copper leads supported by a plastic film carrier.

11.6 Wire Bonding In wire bonding, thin gold or aluminum wires typically 0.7-1.3 mils (18-33 pm) in diameter are bonded to connect from the die 1/0 terminals to the package, lead frame, or substrate metallization. This is a sequential operation forming one bond at a time. Automatic bonding machines operate at a rate of five to seven bonds per second, a significant increase over manual operations. Wire bonding is the most popular interconnect technology used in the merchant market. Table 11-2 shows some typical wire sizes. The most popular are 1.0 mil gold and 1.3-mil-diameter aluminum wire (1 mil N 25 pm). Note the length restrictions. The maximum wire lengths are a

616

11 Integrated Circuit Packaging

Table 11-2. Wire bond mechanical and performance parameters. Material

Au Au AI SI A I SI

Wire diameter (in.)

Min. wire length (in.)

Max. wire length (in.)

Resistance per foot (a)

Max. current (A)

0.0010 0.0013 0.0010 0.001 3

0.040 0.040 0.020 0.020

0.080 0.1 10 0.120 0.150

13.5- 14.4 8.03-8.53 17.7- 19.5 1.3-1 2.5

0.200 0.500 0.125 0.250

Parameter

Wire bond a

TAB leadb

Aluminum

Gold

Copper

0.142 0.025 2.621

0.122 0.025 2.621

0.017 0.006 2.10

79.6 336.5

51.6 336.5

8.3 149.5

Electrical properties: Lead resistance (0) Lead to lead capacitance (pF; 0.008 spacing) Lead inductance (nH) Thermal resistance Lead conduction ( CjmW) Lead convection (free) ( C mW) a

0.001-in. dia. by 0.10-in. long wire bond.

0.001-in. by 0.004-in. by 0.100-in. long TAB lead (1 in. = 2.54 cm).

function of the ability of the wire to support itself, to maintain its integrity under shock and vibration, and to not short to adjacent wires. Also note the resistance values. Significant resistance (0.5 to 0.8 R is not unusual) and inductance (1-5 nH) can exist in the bond wires. This can affect electrical performance in current-carrying capabilities, signal propagation and circuit noise. Maximum-length considerations cause the package cavity size to vary based on die size, for if length exceeds acceptable limits, a smaller cavity size must be used. For power connections, internal bond sites and metallization may be wider to allow for multiple wire bonds and lower lead inductance and resistance. A variety of integrated circuit packages exist, which, from all external appearances, are the same; however, the internal details to accommodate different die sizes make them unique com-

ponents that the semiconductor manufacturers must stock. For power connections larger wire diameters (0.010 in = 0.25 mm diameter is not uncommon for power semiconductors) or multiple wire bonds and very wide internal package metallization are used to minimize resistance and increase current carrying capacity.

11.7 Tape Automated Bonding (TAB) In the early 1970s TAB was developed for automatic interconnection. Initially developed as a high-volume mass termination and production technique for small pin-count “jelly bean” (high-volume) circuits with 14-16 terminals, it is a technology that has become attractive for use with large-terminal-count die and for high performance circuits.

11.7 Tape Automated Bonding (TAB)

For TAB bonding the wafer must go through an additional processing step to “bump” the die 1/0 for thermocompression bonding and to avoid edge shorting. T! pically gold bumps or gold-over-copper bumps are used. The TAB process attaches a die to a tape or plastic film with an etched ccpper pattern, automatically taking it from the wafer and attaching it to the tape. Aatomated equipment makes the connections from the die to the tape, a process called “inner-lead bonding”. An advantage of this process is that the integrated circuits m.iy be tested or burned-in (subjected to te-nperature extremes that will cause those cixuits to fail that are not as reliable or prone to failure) prior to the expensive pitckaging and assembly steps. The “outerle,id bonding” process applies the tape-car-

ried integrated circuits (attached in the inner-lead bonding process) to the package or a multichip substrate, as would be done for hybrid technology or multichip modules. Figure 11-3 shows the basic process steps (Rima, 1985). Various types of lead formation can be employed. The term “spider bonding“ was used to describe this technology in its early development since the leads are formed away from the circuit in a spider-leg fashion where they can be attached by either solder or thermocompression bonding to a substrate. This lead form is now commonly referred to as “gull-wing’’ shaped leads. TAB is well-suited for high-performance multichip circuits for the advantages of high packaging density through the elimination of the individual IC package and

TAPE CARRIER WITH ETCHED LEAD PATTERN TEST IC WAFER WITH BUMPS ADDED TO BONDING PADS

INNER LEAD BOND TAPE CARRIER FABRICATION

I’

61 7

EXCISE, LEAD FORM, A N D OUTER LEAD UTEST AND BOND BURN I N HYBRID ASSEMBLY

Fixure 11-3. Tape automated bonding (TAB) process steps.

FINISHED HYBRID MICROCIRCUIT

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11 Integrated Circuit Packaging

package lead electrical degradation, with the ability to test and burn-in the IC prior to assembly. A related microinterconnect technology is “bumped tape”, where instead of bumping the wafer, bumps are formed on the tape. The bumps are needed for the bonding process and to ensure that the lead is above the surface of the die to minimize any possibility of edge shorting. Tape bumping eliminates the additional wafer plating steps required for TAB and the potential high-cost fallout, should damage occur at that process stage where all the value has been added to the wafer. Bumped tape uses a lower-cost wafer and less expensive tooling and has been successfully developed by some manufacturers, but is not a widely used technique. Another high density, fine pitch technique based on TAB technology is TapePack. Initial development was demonstrated with 20-min centerline terminal spacing, but the technology has the capability for finer pitches, to 10 mils (0.25 mm) or less. Tape-Pack uses TAB circuit fabrication, which is then overmolded with plastic to create a finished package. Leads may be formed in a number of configurations. This approach is an excellent example of high-density, fine-pitch packaging using TAB. It is significant to note that mechanical standards for testable metric TAB tape have been established by a joint activity of the EIA JEDEC committee in conjunction with their counterpart Japanese organization, the EIAJ EE13 committee. See Sec. 11.12, on package types, for information on the standards. There is more and more interest in chipon-board technology, particularly for MCMs with large-terminal-count TAB die, allowing testability, and by eliminating the IC package allowing circuits to be placed

much more closely together than packaged devices. Reliable, high-performance chipon-board technology becomes practical with TAB.

11.8 Flip Chip or Solder Bump IBM developed the controlled collapse chip connection (C4) process technology, more commonly refered to as flip chip or solder bump technology, in the early 1960s and has perfected this automated mass interconnection process. Of the total number of silicon interconnects used worldwide there are probably more solder bumps than any other type. Solder bumps have very short interconnections and the technique is more efficient in its use of silicon area because the full area of the chip can be used for 1/0 terminals. This is not possible with wire bonding or TAB because the pressures that are involved with the bonding process can change device characteristics if they are placed beneath 1/0 pads. Area array solder bumps are also more efficient for interconnection length and area, and all bonds are made in one reflow process step as opposed to the serial, one-at-atime, process with wire bonds. The process was not widely used outside of IBM, for the process controls are quite stringent, but IBM is now licensing the technology and it has significant advantages, particularly for high performance systems. Increasing use of solder bump interconnection is taking place and it is also being applied at the package level in ball grid array packages which will be discussed later. Tummala and Rymaszewski (1989) provide an excellent description of the solder bump technology.

61 9

11.9 Package Sealings

11.9 Package Sealing The last packaging process step is packape sealing. Ceramic packages use two basic processes: glass and solder sealing. Wzlding is used in very high reliability applrcations, typically with metal packages.

Figure 11-4 shows various ceramic package construction and sealing techniques. Glass may also be used to attach the package lid to the seal ring. Solder attachment of metal lids to a metallized seal ring is widely used in military applications. Metal or glass sealing results in a hermetic packKOVAR SEAL RING

ALUMINA

KOVAR

DIE

KOVAR OR OR ALUMINA

GLASS

(a 1

(b)

METAL (OR ALU .I1 IA)

METAL (OR ALUMINA) SOLDER

BRAZED

,(OR GLASS)

METALLIZATIO MULTILAYER E ALUMINA BRAZED LEADS

' METALLIZATION

(d)

(C)

DI'E

MULTILAYER ED ALUMINA

ALUMINA METALLiZATlON

Figure 11-4. Ceramic integrated circuit package alternatives: (a) CERDIP, (b) metal lid ceramic, (c) side brazed ceramic, (d) bottom brazed ceramic, (e) single layer chip carrier.

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11 Integrated Circuit Packaging

age, providing protection of the IC and its internal connections from the corrosioninducing moisture of the environment. Epoxy may also be used for cover or lid sealing and is used in some hybrid applications, however, while it makes it easier to repair/replace devices, this method does not reach the high degree of hermeticity of glass or solder sealing. In plastic packages, the die is attached to a lead frame, and plastic is molded to fully encapsulate the die. Plastic is molded around each die while in strip form and after molding, the package leads are formed, the packages separated and placed in tubes. Figure 11-5 shows a lead frame of a plastic package to which a die would be attached and wirebonded. Plastic packages are non-hermetic since the plastic materials allow the ingress of moisture. Some manufacturers use secondary protection materials such as silica gels or die coatings to protect the surface of the die from moisture. Although plastic packages have been continually improved and are very reliable due to improved plastics and die passivation (where the surface of the die is protected by glass or oxides or the gels, room temperature vulcanizing compounds, or other materials), plastic packages do not provide the long-term high-reliability of metal or ceramic packages. Some military applications are now using plastic packages in places they were

not previously permitted, and the military is moving toward much broader acceptance of plastic packaging due to economic pressure as well as improvements in materials and processes.

11.10 Rent’s Rule One of the primary driving forces of packaging technology is IC component density, not only in random logic but also in memory and microprocessors, and terminal counts have increased at a rapid rate and show no signs of slowing down. Increased IC component density, as measured by the number of components - logic gates per chip for random logic, storage cells for memory, transistors for microprocessors - will continue in the foreseeable future. As a result, the number of package I/O terminals has significantly increased to where microprocessor terminal counts are between 200 and 300 and moving into the 300 to 400 terminal range. (Current predictions are for a six million transistor microprocessor in 1995 and devices with terminal counts in the thousands.) Projections for general-purpose logic show terminal counts continuing to rapidly increase. Why is this? There is a relationship between the number of terminals and the number of logic gates in an electronic function. In the mid-1960s IBM studied their computer

Figure 11-5. DIP lead frame (front) and assembled, molded untrimmed lead frame (rear).

11.1 1 Thermal Management

lo$c packages on printed circuit boards ai-d developed a relationship called "Rent's rule" (Landman and Russo, 1971), a relationship between the number of pins p and th; number of logic gates g in the assembly. Tlie relationship has a proportionality fac.tor a multiplied by a number of gates raised to a power b (less than 1) in the form

p - = agb

(11-1)

Rvnt's rule was empirically derived for random logic on printed circuit boards but has also been shown to apply to individual serniconductor circuits. Bell Labs studies have shown the Rent's relationship that bejt fits their system designs to be p c z 4.5 go.5

(11-2)

Tliis is the number of signal pins needed to support the logic gate count and is typical of many others. The exponential relationship was also shown to apply to PWB routing density (Schmidt, 1981, 1982). Ujiisys studied some of their gate-array logic functions (Steele, 1981) and found the relationship that best fits their designs to be p

2.2 9 0 . 6

(11-3)

again, one that best fits their component, pr ,duct and systems designs ut that time. The power pin relationship will vary wiih circuit technology. For the Bell Labs model the estimator for the number of power pins required was 25% of the number of signal pins. Another more practical ruie of thumb is to estimate the number of pc wer terminals as a function of the number of active outputs; for example, one gr iund terminal for every three switching outputs has been used for ECL circuitry. Aiiother consideration which must be tailen into account to determine the numbei- of power terminals is the total current foi the package to meet DC drop/noise

62 1

margins; with high-speed logic the larger the number of signal outputs the more power terminals are needed for a larger number of outputs that switch simultaneously. The increased number of power terminals reduces the overall lead inductance, an important parameter for simultaneous switching, to minimize noise and ensure signal integrity, and increase performance. Additional power terminals may also be used for impedance control, where the power terminals serve as an impedance reference for the signals and maintain a uniform impedance across the package or connector interface. Lastly, system noise immunity must be considered, and a sufficient number of power and ground terminals must be provided to minimize power distribution losses and keep the noise levels within system noise limits. All of these considerations result in an increasing number of pins for logic devices.

11.11 Thermal Management 11.11.1 Thermal Resistance

Thermal resistance is defined as

(11-4) where TI is the average die junction temperature ("C), T2 the ambient air temperature ("C), P the dissipated power (watts, W), and e,,., the junction-to-air thermal resistance ("C/W). OJA is the summation of the thermal resistances from the die to the airstream which is removing most of the heat. It comprises the thermal resistances of the die (silicon), the materials used to attach the die to the package and the package (its base material and metallization in the thermal path). The thermal resistance from the

622

11 Integrated Circuit Packaging

junction to the case or exterior of the package is called ~ J C it; is a uniform characteristic of a package, or common reference point, for an integrated circuit manufacturer to specify thermal performance. Heat sinks and the means to remove heat external to the package are functions of individual designs and are difficult for an IC manufacturer to specify or control. 8 J C is what is typically characterized and specified by semiconductor manufacturers for a pack~ heatage. The user determines 6 , through sink and system-cooling design. If a heat sink is present this includes the material used to attach the heat sink to the package, the thermal resistance of the heat sink, and the effect of airflow over the package, so that

Junction-to-air thermal resistance is the summation of the individual thermal resistances of the elements that are in the thermal path of the package: 8jA=eD

+ 6jl +

6 p + 6 ~ 2 6H+853

where 8 j A is the junction-to-ambient thermal resistance of the assembly, 8, the thermal resistance of the die, Brl the thermal resistance of the die-to-package interface, 8, the thermal resistance of the package material, 8 J 2 the thermal resistance of the package-to-heat-sink surface, 6 , the thermal resistance of the heat sink material and 6j3 the thermal resistance of the heat sink to ambient air (film resistance). The thermal resistances are depicted in Fig. 11-6, a cross-sectional exploded view of a board-mounted package. Typical thermal resistance of DIP packages ranges

AMBIENT A I R

t HEAT SINK

EPOXY

CHIP CARRIER.

f-'J2 'T

SUBSTRATE CLIPS

EPOXY

THERMAL DIE

LID

(11-6)

PRINTED CIRCUIT BOARD

Figure 11-6. Integrated circuit package cross section and package component thermal resistances.

11.1 1 Thermal Management

623

,'3

0.128 X O 192 in DIE

42 m 10

250

500

750

1000

1250

1500

1750

2000

AIR VELOCITY, LINEAR FEET/MIN

Figure 11-7. Typical thermal resistance of a 0.950' square leadless multilayer ceramic chip carrier.

from 50 to 200 "C/W, depending on material , and construction. In Fig. 11-7 a plot of th 2 thermal resistance of a 0.950 in. (24 mm) square 68 1/0 chip carrier. Note that the e8ective thermal resistance, 8 J A , varies with th; airflow (air velocity is a measure of the ariount of air over the package measured in linear feet per minute, LFPM). For these chip carriers elAis about 25"C/W in still ail. At 1000 LFPM the thermal resistance is 'tbout 12"C/W. Keep in mind that each pa;kage type has a unique thermal resista ice. To determine thermal performance, one m 1st consider the package environment, nc't just the system environment. A piece of equipment might typically have a maxim im specified ambient operating temperature of 40°C. However, the air outlet temperature of the equipment will be subject to th: heat rise from devices beneath them,

and it is not unusual for an internal temperature rise to be 20°C so that the electronics near the air outlet will experience a 60°C maximum ambient temperature. If a package is dissipating 5 W (not unusual with today's circuits) and has a junctionto-air thermal resistance, 8 J A = 12 "C/W, the temperature difference from the junction to the ambient airstream will be 60°C ( 5 W x 12"C/W). The 60°C ambient air cooling the package is added to that of the junction temperature rise, resulting in a junction temperature of 120 "C. While this is within the limits of the operating temperature of most ICs, it is best to minimize the junction operating temperatures for improved reliability and performance. With higher temperatures and larger temperature differences, electrical parameters will degrade, and the non-uniformity of the thermal environment will cause wide differ-

624

11 Integrated Circuit Packaging

ences in the electrical characteristics (e.g., threshold level, noise immunity) of the IC so it is best to have temperature differences minimized. Thermal performance of packages is a major concern with new highspeed circuits and MCMs. Keep in mind that the die attach process has a primary effect on the thermal resistance of an integrated circuit package. 11.11.2 Cavity-Up/Down

Another important package characteristic relating to thermal performance is the orientation of the internal package cavity which is referred to as “cavity-up’’and “cavity-down”. Most DIP packages are in a cavity-up configuration. This terminology was created when chip carriers became popular since they offer the opportunity for mounting in both the cavity-up and cavity-down orientation because they are leadless and can be metallized to allow them to be mounted with the die cavity adjacent to, or away from, the mounting surface (or package seating plane). For air-cooled systems, the cavity-down configuration, where the die cavity is down and adjacent to the mounting surface, was developed. This arrangement allows the primary heat-dissipating surface, the back side of the die and the back of the package, to have direct conduction from the die surface through the die through the back of the package to the heat sink, as shown in Fig. 11-6. The cavity-down construction has been used extensively in air-cooled systems. Figure 11-8 shows a cavity-down PGA package configuration. PGA packages also have the capability of both orientations but the maximum terminal count is reduced in the cavity-down configuration. This is shown in Fig. 11-9. The cavity-up construction is still quite popular for indirect cooling. such as cold bars or surface

pads, to remove the heat through the base of the package into, or through, the mounting substrate or printed circuit board. Packages now are becoming more and more complex to where they must package die dissipating 30-50 W in a single chip package. Thermal performance has always been important in electronic packaging, but it is now essential to consider thermal performance in the earliest stages of system and packaging design for successful system application. Thermal design and performance can no longer be an afterthought.

11.12 Package Types As defined in the introduction, a package is “an enclosure for one or more semiconductor chips that allows electrical connection and provides mechanical and environmental connection” and can be of many forms each having numerous variations. There are many package standards and there is an active effort in the worldwide industry to minimize the number of package variations. The primary standards organization for IC Packages in the U.S.A. is JEDEC.

11.13 JEDEC JEDEC, formerly the Joint Electron Devices Engineering Council, is a function of the Electronics Industry Association (EIA) and defines the microelectronic standards in the U.S.A. JEDEC currently has 15 committees that are involved in all aspects of microelectronics and semiconductor technology standardization, specializing in digital, bipolar, MOS, linear memory, gate arrays, mechanical standards and other areas. The EIA/JEDEC JC-1 1 Committee on Mechanical Standardization of

11.13 J E D E C

625

Figure 11-8. A cavity-up pin grid array package with a double bond shelf,

Figure 11-9. Pin grid array double bond shelf packages: cavity-up (center) and cavity-down (left and right).

Solid State Devices is responsible for micrc )electronic package outlines and has developed standards for all package types. This committee is the recognized U.S.standa rd organization for packages and represeIits the United States in the International Elt.ctrotechnica1Commission (IEC) (Freedm:.n, 1993). The JC-11 committee has an ongoing standardization effort for packages in both ceiamic and plastic construction and in 1938 pioneered international coordination to minimize package proliferation by estaldishing an ongoing relationship with its co Linterpart Electronics Industry Association of Japan, EIAJ EE-13 committee.

The JEDEC JC-11 committee has attempted to minimize the variations and has provided excellent documents defining the mechanical outlines of packages in Publication 95, JEDEC Registered and Standard Outlines for Semiconductor Devices, and package design guidelines in JEDEC Standard No. 95-1, Design Requirements f o r Outlines of Solid State and Related Products. The JEDEC JC-IO Committee on Terms and Definitions has developed a number of documents on symbols, terms and definitions for semiconductor and optoelectronic devices, two of which are of significance to packages: JEDEC Standard No. 99, Glossary of Microelectronic Terms,

626

11 Integrated Circuit Packaging

Definitions and Symbols and JEDEC Standard No. 30, Descriptive Designation System for Semiconductor-Device Packages. JEDEC is moving toward full adoption of the alphanumeric package designations described in JESD-30, which includes in the designation details of design and construction. As they are not fully adopted, they have not been included herein (JEDEC Standard 95, JEDEC Standard 30). Another useful reference defining package types is the US. Military Standard MIL-STD-1835, Microcircuit Case Outlines and the Electronic Packaging, Microelectronics, and Interconnection Dictionary (Harper and Miller, 1993). The following descriptions are based on these references; however, in many cases there are minor differences in the “standard” definitions in these documents, in which case a description has been created from them or the most appropriate description selected and referenced. The following descriptions of package types are for the most popular existing and emerging types and do not cover all possible types and variations. They can be found in the JEDEC Standards.

11.13.1 Dual In-Line Package A dual in-line package is a rectangular package with two parallel rows of terminals, or leads, that are positioned in two straight rows on the sides of the package. The terminals are oriented perpendicular to the package seating plane for insertion into interconnecting holes in a substrate. Figure 11-10 shows a variety of DIPS in a printed wiring assembly.

11.13.2 Flatpack A flatpack is defined as “a low-profile

package whose leads project parallel to, and are designed primarily to be attached parallel to, the seating plane. The leads typically originate from either two or four sides of a package. The body of the flatpack is similar to that of a chip carrier. Leads may be formed generally away from the package body. If the leads are formed back towards the package body, the correct term is “chip carrier” (JEDEC Standard 95, JEDEC Standard 30). The flatpack was one of the earliest package types and a long-time military use package (with

Figure 11-10. Through-hole mounted integrated circuit packages.

11.13 JEDEC

627

leads on two sides). With the advent of high density surface mounting the quad flat pack (QFP)with leads on all four package sides, in both English and metric spacing. became popular for high lead count very fine pitch surface mounting for its ease of membly and inspectability. 11.13.3 Chip Carrier This term is sometimes used to describe an! package which contains a chip but is more properly used to define a specific Invented in the late 1960s in package cer

Figure 11-11. A typical leadless ceramic chip carrier package.

Figure 11-12. An array of leadless ceramic chip carriers: (a) cavity side, (b) input/output side.

628

11 Integrated Circuit Packaging

Figure 11-13. Plastic leaded chip carriers.

leadless chip carrier or LCC. Figure 11-13 depicts a plastic leaded chip carrier or PLCC which has its leads formed in a Jlead configuration for surface mounting. This is now by far the most popular type of chip carrier due to the low packaging cost through the use of plastic. 11.13.4 Small Outline Package

The small outline or SO package, also referred to as an SOP or SOIC, evolved from the small outline transistor (SOT) package, one of the first surface mount packages for active devices.The SOT package was a plastic package with three terminals formed out from the body and was developed to overcome some of the problems in handling chip transistors. In the early 1970s Philips conceived the SO package with gull-wing shaped leads similar to a flatpack for larger terminal count devices. Typically it was used for 8 through 20 terminal devices and as die sizes increased the body size and terminal count increased to 40 leads (Amey, 1984). The package is defined by Harper and Miller (1993) as “a small rectangular integrated circuit surface mount electronic package with leads on two sides and with 1.27 mm, 1.O mm, or 0.85 mm spacing”. The package

footprint is defined by the forming of the gull-wing-shaped leads. Figure 11-14 shows a typical SO package. Another package style is the SOJ package, where the leads are formed in and beneath the package body in a “J” configuration as is done in the PLCC. With the J-lead the footprint is dictated by the body of the package. This has become a popular package for memory applications. Separate and distinct standards exist for both the SO and SOJ package styles. 11.13.5 Grid Array Packages A grid array package is defined as “a low profile package whose terminals are located on one surface in a matrix of at least three rows and three columns; terminals may be missing from some row-column intersections” (JEDEC Standard 95, JEDEC Standard 30). The most widely used grid array package is the pin grid array (PGA) first used in high volume by IBM in the 1960s. In the mid-to-late 1970s, as semiconductor terminal counts increased beyond that which was practical for the DIP, chip carriers and PGA packages became more widely used in the merchant market. In 1979, IBM dramatically demonstrated the capability of the PGA

Figure 11-14. Small outline (SO)packages.

11.13 JEDEC

Fiyre 11-15. A single bond shelf cavity-up pin grid ar 3y package with a wire bonded die.

st ,le in a 1800-pin, 133-chip multichip m ,dule, the thermal conduction module, fiIjt applied in the 3081 System (IBM, 1582). A formal definition of the PGA is “( I ) A predetermined configuration of many pl ilg-in electrical terminals for an electrl mic package or interconnection application. (2) A package with pins located over nedrly all its surface area. (3) A square form t t package with leads distributed over th: bottom of a grid pattern at 0.1 inch (2 54 mm) or finer pitch” (JEDEC Stand: rd 95, JEDEC Standard 30). A typical PC ;A is shown in Fig. 11-15.

629

Different names have been used to describe a grid array package which does not have pins: pad grid array, land grid array and leadless grid array have all been used to describe the same type. Land or leadless grid array (LGA) is preferred to avoid the confusion inevitably resulting from abbreviation where the two unique types would both be PGA if the term “pad” were used to describe the absence of pins. LGA packages have been developed for commercial applications and their improved electrical properties over the equivalent PGA packages have been demonstrated (Goodman et al., 1993). Recently, the ball grid array (BGA) package has been developed which is a LGA package with solder balls for package terminals. The use of compliant solder terminals allows the use of organic substrate materials or for the package base and plastic encapsulation to protect the die. It is similar to, and compatible with, the solder bump or flip chip microinterconnect technology previously described. A typical configuration of this style/type is shown in Fig. 11-16 as it has been implemented by Motorola with the trade name OMPAC. While at this time the BGA is a newly emerging style/type it has the potential to be a widely used package for its advantages

Fit ure 11-16. Cross section of a ball grid array (BGA) package.

630

1 1 Integrated Circuit Packaging

of very high density interconnect at the microinterconnect and package level, surface mounting with TCE compatibility with organic substrates, and low cost through the use of organic materials (Houghton, 1995). 11.13.6 Hybrid Circuit Packages

Figure 11-17. Metal case hybrid circuit packages: (a) with ceramic substrate mounted, (b) high power with large diameter high current leads, (c) isolated RF input, (d) plug in or through-hole package with nailhead bond pedestal leads.

Multichip hybrid circuits have been used in electronic packaging for more than 30 years, typically in military applications; however, they have also been used quite effectively in cost-driven commercial applications (Amey, 1990,1992). Both metal and ceramic packages similar to, or interchangeable with, the types previously described have been widely used for packaging hybrid circuits. Primarily custom packages, there are thousands of variations available. In addition to multichip, high performance, high reliability applications they are used in microwave, electro-optic and high power applications. Typically the metal hermetic packages are made of Kovar with glass-tometal seals for lead passage through the metal body. Steel bodies and base materials of copper, steel, or molybdenum exist for high power dissipation circuits. Various internal lead configurations are available to meet wire bond or lead attachment requirements. Flat lids, stepped lids, or “dished” or “cup-shaped’’ lids can be used

11.14 Package Attachment

631

Figure 11-18. An all-ceramic hybrid package.

and they can be solder sealed (using prefo-ms), brazed or welded for hermeticity or epoxy sealed if a high degree of hermeticity is not required. The packages and components are usually gold-plated for bonding arid sealing. Figure 11-17 shows four typical metal hybrid circuit packages. Not depicted but also available are flat platforms or headers for substrates or single die packaging. Multilayer cofired ceramic consti uction can be used with mechanical interchangebility for essentially all of the types of metal packages. Figure 11-18 shows a typical ceramic hybrid package. The tradeoffs in the selection of the appropriate constr uction for an application are beyond the scope of this chapter. See Bieber (1989)and Leedecke (1989) for further information. Table 11-3 summarizes the package types and their variations as they existed in 1994. Note that presenting a summary of this kind is risky for it is constantly changing, but this shows the many, many options and choices faced by the designer and provides a starting point for package selection.

11.14 Package Attachment The soldering of grid array packages to printed wiring boards or substrates violates an old axiom, “If you can’t see it,

don’t solder it”. LGA and BGA solder joints are blind and PGA solder joints can only be seen from the solder side of the assembly whereas perimeter package connections can be visually inspected in full for solder joint quality and the absence of chemical contamination. In through-hole soldering, poor quality solder joints can still occur even if the joints appear to have good filleting on the solder side of the board. The solder fillet connecting the board to the pin can fill and tent the lower portion of the hole while the upper portion of the hole/pin connection may not be soldered. Poor wetting of the solder due to heat transfer problems, poor plating or cleaning of the package pin or poor plating or cleaning of the printed wiring board hole can all contribute to inferior pin-to-hole solder joints. These will typically not evidence themselves until they are subjected to thermal or mechanical stress from thermal cycling in equipment operation or in board flexure due to handling or mechanical vibration/shock. Full visual inspection of a solder joint insures the highest quality. And yes, reliable grid array solder joints can be produced in the factory environment using special equipment and techniques; however, it is much too much to expect reliable field soldering of packages

Table 11-3. Integrated circuit package types a n d their variations.

ru Package Type

Acronym

Terminal count

System

Pitch

English Metric Dual in-line package Flat pack Chip carrier Leadless chip carrier Plastic leaded chip carrier Grid array Pin grid array Leadless (land) grid array Small outline or small outline IC Small outline J lead Tape automated honding In-line packages Single in-line package Zig-zag in-line package Quad in-line package Single in-line memory module Quad flat pack Molded ring carrier Fine pitch quad flat pack Thin quad flat pack Shrink small outline package Thin small outline package Thin shrink small outline package Grid array Ball grid array Plastic ball grid array TAB ball grid array Surface mount pin grid array Metric TAB Multichip module MCM pin grid array MCM ceramic quad flat pack Shrink DIP Memory cards Large 1/O SIMMs

DIP FP Cc' LCC PLCC

16 to 156 18 to 124

PGA LGA SO o r SOlC SOJ TAB

81 to400 81 to400 8 to 40 24 to 44 14 to 400

SIP ZIP QUIP SIMM (SIP)

I I to40

QFP TAPE PA K FQFP TQFP SSOP TSOP TSSOP BGA PBGA ATAB SMTPGA TAB MCM MCM PGA MCM CQFP

SIMM (SIP)

4 to 64 14 to 64

16 to 40

14 to 64 30 24 to 340 64 t o I080 64 to 376 32 to 256 8 to 64 24 to 56 8 to 64

English (in)

Perimeter

Metric (mm)

0.1 0.05

e 0

e e

0.1 0.1 0.05 0.05

0 0

lead

pull

e e

0 0 0 0 0

e e 0 e

0.025

0 0

Pad J

.5. .65, .8, 1 .3, .4, .5, .65 0.4, 0.5 .4, .5, .6S, .8, 1 0.4, 0.5, 0.65 0.5 0.4, 0.5, 0.65

0 0 0 0

81 to 1936 260 to 1080 14 to 52 60,68, 88 72, 76, 80

1. 1.27, 1.5 1.27

e 0

0.15 to 0.5

.4, .5, .65, .8

0.1

0 0 0

0.05

0.07

1/I .27

0.05, 0.1

Note: Many variations in the above types. Common/typical shown. Preliminary information included. Trademark.

3 Irt

eJ a

-2

E. '0

0 16 to 2401 256 to 961 288 to 1680 96 to R72

lead Pad gull J lead (flat) lead lead lead pad gull pad/lead gull gull gull gull gull

e e e e e

e e

-A

ii;

0 0

0 0.1 0.1 /0.05 0.1 i0.05 0.1 0.15 to 0.0s

Array Terminal form

2-Sided 4-Sided Staggered

0.04.0.05 0.05

Terminal arrangement

solder ball solder ball solder ball lead solder ball lead lead (flat) lead socket padjlead

nl 5. 3

633

11.15 Electrical Considerations

with hundreds of terminals without visual in cpection. This requires special consideration in choosing a grid array package as a field replaceable unit (FRU) in a system.

Table 11-4. Typical dielectric constants of some popular packaging materials. Material

Dielectric constant ~

11.15 Electrical Considerations Many of the package considerations and tr,ide-offs are a function of surface mount technology which offers many interconnection advantages over through-hole technology. However, the smaller overall size of large terminal count fine pitch packages bccomes a significant advantage if highspeed logic circuits are used in applications where a number of single chip packages form the system or when a large multichip substrate is used. In these cases the substi-ate material can have a significant effect 011 electrical properties. The delay effect of the package material can exceed the typical delay of a circuit element. The relative dizlectric constant of the material, E , , is the property which determines the line capacita nce; the higher the dielectric constant, the greater the line capacitance. Typical dielectric constants of some popu l x electronic packaging materials are summarized in Table 11-4. (Note that the dielectric constant can vary with a number of conditions such as teinperature, frequency, fillers, curing properties, etc. The values shown are typical.) The higher the dielectric constant, the greater the signal propagation delay. This can best be seen in curves showing the cbange in propagation delay with dielectric constant, E , . The equations for propagation delay for both stripline and microstrip interconnection used for these examples were developed by Motorola in their MECL System Design Handbook (Blood, 1988), an excellent reference for high performance design.

Teflon Kapton Valox Ryton FR-4 epoxy glass Low temperature cofired ceramic Low K thick film dielectric Beryllia ceramic Alumina ceramic

2.1 3.5-3.7 3.7 4.0 4.8 4.8 5.2 6.5- 6.9 8.8 -10.1

For microstrip, which describes a signal line separated from a ground or impedance reference plane by the dielectric, with the signal line and dielectric surrounded by air, as shown in Fig. 11-19, the equation for the propagation delay t,, in nanosecondsjfoot is t,, (nsjft)= 1.017 40.475 E , + 0.67

(11-7)

(1 ns/ft = 3.28 nsjm.) For stripline, which describes a signal line imbedded in the dielectric between two impedance reference planes, as shown in Fig. 11-20, the equation is t,, (ns/ft) = 1.017

der

(11-8)

Note that the propagation delay in both configurations is a function of the dielectric

G rou n d

-I

r///////A

Figure 11-19. Microstrip configuration.

634

1 1 Integrated Circuit Packaging

-I

I-

Ground P l a n e S t p i p Line

Ground Plane

Figure 11-21 (Amey, 1981 b) shows the variation in propagation delay in nanoseconds/foot (1 ns/ft z 3.3 nsjm) with dielectric constant for microstrip and striplines. Figure 11-22 shows the propagation delay in nanoseconds vs. signal length in inches for three values of dielectric constant. In assemblies of multiple circuit packages, it is not unusual to have net lengths (the length of the total interconnection between packages) both within the package and the next level interconnection of 6 in. to 12 in. (15-30 cm), and similar or longer lengths with large MCM packages. It becomes important to minimize the interconnection path length in the high dielectric constant material, which can be a significant part of the delay in the circuit element. High speed circuits with propagation delays of less

constant only, it is not a function of line width or spacing. The microstrip configuration is typical of external signal lines on packages (or higher levels of interconnection) while the stripline configuration is typical of internal, buried signal lines. The microstrip configuration is inherently faster due to the air dielectric on one side of the line and the absence of a second impedance reference plane in close proximity to the line (lower capacitance). If coatings such as solder masks or conformal coatings are used over signal lines in the microstrip configuration, the equations must be adjusted for “coated microstrip”, which will result in propagation delay somewhere between the microstrip and stripline values. Typical solder masks will increase delay by about 7-10% (Belopolsky et al., 1991).

0.5{ 0 1 . 2

16 18 20 DIELECTRIC CONSTANT e, 12

Figure 11-20. Stripline configuration.

’

Figure 11-21. Interconnection propagation delay variation with configuration and substrate dielectric constant (1 nsjft = 3.3 nsjm).

1 1 . I 6 Other Package Selection Considerations

635

Figure 11-22. Interconnection propagation delay variation with configuration, substrate dielectric constant and interconnection length.

INCHES

th in 200 ps are now available. If, for examplrt, all interconnections were alumina cera nic with a dielectric constant of about 10 the delay contribution of 6 in. of stripline in1erconnection would be, from Fig. 11.22, l.fI ns. If the same interconnection were in y printed wiring or low temperaep ~ x glass tu e cofired ceramic with a dielectric const; nt of about 4.5, the delay would be 1.1 ns. This saving of 0.5 ns is equivalent to 1 or 2 additional logic circuits in the net. TI-is can be particularly significant in a critical path in high speed applications. As typical net lengths increase and/or circuit de ay decreases, the delay savings through thi use of low dielectric constant interconne ition material become more significant. If ceramic packages are used for their su ,erior properties for semiconductor proce, sing (attachment, bonding and thermal performance), it is important that their size be minimized to minimize delay (unless onz is in an all-ceramic system). Epoxy glass printed wiring is widely used for the next level of interconnection. The use of a sm aller ceramic package, even if the board focltprint remains the same due to the de-

sirability of the 0.1 in. or 0.050 in. grid for testability, is still an advantage, for the electrical signals are propagated in a faster media for a larger percentage of the total net length. If smaller interconnect grid spacing is tolerable, there are even further advantages with the smaller package size because higher packaging density can further reduce net lengths.

11.16 Other Package Selection Considerations The major considerations distinguishing each package type have been reviewed. There are a number of additional factors which may or may not be significant depending on particular applications or manufacturing preferences. These are briefly stated without discussion and should be considered in the selection of a packaging t Y Pe.

1. Many times new package types are initially implemented in ceramic. They then have a high potential for future cost re-

636

11 Integrated Circuit Packaging

ductions through the use of plastic and selective plating technology. For example, packages can be further reduced in cost through the use of a non-noble package plating and integrated tape automated bonding technology. 2. The smallest package size minimizes degradation of critical electrical parameters. Lead resistance, capacitance and inductance are all minimized in smaller packages and lead length uniformity is improved. Also, lead resistance is lower for certain constructions having external, plated circuit paths. 3. Leadless packages can utilize “soft” interconnection for testing of assemblies prior to soldering. Elastomeric connector elements have been used for this testing (Beaman et al., 1993). 4.Packages with large terminal counts require low insertion force (LIF) or zero insertion force (ZIF) connectors for testing and sometimes even for production use. The insertion of hundreds of pins into printed wiring board holes requires tight tolerance controls and insertion aids. 5. Simple board test systems exist for 0.1 in. grid terminal spacing. Tighter grid spacings require advanced, more costly test techniques. 6 . Some packages may be thermally oriented in both the “cavity-up” or “cavitydown” configuration, without any reduction in terminal density. Grid array terminal count must be reduced (or the package size increased) if cavity-down mounting is used. Cavity-down PGA package orientation requires bonding within a nest of pins which is practical but may require bonding machine adaptations. 7. Leadless packages offer high terminal density with the largest possible cavity size or circuit area for cavity-down

mounting. This is important if multichip circuits are used in the packaging system.

11.17 Cost Valid package cost comparisons are difficult to obtain except in very specific cases comparing direct functional equivalents. Cost comparisons must also be made at the proper level. It can be very misleading to make a packaging decision based on one characteristic, for example, terminal spacing or the basic package cost, when performing a packaging trade-off. Yield losses in assembly operations and field repair costs directly attributed to the package must also be considered. Even though one type of package may be a less costly component, the costs imposed at the next level (or higher levels) of interconnection may exceed any savings at the component level. The increased cost of new technology over existing technology must also be understood and cost comparisons made at the point in a program where volumes/costs are realistic for comparison. Projections of the future extensibility of a technology or component style to meet future needs must also be considered. Typically a one-timeuse new component or technology is not cost effective. The costs for the various alternatives should be evaluated for each application for there are many time dependent design, material and volume variables affecting cost. The cost of the yield losses due to the package in semiconductor assembly operations must be considered in the basic package costs. Packages with leads introduce an additional source of yield loss through the die attachment, bonding, sealing, test and handling operations. Even though the percentage of loss is small, it can result in

11.18 Multichb Modules

si :nifkant dollar losses the further the falloiit occurs in the manufacturing process. T ie larger the number of terminals on a pilckage, the higher the probability that an 01 herwise good semiconductor or MCM cb n be rendered unusable due to the irrepaiable damage to a single lead. This is an aclvantage of leadless packages over leaded packages for this source of package failure is climinated. If leads are necessary, leadless piickages, repairable substrate clips and t h z “leads last” concept, that is, putting the le ids on at the last possible stage of assemblv to minimize lead damage, should be ccsnsidered (Amey, 1981c).

1 1 .18 Multichip Modules 11.18.1 Introduction Multichip packaging (MCP) is not new. It has been widely applied in both milita ry and commercial applications for over 2‘ years. Ceramic multichip modules (hlCMs) have been used as a primary systens packaging technique since the late 15 70s. IBM developed and announced the pi zviously mentioned thermal conduction module (TCM) in 1979. This large ceramic ms)dulehas been widely applied in their high performance products. The technology was extended for air-cooled systems ar d a new generation of improved ceramic m iterials have been developed (Tummala ai,d Rymaszewski, 1989). The technology is now being offered to the industry and is in volume production. The technique elimin.tted an entire level of packaging and exer iplifies the complex mechanical, electricii I, thermal and repair tradeoffs involved in MCP. The basic design still represents st Ite-of-the-art ceramic and packaging te bhnology.

637

There are numerous other examples of MCP applied over the years in commercial and military products using multilayer thick film and cofired alumina interconnections in applications with solder bump, TAB, and wire bond microinterconnects. Thick film technology, as an interconnecting substrate for high density packaged surface mount ICs (ceramic leadless chip carriers and flatpacks), was pioneered by and is widely applied in military system packaging. These applications have been widely publicized and described in the technical literature. Amey (1990, 1992) describes a number of these technologies and applications. Useful background and current information on MCM technology is provided in the proceedings of NEPCON (1989-1996), IEPS (1988-1996), IEEE (1996), ISHM (1988-1996) and International Conf. on Multichip Modules (19921996); these are primary sources of information to stay current on MCM technology, which is rapidly changing.

11.18.2 Multichip Packaging Considerations There are many choices and design trade-offs in the consideration of MCMs for system packaging. The following is by no means a comprehensive treatment of each of the design considerations but is intended as a summary of major packaging and material issues. The references should be consulted for an in-depth treatment of these areas. Note that all areas are highly interrelated.

1. Substrate choice; The options are numerous: all ceramic (high temperature cofired aluminia, low temperature cofired ceramic or Green Tape, beryllia, aluminum nitride, etc.), all organic (thin FR4 printed wiring, thin-film polyimide, etc.), silicon, silicon-on-ceramic

638

11 Integrated Circuit Packaging

and all combinations of the above. At this time, the most popular choice for high density, high performance applications is thin-film copper on polyimide on a ceramic substrate or “platform”. In addition to the many design and performance trade-offs, the choice of substrate is highly dependent on size and process considerations. The patterning method chosen may dictate maximum size limits of the MCM due to equipment types or the ability to image/resolve features with the required precision. 2. Die attachment: Integrated circuit die larger than 1/2 in. square and dissipating more than 30 W are projected (Buschbom, 1988). This large die size and dissipation poses attachment problems for mechanical (shock, vibration), thermal (uniform, thin, void free die attach) and process (stable over wide temperature range) reasons. Attachment techniques and materials for ceramic and plastic packages are well understood while attachment to organic substrates requires new materials and process development. 3. Microinterconnect method: Signal interconnections or bonding of the die using wire bond, TAB or solder bump connections have all been applied in MCMs. While having the obvious major influence on electrical and thermal issues, the areas of IC availability, test at both the die and substrate level, process yield, and substrate compatibility are also major considerations in the choice of a mirointerconnect method. 4. Interconnecr density: Interconnecting substrate feature sizes (line width, minimum spaces, via size, 1 / 0 size), the number of metallization layers consistent with the circuit technology, and mechanical sizing to meet system needs

must be selected based on both existing requirements and future needs. With higher speed circuitry, controlled impedance connections are becoming necessary even over relatively short intra-module distances. This further complicates signal interconnect design and density requiring an increased number of metallization layers. Design, as well as process capability, plays a major role in cost effective high density interconnections. 5. Interconnect noise: As circuit speeds increase and circuit rise times become faster, coupling between circuit signal lines becomes greater. Circuit density (line spacing), the microinterconnect method and maintaining a uniform thermal environment are critical to noise control. Low dielectric constant materials play an important role in this area. A good treatment of the issues has been given by Balde (1987). 6. Interconnect delay: Again, as a result of faster circuits, the time for signals to propagate from one circuit to another has become a significant portion of system speed, limiting overall system performance. As has been discussed, the time-of-flight delay of signals is a direct function of only the dielectric constant of the interconnecting media. Alumina and conventional thick film ceramic materials have a relatively high dielectric constant, E , = 8 to 10, and are generally not thought suitable for very high performance applications. For many applications a dielectric constant of 4-5 (typical of FR4 printed wiring and glass ceramics) is found to be effective for projected needs and only the very high performance applications require E , = 3.2 and lower, typical of polyimide thin-film interconnection. As in the other considerations there are many trade-offs.

11.18 Multichip Modules

I. Signal termination: High speed circuits using controlled impedance interconnections typically require some form of line termination to minimize reflections, maintain signal integrity and control noise. This is true for both CMOS and bipolar circuits. The need for termination is circuitry, signal net configuration, and length dependent. With high speed bipolar circuits parallel resistor termination is typically used, and close proximity of the termination to the circuit is necessary. Integral termination resistors on an MCM substrate are desirable with a minimum impact on packaging and routing density. Products and material systems have been developed for printed wiring [IPC Design Guide, Resistors (Polyfunctional Laminate)] and ceramic substrates (Brown and Shapiro, 1993). The ability to change signal net terminations is also an important consideration in that logic changes can effect signal net configurations requiring addition and deletion of terminating resistors. 8 Power distribution: High speed ICs with high levels of integration have high power supply currents. While the current may be distributed through many leads, the high current levels place special demands on MCM metallization. High conductivity conductors are essential and connection resistances must be minimized. More power planes are typically required in that some circuitry has separate power distribution for output (switching) circuits and the internal logic. The output circuit distribution system may be separated from logic power distribution and impedance reference planes for improved noise control. This adds cost and complexity. 9. Power system decoupling: High speed circuitry requires power supply decou-

639

pling (or filtering) in close proximity to circuit outputs to minimize the effects of noise in the power distribution system coupling into output circuits thereby causing unpredictable logic operation if switching threshold levels are exceeded. Capacitors with a high resonant frequency are required and typically multilayer ceramic construction surface mount chip capacitors are used in high performance applications. The capacitors also minimize the effects of lead inductance in the power and output leads and serve as a localized source of current for very fast output switching circuits. As in the case of resistors, products and material systems to integrate the decoupling capacitors in the substrate have been developed for both printed wiring (Wang, 1993) and ceramic substrates (Drozdyk, 1993). IO. Thermal management: Individual die dissipations of 30-50 W, individual modules dissipating kilowatts, the need for low junction temperature for reliable long-life operation and maintaining a uniform thermal environment to minimize electrical performance variations (noise, switching speeds) are placing severe demands on thermal management. High speed circuitry and high density packaging have significantly increased volumetric thermal densities requiring novel cooling methods and cooling systems with high heat removal capacity. High thermal conductivity ceramics such as aluminum nitride for module platforms, high conductivity heat sink and attachment materials, liquid-cooled heat sinks and miniature cooling fans to mount directly to a package or substrate are being developed to meet MCM needs. Package sealing methods and materials for large area/long perimeter sealing and pre-

640

11 Integrated Circuit Packaging

serving seal integrity over a wide temperature range is also a thermal concern. Design techniques for improved thermal performance, (e.g., thermal vias or heat-spreading layers) may be necessary for uncased and packaged devices but their use is at the “expense” of routing density, packaging density and cost. Thermal vias offer a significant advantage in that, once characterized, they may be “personalized” to each IC so that a large number of vias are placed under high dissipation devices and a smaller number, or no vias, under low dissipation devices to maintain a uniform junction temperature and its benefits of more uniform delay and noise minimization (Poulin and Nguyen, 1993). The thermal/mechanical/electrical/cost tradeoffs are much more complex in high performance multichip packaging than in conventional single chip/printed wiring designs. 11. Next level interconnection: The type of interconnection from the module to the next level of interconnection is critical to overall performance. Area vs. perimeter terminals, through-hole or surface mount interconnection, leaded or leadless, soldered or separable connections are all practical and employed in MCMs. In addition to the usual tradeoffs, one must carefully consider MCM factory test methods and the system and MCM maintenance approach including the potential for damage to the module or next level interconnection during change and repair. The cost of spares (both unit and pipeline costs) and field test/fault isolation capability is also important in the choice of interconnection from MCM to the next level (Grabbe et al., 1993). 12. Change and repair: In all but the simplest modules or those with very regu-

larized interconnections (e.g., memory modules) the provisions to change interconnections to correct logic errors, replace failed circuits and/or remove terminations must be provided. Designs should allow for spare terminals, spare termination sites, and spare decoupling sites for potential future use. Even with today’s high degree of simulation, test and design aids, circuits, modules and systems which have millions of gates can have undiscovered bugs (Wall Street Journal (1990)) which must be corrected. While it is possible to correct on-chip IC logic errors (Florod Corp., 1991; IBM Microelectronics, 1993), it is still highly advanced technology, however, it is possible to have practical, production-worthy high density techniques for MCM change and repair, the details of which are described below and by Florod Corp. (1991) and IBM Microelectronics (1993).

11.19 Change and Repair In April 1980, Sperry UNIVAC Computer Systems (now UNISYS) announced the System 80, a mid-range commercial computer system which used thick film ceramic hybrids (which were, in today’s terms, multichip modules) and custom VLSI. This was UNIVAC’s first application of thick film technology as a basic packaging technique for commercial computer systems. The modules packaged up to 16 of the 10 k ECL family of integrated circuits in a 1.35 in. (34mm) square module meeting JEDEC standard outlines. The substrates were typically three conductor layer thick film (up to five layers were required on some modules) with 64 integral resistors for the termination of internal ECL nets

11.20 Change Bars

64 1

Figure 11-23. A thick film ECL digital logic module with interconnection change bars.

and internal chip capacitors for power supply decoupling. The cavity-down modules used heat sinks in an air-cooled system and were capable of dissipating up to 7 W (see Fig. 11-23). These thick film modules were used in volume production and about onehalf of the 35 modules used on the CPU board were ultimately converted to ECL macrocell gate arrays. This application is a good example of multichip module design issues and ceramic solutions in cost-performance commercial computer systems (Amey, 1981 c; Freedman and Short, 1981). A key feature of these modules was the design techniques for change and repair. The techniques discussed are not necessary for designs with very few circuits, which have an easily testable and predictable logic configuration, or for memory boards or similar applications which have a very regularized interconnection structure with little possibility of future change or repair. However, even with extensive modeling and computer-aided design the complexity of large random logic structures (that is,

logic systems with the number of gates in the 10’s or 100’s of thousands or those with a large number of packages) makes it impractical to fully model or test all the conditions that the logic will experience. Change is a way of life in the initial system test and prototype debugging as well as in early production. For complicated interconnect systems, one must have the means to change and repair without having to update and reroute the circuit interconnection, replot and fabricate a module every time a change occurs. The repair technique must also have electrical and mechanical reliability suitable for field use and quality comparable with the initial interconnections.

11.20 Change Bars In one implementation, the multichip thick film circuits were capable of factory change using small ceramic “change bars” and wire bonding to externally reconfig-

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11 Integrated Circuit Packaging

ured nets. The die-to-substrate interconnection was conventional gold ball chipand-wire. The die was epoxy die attached and wire bonded to the substrate. Epoxy preform cover sealing was used to facilitate change and repair. If a change was required to the interconnections in a logic signal net, the wire bonds were pulled off of the die and substrate. This isolates the die from the signal net in the multilayer substrate. Thick film metallized alumina change bars, 15 mils (0.38 mm) thick, metallized with a 10 mil (0.25 mm) wide thick film gold conductor on the top surface, were epoxied to the substrate to reconstruct the interconnect paths. The change bars were attached with non-conductive epoxy. To turn corners, the change bars were interconnected from one to another with wire bonds to complete the connection from die to die. (A double change bar which is a single piece of ceramic with two metallization stripes was also used.) Figure 11-24 shows a prototype circuit which had a large number of changes. The technique permitted jumping over change bars.

In jumping over the change bars, a nonconductive epoxy was used to prevent shorting of the wire bond to the top surface of the change bar. This change and repair method for chip-and-wire circuitry proved to be quite effective for change and repair, an absolute necessity in the design of random logic systems. Of the 35 types in the initial system design, it was necessary to relay out only four circuits when the number of change bars and changes to the circuit caused concern that perhaps the next change would be impossible to route on the top surface. The change technique was fully qualified so that modules with engineering changes or repairs were suitable and reliable for production use.

11.21 Repair Links Another method for the change and repair of high density ceramic modules with chip carriers was an approach using repair links. This was an extension of a similar technique which was applied for many

Figure 11-24. Thick film change bars with wire bonded jumpers.

11.21 Repair Links

y 2ars for multilayer controlled impedance E CL printed circuit assemblies used in the 1100 family of computers and is a design/ layout approach that is applicable to printed wiring, ceramic and other interconnect technologies. The method uses surface rcpair links with a basic ground rule that there is no internal layer signal connection t o the component attachment pad. All innzr layer nets are terminated at a via and tlie signal is connected on the external surfr ce to a pad used for the IC lead attachnient. One such geometry is shown in F ig. 11-25. Using this approach, the IC and tlie internal net can easily be isolated from one another by cutting (or grinding, or axading) the repair link. Note that the extcrnal repair link geometry can take a number of forms and will vary based on electrical and process requirements. There should be thin lead connection between the internal net via/pad for ease of cutting the link. The IC attach pad may be extended, or configured as shown in Fig. 11-25 to a low for attachment of change wires. A nire can be added to the internal net pad for connection to the internal net and to the extended IC attachment pad. Consistc nt, reliable surface mount soldering is sensitive to pad size and via hole locations. A thermal link can be added, as shown, M hich results in uniform feature size. This INITIAL

643

minimizes the effect of heat being drawn off by the via holes and the inner layer interconnections (which are typically non-uniform) which would result in non-uniform, inconsistent, unreliable solder joints. The spacing of surface mount pads is such that fine wires can be used for changes. Figure 11-26 shows a five layer thick film hybrid with 0.040 in ( 1.O mm) terminal pad spacing using this change approach. Changes were made with 0.005 in (-0.1 3 mm) diameter insulated wire. Repair links reduce packaging density, block routing channels, and can increase substrate cost. Packaging density, and performance, can be degraded in that repair links occupy at least two grid spaces beyond the overall outline of the package than when repair links are not used. However, these increased costs and density reduction must be weighed against the problems associated with making the change or repair, the reliability and quality and the cost of making a change using other methods. The repair link change approach is relatively inexpensive. It can be done with standard tools, does not require high skill levels or special bonding methods and it is a more regular, controllable change approach. These are just two possible techniques for the change and repair of high density

WITH CHANGE

Add Pad

Repair Link ,-Net Pad

Cut Link

Figure 11-25. Repair link configurations. Inner Layer Connections

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1 1 Integrated Circuit Packaging

Figure 11-26. Thick film substrate with repair links for surface mount packages (shown with lcadless chip carriers).

modules, both suitable for production of commercial products and are demonstrated practical methods of change and repair. Other techniques such as redistribution layers and methods for other types of microinterconnect (TAB and flip chip) have been successfully used by others. For large gate count random logic packaging, it is essential that repair and change methods be considered. The tradeoffs of development cost, production hardware cost, maintenance and logistics cost, electrical performance, density, quality, and reliability along with quick turnaround times for changes are complex and will vary with each application. The system designer or packaging engineer must, through careful analysis of the complex tradeoffs, select the technique best suited for each and every application.

11.22 The Future Cost and interconnection density are two major metrics in the selection of inter-

connection technologies. Messner’s work (1988) is very insightful and one of the many ways these data have been presented. These global comparisons are difficult for there are many other variables involved in the comparisons - volume, profit margins, thermal performance, etc., which significantly impact final product performance and cost. In 1982, the relative cost and density relationships of three primary interconnection technologies - printed wiring, thick film ceramic hybrids, and ICs - were well expressed by Mayo (1982) of AT&T as shown in Fig. 11-27. This was a good basis for comparison of technologies because AT & T was a volume manufacturer of all three technologies and the study provided significant insight for it showed the gap that existed between the ceramic and IC technologies. AT&T was one of the pioneering companies to develop and market thin film MCM interconnections (Polyhic) to fill this gap. In the mid-to-late 1980s there was substantial interest in the thin film technology, and it has slowly developed to the point where there are viable

645

11.22 The Future

The axes have purposely been left blank for the improvements in each technology will progress at about the same rate, keeping the relationships the same (and it also avoids predicting the unpredictable). And yes, the picture will change and thin film will become more cost effective as volume increases as applications truly need the high interconnection density that thin film offers. The cost/density picture will then look as shown in Fig. 11-29 and designers will be able to choose the best technology for their application from the continuum spanning printed wiring to integrated cir-

r ierchant market suppliers, however, the c,)ststill remains relatively high. And now t ie next industry bandwagon is rolling, t iat of fine-line, thin-laminate printed wiri ig technology for MCMs. In fact, all the r iainstream interconnection technologies k ,ive advanced in reducing relative cost per i iterconnection and higher densities to r ieet design needs compatible with semiconductor and package advances - reacti ig to the competitive threat of replacerient by thin film. So today, we have a situation illustrated by Fig. 11-28, which \ ill continue for the foreseeable future.

Printed Wiring cl

Figure 11-27. Relative cost vs. interconnection density for interconnection technology alternatives 1982.

Circuit I

io2

lo3

104

io6

105

Interconnection Density, in.*

Thin Film (loday)

Integrated Clrcult ,,,

Interconnection Density, in -2

Figure 11-28. Relative cost vs. interconnection density for interconnection technology alternatives - today.

646

1 1 Integrated Circuit Packaging

Thin Film (Today) *.‘

‘*.

..:+--.7 ‘. -.---L.’ %*

%.*

’\.

- . ~ T h i f Film l (Future)

‘\

‘. -..

---____..I

Figure 11-29. Relative cost vs. interconnection density for interconnection technology alternatives - future.

Interconnection Density, in -2

MCM Options 10,000

3,0001,000

n H

100

10k

100k

I/O Count

Figure 11-30. Multichjp module interconnection options-package cost VS. 110 count. Source: IBM Technology Products.

cuitry. Will the technology relationships change? Not in the foreseeable future. The same relationship shown in the AT&T chart has been shown more recently by IBM, Fig. 11-30, and there are no practical alternatives on the horizon. Planar optical interconnects (Thomson et al., 1994) have potential and are probably the next step beyond semiconductor thin film interconnects in effective interconnection density but it is a long way off. Does this mean that thin film will “win” the current battle between MCM-L (laminates), MCM-C (ceramics) or MCM-D (deposited thin film)? No, for there is more than cost and density in the selection of an interconnection technology. For example, thermal management is another major attribute demanded of an interconnection/ substrate technology and it can substantially change the picture. Again, the tradeoffs are numerous and complex and no one technology will meet all the semiconductor interconnection and packaging needs of the many, many varied applications in the electronics industry. The most effective future technologies are hard to predict, however, the three basic technologies of the 1990s will all be ap-

11.23 References

plied in volume plus the new high density techniques, filling the cost/density gap as shown in Fig. 11-29.

11.23 References Amey, D. (1981 a), Semicond. Int. Highlands Ranch, CO: Cahners Publishing Co. Amey, D. (1981 b), in Proc. IEPS Tech. Conf. Edina, MN: IEPS, pp. 1- 15. Amey, D. (1981 c), in Proc. Int. Microelectron. Conf. Highlands Ranch, CO: Cahners. Amey, D. (1984), “Surface Mounted Components” in Surface Mount Technology. Reston, VA: ISHM, pp. 11 -44. Amey, D. (1990), in Proc. Int. Microelectron. Conf. Reston, VA: ISHM, pp. 545-554. Amey, D. (1992), in Proc. Int. Symp. on Microelectron. Reston, VA: ISHM, pp. 225-234. Balde, J. (1987), in Proc. 7th Annu. IEPS Conf. Edina, MN: IEPS, pp. 860-872. Beaman, B., Shih, D., Walker, G. (1993), in Proc. Int. Con$ on Multichip Modules. Edina, MN: IEPS, and Reston, VA: ISHM, p. 341. Belopolsky, Y., Abramson, E., Murphy, A. (1991), in Proc. 1551 Jpn. Electron. Manufacturing Technol. Symp. Piscataway, NJ: IEEE. Bieber, C. (1989), in: Electronic Materials Handbook. Materials Park, OH: ASM Int., pp. 451-459. Blood, W. R. (1988), Motorola M E C L System Design Handbook, 4th ed. Tempe, AZ: Motorola Semiconductor Products Inc., pp. 44-48. Brown, R., Shapiro, A. (1993), in Proc. Int. Conf. on Multichip Modules. Edina, MN: IEPS, and Reston, VA: ISHM. Buschbom, M. (1988), IEEEICHMT V L S I and GaAs Chip Packaging Workshop, Sept. 1588. DiGiacomo, J. (1989), V L S I Handbook, New York: McGraw-Hill, p. 23.12. Drozdyk, L. (1993), in: Proc. Int. Symp. on Microelectronics. Reston, VA: ISHM, pp. 209-214. Florod Corp. (1991), L A S E R Stitching. A New Way to Rewire IC’s. Gardena, CA: Florod Corp. Freedman, M. (1993), in Proc. Surface Mount Int. Con6 EIA and SMTA.

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Freedman, M., Short, F. (1981), in Proc. Int. Symp. on Microelectronics. Reston, VA: ISHM, pp. 5 1 56. Goodman, T., Fujita, H., Murakami, Y Murphy, A. (1993), in Proc. 43rd IEEE Electron. Compon. Technol. Conf. Piscataway, NJ: IEEE, pp. 425435. Grabbe, D., Pryputniewicz, R., Merkelo, H. (1993), in Proc. Int. Conf. on Multichip Modules. Edina, MN: IEPS, and Reston, VA: ISHM, p. 347. Harper, C., Miller, M. (1993), Electronic Packaging, Microelectronics, and Interconnection Dictionarj,. New York: McGraw-Hill. Houghton, J. (1995), Electron. Design, February 6, 141. IBM (1982), “Thermal Conduction Module Design”, IBM J. Res. Devel. 26 ( 1 ) . 30. IBM Microelectronics (1993), Lasersonic Bonding. Hopewell Junction, NY: IBM Microelectronics. Landman, B., Russo, R. (1971), IEEE Trans. Coinput. C-20, 1469. Leedecke, C. (1989), in Electronic Materials Handbook. Materials Park, OH: ASM Int., p. 451. Mayo, J. (1982), Circuits Manufacturing, April, 29. Messner, G. (1988), in Proc. Int. Symp. on Microelectronics. Reston, VA: ISHM, pp. 28-36. Penry, M. (1983), Wescon, Session 3. Piscataway, NJ: IEEE, pp. 3-4. Poulin, T., Nguyen, L. (1993), in Proc. 43rd Electron. Compon. Technol. Conf. Piscataway, NJ: IEEE. p. 904. Rima, P. (1985), Hybrid Circuit Technol. November, 15. Schmidt, D. (1981), in Proc. IEPS Tech. Conf. Edina. MN: IEPS, p. 143. Schmidt, D. (1982), IEEE Trans. Comput. Aided Design Integ. Circuits Syst. C A D - l , 1469. Steele, T. (1981), IEEE Trans. Compon., Hybrids Manuf. Technol. C H M Y - 4 , 192. Thomson, J., Levesque, H., Savov, E., Horowitz, F., Booth, B., Marchegiano, J. (1994), Opt. Eng. 33, 939. Tummala, R., Rymaszewski, E. (1989), Microelectronic Handbook. New York: Van Nostrand Reinhold. Wall Street Journal (1990), “Another ‘Bug’ in Intel Chip May Delay Few Shipments”, Wall Street Journal, January 30. Wang, T. (1993), E M C Design Test, February, 27.

1 2 Interconnection Systems M'ulf Knausenberger

R D Hikuai. via Thames. New Zealand Fc )rmerly of AT & T Bell Laboratories

Lid of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnection Technology Trends and Drivers . . . . . . . . . . . . . . . . . . . . . . . 12.2 12.2.1 Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Interconnection Density as a Cost Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2.1 Interconnection Capability and Cost Metric . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 Interconnection Cost Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Matching Capability and Need .................................... Interconnection Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 12 4 Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Partitioning Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2.1 Component-Oriented Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2.2 Interconnection-Oriented Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3 Interconnection Distribution Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3.1 Broadcast Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3.2 Network Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3.3 Status/Control Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.4 Ideal System Partitioning Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichip Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 12.6 Printed Wiring Board (PWB) Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.61 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.62 Material Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.3 PWB Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.3.1 Rigid PWBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.3.2 Discrete Wired Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.r7.3.3 Flexible PWBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.4 PWB Production Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.'1.4.1 Basic Processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.4.2 Fabrication Sequences for Different PWB Types . . . . . . . . . . . . . . . . . . . . . 12. Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Merging of Markets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. '.l 12.1.2 New Form of Consumer Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.''.3 Evolution of Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.S

650 652 655 655 658 658 659 661 661 665 665 666 666 666 668 668 669 669 669 669 671 671 671 673 673 673 673 674 674 676 677 678 678 679 680

650

12 Interconnection Systems

List of Abbreviations B-stage epoxy BGA

CMOS

COB DCA

DRAM DSR FR-4 FRU HIC

IC IjO

KGD

LSI MCM MIPS

MLB MSI

PC PTH

partially cured epoxyifiberglass mat sheets, used in the manufacture of MLBs ball grid array: a component package whose IjO interface to the interconnection substrate is by means of small metal balls placed in a regular array on the bottom surface of the package complementary metal-oxide semiconductor : the most prevalent form of silicon chip technology in use today because of its low power requirements and the ease of achieving high levels of integration chip-on-board: the chip packaging practice in which the chip is mounted directly on the PWB, without an intervening chip package direct chip attach: a chip to interconnection substrate attachment method in which the chip is directly adhesively attached without any intermediary package dynamic random access memory double-sided rigid : a PWB with two total layers of printed circuitry fire retardant-4: the most widely used grade of epoxy impregnated fiberglass circuit board, often referred to as “the industry workhorse” field-replaceable unit : a physically and functionally separable module of electronic equipment which is readily replaceable or swappable hybrid integrated circuit : a functional ceramic interconnection substrate which can combine active chips and passive resistors, capacitors, or inductors integrated circuit: a semiconductor chip which contains a multiplicity of transistors input or output terminal: a lead-in or lead-out within electronic equipment which is interconnected from one interconnection level to another known good die: a chip, in bare die format, which has been functionally and parametrically tested to provide a high level of assurance that it will function properly when mounted as part of an MCM assembly large scale integrated circuit: a chip which contains a large amount of electronic functionality, with a gate count in the range of 1000 to 100 000 multichip module : a functional interconnection substrate which interconnects two or more unpackaged chips millions of instructions per second: an absolute measure of computer performance multilayer board: a PWB with more than two layers of printed circuitry medium scale integrated circuit: a chip which contains a moderate amount of electronic functionality, with a gate count in the range of 10 to 1000 personal computer or printed circuit plated-through hole: a hole in a PWB which is first drilled and then copper plated to complete the connection between circuits on the upper and lower layers

List of Abbreviations

'WB !;SI TAB

','LSI

651

printed wiring board: an interconnection circuit formed by etching copper conductors on a rigid or flexible insulating substrate small scale integrated circuit : a chip which contains only a small amount of electronic functionality, with a gate count in the range of 1 to 10 tape automated bonding: a component package whose IjO interface to the interconnection substrate is, by means of a flexible tape lead frame, bonded both to the component and to the substrate very large scale integrated circuit: a chip which contains a very large amount of electronic functionality and generally more than 100 000 gates

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12 Interconnection Systems

12.1 Perspective In the past, the major technology emphasis of most electronic product developments has been concentrated on integrated circuit (IC) design and IC technology development. Before the days of very large scale integrated (VLSI) circuits, there was an implicit premise that gates were relatively expensive, whereas by comparison, wiring and packaging were cheap (Sutherland and Mead, 1977). Thus, designers expended their energy on implementing the desired function with a minimum of circuitry. Any effects of this design approach on interconnections were viewed as merely a secondary consideration. Interconnections and packaging were treated as something that could be purchased off the shelf near the end of the development cycle. An underlying assumption was that with further development of VLSI, it would be possible to fit all the electronic functions on a single chip and the interconnection problem would go away.

With the tremendous progress in IC technology in the intervening years, this situation has been completely reversed. Now the cost of an individual gate has become almost vanishingly small, while the cost of the interconnections has become dominant. In modern ICs, the interconnection paths generally occupy most of the space. ICs are being made with two or three metallic interconnection layers in order to still leave some room for gates. Offchip, the relatively long interconnections are even more costly. The cost must be calculated in terms of both actual incurred cost as well as performance limitations which are introduced because of the interconnections’ size and delaying effect. With each succeeding IC generation, it has become clear that the increased capabilities are being used to design more compact new systems with higher levels of functionality, rather than just simpler, more cost effective single chip versions of the old systems. Figure 12-1 illustrates the rapid evolution of computing capability over time (Wessely et al., 1991).

Figure 12-1. Performance trends in computer systems over time (Wessely et a]., 1991).

653

12.1 Perspective

Figure 12-2. A comparison of the dramatic evolution of data modem products.

However, density and performance imp -ovements, though most publicized in computers, have been achieved througho lt the electronics industry. The evolution 0’ computing capability has been so rapid tbat the definition of mainframes and perscdnal computers, expressed in terms of millic )ns of instructions per second (MIPS), differ only by a time function. In actuality, minframes and personal computers differ in many ways beyond mere computing power. Figures 12-2 and 12-3 show the physical hidory of the volumetric and performance iniprovements in a data modem product liiie over a span of 37 years. During this tit lie the physical form factor of the modem e\ olved from a large steel-encased box into a light and diminutive PC card. This represeits a reduction in physical volume of mi ,re than two orders of magnitude. At the sa ne time, there has been a factor of 576 int:rease in transmission rate capability. System designers are just as dynamic as chip designers as they incorporate innovati\ e capabilities into each new equipment generation. Designers now develop systems with functionality and performance wliich were unthinkable just a few design ge ierations earlier. As the chips become

1960

1970

1980

1990

2000

Year of Introduction

Figure 12-3. The evolution of data transmission capacity of data modems. At the same time as the data rate was dramatically increasing, the physical volume ( V ) of the equipment was dramatically shrinking.

more complex, the interconnection problem keeps expanding. Systems today often consist of arrays of many VLSI chips and other varied components which must be interconnected together. And all the while, the complexity keeps growing. Figure 12-4 illustrates the growth in single-chip gate capability over time, as observed in dynamic random access memory chips (a rec-

654

12 Interconnection Systems

1960

1970

1980

1990

2000

Year

Figure 12-4. The history of leading-edge dynamic random access memorq (DRAM) chip densit!.

ognized technology driver). This leads to a complex and variable interconnection problem on the board level. Figure 12-5 shows the historical trendline for the minimum feature size on a silicon chip over time. Leading-edge VLSI chips are currently doubling in complexity about every one and a half to two years. This relentless advance, in turn, creates the requirement for system level packaging engineers to interconnect larger, more

complex chips with increasing numbers of II'O leads per chip. This has, in turn, required a steady growth in interconnection capability on the PWB level. Figure 12-6 illustrates this capability growth in PWB products, both historical and projected, as typically applied in the volume markets of the telecom and mid-range computer industries (Knausenberger, 1992). The challenges encountered in interconnecting today's VLSI chips are much greater than those which had to be solved with the SSI and MSI chips of prior generations. Today it is becoming widely recognized in the electronics community that one cannot achieve the full benefits of VLSI without also having very advanced and sophisticated interconnection technology (Pinnel and Knausenberger, 1987). The interconnection system plays a vital role in translating the system designer's chips and concepts into reality. The design of the interconnection system (also called packaging design or physical design) is a major engineering effort which addresses every aspect of the system's design, from the underlying

100 n

z 5

P IJY

E I-

0 1970

i -13% Reduction per year

01 1960

1970

1980

1990

-A

Zoo0

Year

Figure 12-5. The history of minimum feature length of leading-edge silicon chips over time

1975

1980

1985

1990

1995

2000

YEAR

Figure 12-6. Interconnection needs of plug-in cards in telecom and mid-range computer industry. A "comp term" is a component termination or rnounting point (source of an l/O).

655

12.2 Interconnection Technology Trends and Drivers

niaterials and technologies, all the way to accommodating details of the manufacturiiig process. It is the job of the physical d -signer to orchestrate inputs from these 1 ,irying disciplines and make an optimized design choice. The physical designer is gene ally responsible for integrating the layo Jt, interconnection design, prototyping, t liermal design, reliability, testability and d s i g n for assembly and manufacturabilit: . The solution involves performing a ser:2s of trade-offs between materials, mec ianical design and electrical performance M ith the objective of achieving the lowestCI )st system which will meet the design objcctives. Later parts of this chapter will a Idress some of the technology elements M hich must be mastered in order to make tliese trade-off decisions effectively.

1 2.2 Interconnection Technology Trends and Drivers 12.2.1 Trends

Rapid technological advances in electronic system technologies are placing inCI easing demands on interconnection media. A primary driving force is the relentless e\ olutionary advance in the scale of integi ation in silicon IC technology discussed at.rove. Another is the revolutionary development of photonics, which is being integi ated into many levels of the interconnecti, )n hierarchy of electronic systems. These attvanced electronic and photonic technologies are physically embodied in the fc rm of advanced electronic components. These must then be physically interconntzted with one another, as well as with 01 her more traditional components, by an in terconnection system. The interconnection system must be carefully designed in order to achieve the overall objectives for the electronic system. Increasingly, in

modern day electronic systems, the interconnections dictate what the final product will be like and determine what level of performance can be offered. The major trends in electronic systems evolution are well established. The demand is for systems with ever higher performance that provide their required functions in less physical space (Pinnel and Knausenberger, 1987). At the same time, international competition requires that this be done in the most cost-effective way possible. Figure 12-7 summarizes these key factors and trends. Practical feature sizes (design rules and grid spacings at all interconnection levels) are continually decreasing, coincident with a rapidly increasing scale of integration on ICs. Figure 12-8 illustrates the design rule improvement trends as observed in leading edge IC chips and printed wiring boards (Rust, 1989). This has driven a decrease, over the years, in the physical size of major electronic systems - from full equipment bays, through single frames or shelves, down to the single-board level (Hoover et al., 1987). Single-wafer or chip-level systems of impressive complexity are continually being developed. The obvious by-products of this technology direction include greatly increased speed, shorter path lengths, and the use of less material. The result is more

Decreasing feature size

$Emance

less integration Lower cost ~~

Figure 12-7. Trends in electronic packaging.

656

12 Interconnection Systems

Table 12-1. Impact of technology drivers on electronic system attributes.

-2.0 3.0

IC Industry

0.04 0.030.02 0.01

1960

1970

1980

1990

2000

Year

Figure 12-8. Trends in minimum feature size for the microelectronics industry (IC: integrated circuit; PC: printed circuit; 1 mil = 25.4 pm).

compact and lower-cost systems with higher performance. There are many technology drivers for electronic packaging. The primary ones are : 0 0

Photonics

Software control

t t

4.0

VLSI

very-large-scale-integration (VLSI) integrated circuit technology photonic technology control of system functionality through software control

The major one is the continuing evolution of VLSI in silicon. This driving force has had a profound impact and influence on the electronics industry since the 1960s. Photonic signal transmission and the future promise of all-optical signal switching and processing, coupled with ever-increasing use of software control, are two more technologies that are having a major effect on current electronic systems. Table 12-1 summarizes the impact of these technologies on system-level products in terms of

Circuit density Interconnect density Memory size and density Thermal density System capability System complexity Cost per function

t t 1

t t

density, system capability (performance), and system complexity. The “bottom line” is that these drive the potential for everlower costs per system function. Since the advent of the first ICs in the early 1960s, the design rules (dimensions) on silicon have decreased by nearly two orders of magnitude. Concurrent with this decrease in feature size, the typical density (gates per chip) has increased by almost three orders of magnitude, while the cost (cents per gate) has declined by almost two orders of magnitude (Fig. 12-9). It is anticipated that this trend will not change dramatically in the foreseeable future. Continued progress toward more costeffective, capable systems is expected as photonics and software control both experience innovation and approach maturity. System designers continue to find that the most cost-effective and highest-performance systems minimize the number of field-replaceable units (plug-in cards) by increasing the amount of circuitry per card. The overall effect of this design direction is to further increase the packaging density of the system. The higher performance and IjO requirements of modern chips helped to establish a fundamental change in assembly technology - the transition in the 1980s

12.2 Interconnection Technology Trends and Drivers

657

Design rules ( prn)

3.5 2.5 1.75 1.251.0 0.5 0.35

0.2

1O s i

Figure 12-9. Chip gate density, cost per gate and design rules as a function of time. 1970

1975

1980

1985

1990

1995

2000

Year

from wave-soldered, through-hole assembly to the higher-density surface-mount technology. This change impacted all clmes of components, yielding higher inte rconnection densities by eliminating la rge through-holes for leads and reducing tl-e pitch of the IjO leads. The future will bring further density increases by continuing IjO lead pitch reductions and by arrbnging the I/Os of the components in an area array, rather than perimeter, pattern. And the ultimate package will be no package at all. Unpackaged chips mounted dire ctly to the printed wiring board (chip-onboard technology, COB) will become more common. Figure 12-10 illustrates the nature of this progression to higher-density interconnections. Note the dramatic deC I ease, for each technology progression step, in printed wiring board area occupied b:, a 40 IjO component.

As the packaging density increases, the number of terminals interconnected on each field-replaceable unit (FRU) increases. Figure 12-11 contrasts data from 1970 to 1990 on the rapid growth in assembly point (also known as component terminal or pad) density in telecommunications products with the chip level component growth curve (Rust, 1989). The chip-level trends scale to similar trends at the system or product level. As feature size decreases and memory capacity increases, system complexity and power density increase dramatically. But for these benefits to be realized, similar innovation and improvements must occur throughout the interconnection hierarchy. During the early years of the IC revolution, high-end (mainframe computer) packaging technology solutions represented the leading-edge of future mass-produced elec-

658

1 2 Interconnection Systems Thru-Hole

Surface-Mount

Chipon-Board

1.27 mm grid 10 cmlcm,

0.41 mm grid

0.25 mm grid 35 cdcrnz

20 CdCM

r------------

-----l L

I I

L,,,,,,-,-----A

40 pin DIP

40 pin CHIP CARRIER

40 pin TAB

6.5 cma

1.6 cma

10.7 cm*

tronics. The "trickle down'' theory stated that, as a high-end product matured, it would become more cost-effective when produced in volume, and be adapted into mass-marketed products. By the mid1980s, mainframe computer technology began to lose this technology driver role. Its technological solutions began to fulfill more "niche" technology roles. Consumer electronics had begun to change its character and be more directly driven by the most cost-effective solutions to the given prob-

1970

1980

1990

Year

Figure 12-11. Silicon IC scale of integration contrasted to assembly points on plug-in cards in telecommunications product.

Figure 12-10. An illustration of the increasing interconnection density, expressed in centimeters of wiring capability per square centimeter of substrate.

lems. Frequently these solutions were unique. When they were repeatedly picked up and applied in different situations, they became "standard" and were added to the base of available technology. 12.2.2 Interconnection Density as a Cost Driver

It is a widely accepted concept that the aggressive application of the highest-density VLSI chips available to a new system design will generally lead to a minimum interconnection cost (Goddard, 1979). It is also generally accepted that the interconnection cost will decrease as the interconnection medium approaches the chip level. It will be shown that this is generally true because this approach on average will lead to shorter overall interconnection lengths in the system. The cost per unit length of most interconnection media is roughly comparable, whether on printed wiring boards or on silicon (Knausenberger and Schaper, 1984). 12.2.2.1 Interconnection Capability and Cost Metric

There is a hierarchy of interconnection levels used for connecting devices. These

12.2 Interconnection Technology Trends and Drivers

will be defined in detail in Sec. 12.3. The chip itself can be viewed as a substrate to co tinect polycells, or other cell-like elemchnts. The hybrid circuit connects bare chips, and the printed wiring boards can connect bare or packaged ICs. The item of concern for all these “substrates” is interco tinection capability and interconnection co >t* The simple measure of interconnection de isity is not a good measure of substrate ca;)ability because small devices (i.e., polycells) will obviously have many interconnet.tions per square inch. The wires will be sh(n-t, as well as dense. Large components, su( h as chip carriers, will require much loriger wires for an interconnection. The figure of merit of inches of interconnec%tion(wire) available per unit area of SUI strate is useful for gaining insight into tht cost of interconnections. This measure is directly related to substrate technology, no to the size of the devices to be interconne( ted. The cost per unit length of available wire is the yardstick used to determine the relativc cost of making wires in the various technologies. Specifying the cost per intercoiinection would be inappropriate since it is strongly related to device size, since size will influence interconnection length. 12.2.2.2 Interconnection Cost Comparisons iin interconnection cost comparison betwi en several varieties of printed wiring bo:irds, a hybrid circuit and a CMOS IC deriionstrated that the relative cost per unit length of wire is essentially constant, regardless of the substrate technology. In thi., study, the generally accepted principle that interconnection cost decreases as the interconnection medium approaches the chi ~3 level (Goddard, 1979) was carefully examined as to its origins. It was determii led that the decreases in interconnec-

659

tion cost resulting from more aggressive use of VLSI chips are entirely due to decreases in interconnection length (Knausenberger and Schaper, 1984). The capabilities of the following five interconnection substrate technologies were compared and contrasted: CMOS silicon chips with 2.5 pm design rules; a ceramic HIC substrate with 5 mil (125 pm) lines and spaces; a multi-layer board (MLB) PWB with 8 mil (200 pm) lines and 9 mil (230 pm) spaces and surface-mounted components interfacing to a 30 mil (760 pm) via land; MLB PWB with 8 mil (200 pm) lines and 9 mil (230 pm) spaces and through-hole components inserted into holes in 60 mil (1520 pm) lands; and a double-sided rigid (DSR) PWB with 12 mil (300pm) lines and spaces and throughhole components inserted into holes in 60 mil (1520 pm) lands. Their total interconnection lengths were determined and then contrasted with their actual costs, which were then normalized. Figure 12-12 plots relative cost per inch of wire against the capability, in inches of wire per square inch of substrate. Even though the capability range spans more than two orders of magnitude, the range of relative costs is very small. In effect, wire costs the same per unit length whether on printed wiring boards or on silicon. The importance of high-density wiring for low system cost is that the high density allows the total length of wire required to interconnect the active devices in the system to decrease. Since cost is directly proportional to total wire length, this allows a lower system cost. Earlier data (Goddard, 1979) were traditionally plotted from the perspective of constant cost-perunit area trendlines (Fig. 12-13). This has been useful because it tends to catagorize different interconnection media naturally into different inherent density bands.

660

1 2 Interconnection Systems

e HIC 0 2.5pm

MLB - TH 0 MLB - SM

100

Figure 12-12. Relative interconnection cost of five different interconnection substrates plotted on a cost-per-unit-length basis. versus interconnection capability. This shows that the cost of a unit length of interconnection is essentially invariant, regardless of the medium.

10 000

1000

Interconnection capability in / in2

Constant cost / in2

Figure 12-13. Per-interconnection cost of substrates plotted against interconnection density. showing how each substrate class falls into its own cost-per-unit-area category.

L silicon

100

10K

IOOK

Interconnection density (per in

)

Figure 12-14. Per-interconnection cost of substrates plotted against interconnection density. showing how the cost of each substrate class. when considered on a cost-per-unit-length basis, is essentially invariant. 1

100

1OK

IOOK

Interconnection density (per in2)

The trendlines in Fig. 12-13 have a slope of 1/2. Their dimensions show that this is again a statement that interconnection costs are constant on a per-unit-length basis. Reanalysis of these data reveals that

they also follow a constant cost per length of interconnection trendline. The data are replotted in Fig. 12-14 with a constant cost-per-linear-inch trendline. All the prior data points conform reasonably well to

12.3 Interconnection Hierarchy

66 1

Figure 12-15. Cost of an interconnection viewed from the level of a single chip through to spanning across the worldwide communications network (Knausenberger and Schaper, 1984). 1u2

iaz

io4

lo6

Distance from center of chip (meters)

this replotted constant cost-per-unit-length ti endline. If one were to view all levels of interconnsction, up to and including the worldwide telecommunications network, it would span interconnections ranging from micrometers to millions of meters. Figure 12-15 (Knausenberger and Schaper, 1984) illustr ates how interconnection costs over this D ide range of physical interconnection lengths, to a first approximation, can still bc generally described as invariant on a per-unit-length basis. 12.2.3 Matching Capability and Need

In order to minimize system costs, there must be an approximate match between a s ~bstrate’s ! wiring capability and the intercclnnection requirements of the componmts placed on that substrate. If packages 01 devices with high interconnection demdnds are placed on low-capability subst-ates, routing will either be impossible, or the devices will have to be spread out o ~ e ra much greater substrate area than thdt of the devices themselves. This would generally not be a desirable solution when miniaturization is an objective. Conversely putting packages with low interconnection demand on a high-density substrate is

uneconomic, because expensive substrate area (and therefore a great deal of wiring capability) is not being effectively used. Optimal packaging strategies will roughly match the interconnection capability of the substrate to the wiring demand placed on that substrate by the devices mounted thereon. Studies have shown (Pinnel and Knausenberger, 1987) that following such strategies will generally lead to minimized system interconnection costs.

12.3 Interconnection Hierarchy One can think of a digital electronic system as logic gates and memory cells that must be interconnected together in a particular way, by means of a packaging system, in order to achieve the desired system functionality. The interconnection system, together with the hardware which is required to physically support and realize it, constitutes a packaging system. A successful packaging system must satisfy all the demands imposed on it by the system design (Ambekar et al., 1987). The physical realization of a system should result in providing low-cost, functional, and reliable interconnection between all ele-

662

12 Interconnection Systems

ments of the system. These interconnections span the range from on-chip transistor to transistor connections, measured in micrometers, to the final system level outputs, measured in meters. The nature of the physical realization of the system is very dependent on the size and nature of the system being interconnected. Physically small systems tend toward unique solutions which are very dependent on the particular characteristics of the application. Digital thermometers, watches, pocket pagers, hand-held radios, pacemakers, and remote controllers are examples of systems which benefit from such unique approaches. These systems have a flat interconnection hierarchy and will not be discussed here further. The subject to be addressed here is large electronic systems which exhibit a hierarchy of interconnection levels. Figure 12-16 shows a schematic representation of a frame of electronic equipment as is typical of large telecommunications systems. Many different types of interconnections are present in such a system, from tiny on-chip connections to long inter-cabinet connections. They can be conveniently categorized in terms of levels of interconnec-

tion within the interconnection hierarchy, which will be defined and described here. The interconnection hierarchy is the sequence of physical levels or layers of interconnection hardware that join IC chips and other components to form an electronic system. Interconnection is truly the bridge between the chips and a functional electronic system. Level 0 consists of transistor-to-transistor and gate-to-gate connections within an IC chip. This, the most fundamental level of interconnection, provides all the internal chip connections between elements and organizes the external chip connections into regular arrays for interconnection to the next level (see Fig. 12-17). The IC chip itself is usually packaged for environmental protection, testability and ease of handling, but this constitutes the next level of interconnection. Level 1 is the packaging of silicon chips into single-chip packages or multichip modules. Refer to Chapter 11 for a much more detailed discussion of single chip packages and to Sec. 12.5 of this chapter for a discussion of multichip module technology. In the case of chip-on-board (COB) packaging, level 1 interconnections

Figure 12-16. An isometric overview of a "rack and frame" style packaging system.

Figure 12-17. A close-up picture of a bare silicon chip.

1 2 . 3 Interconnection Hierarchy

Figure 12-18. Isometric drawing of a plug-in board (1 :vel 2).

663

consist only of the chip-to-board connections. Level 2 concerns the interconnection of individual component terminals with one another on the board (also frequently referred to as “card”) level. This is shown schematically in Fig. 12-18. The most frequently utilized level 2 interconnection medium is the printed wiring board (PWB). See Sec. 12.6 for a more complete description of PWBs. When the components have been assembled to the PWB, the resulting assembly is called a field-replaceable unit (FRU) or a circuit pack. Figure 12-19 shows a typical modern telecommunications circuit pack.

Figure 12-19. Photograph of an early 1990s telecommunications plug-in board (interconnection level 2).

664

12 Interconnection Systems

Level 3 is the term which is applied to backplane (also known as backpanel) interconnections. Their function is the interconnection of the I/Os originating from all the FRUs which plug into the backplane of a unit or equipment rack. See Fig. 12-20 for a schematic representation of this function. The FRUs may connect to the backplane as orthogonally intersecting planes (as shown in Fig. 12-20), or as planar attachments (as seen in Fig. 12-21). The former has the advantage of allowing the interconnection of a large number of FRUs which are easily removable, but the disadvantage of relatively long interconnection lengths and a limited number of FRU-tobackplane 110s which is determined by the intersection length of the planes. The latter has the advantage of shorter interconnection lengths on average and a capability for more I/Os, limited by the FRU perimeter, or the planar area of intersection, de-

Figure 12-20. Isometric drawing of traditional shelflevel equipment unit (interconnection level 3).

Figure 12-21. Isometric drawing of a planar layout backplane shelf unit (interconnection level 3).

pending on the connector technology utilized. But the latter approach has the disadvantage of requiring more backplane area per FRU, and thus yields a lower FRU density. In addition, the planar approach generally renders FRUs less easily removable. The physical partitioning approach (discussed in Sec. 12.4) selected will strongly influence the backplane approach chosen in any system design. Level 4 refers to interconnections between units or equipment racks, while still remaining within the cabinet or equipment frame. This is generally in the form of discrete wires, discrete coaxial cable, wire harnesses, flat cable, optical fibers or fiber assemblies and power bus-bars. The interconnections are dominantly made between the rear of the units or racks, but can also be made to the front or sides. Refer to Fig. 12-22 for a schematic representation of this type of interconnection. Level 5 refers to inter-cabinet or interframe interconnections. These interconnections link individual frames in large, multi-cabinet electronic systems, or interconnect single-cabinet systems with the outside world. The interconnection media are much the same as used in level 4 interconnections, but the physical interconnection lengths tend to be longer. In addition, the signal bandwidths are generally greater. As a consequence, coax and fiberoptic interconnections play a more dominant role at this level. The interconnection hierarchy continues beyond level 5 for many more levels, encompassing interconnections between rooms and floors of a building, all the way to worldwide telecommunications interconnections. These will not be discussed here, however, since the focus is upon interconnection systems which enable the building of freestanding electronic systems.

12.4 Partitioning

Figure 12-22. Isometric drawing of equipment frame (interconnection level 4).

Consumer electronics equipment generall! encompasses interconnection levels 0 through levels 2 or 3. Large freestanding equipment spans levels 0 through levels 4 or 5. Equipment which is interconnected with other equipment in physically dispalate locations, such as a world-wide COI nputer or telecommunications network, spans levels 0 through levels 7 or 8.

12.4 Partitioning 12.3.1 Introduction I n the IC and system design process, transistors are grouped closely together to form logic elements (gates) of various kinds (NAND, NOR, inverter, etc.). These gatzs are then interconnected to one another to perform higher-level logical functions (addition, subtraction, shifting, multiplication, etc.). The higher-level functioiis are grouped together to form functional entities (multiplexers, demultiplexers, counters, decoders, etc.) and functions

665

at an even higher level. This process is carried through until all the functions required in the overall system are constructed. Physically, this encompasses all the levels of interconnection which are appropriate to the end product. As IC technology has evolved, an ever greater fraction of these interconnections have migrated into on-chip, or level 0 interconnections. This migration, over the years, of so many system interconnections to lower levels of interconnection (resulting in much shorter overall interconnection lengths) has contributed substantially to the remarkable cost/performance improvements in successive generations of electronic equipment. The partitioning of an electronic system is the process of dividing the overall system into manageable sub-units. Each of the resulting sub-units can then be individually carried through the physical design process. The final system is then assembled out of the independently designed subunits. Some of the general objectives of the partitioning process are to : 1. Minimize the number of interconnections intersected in the partitioning process. Cutting more interconnections than the maximum number of I/Os physically available on the sub-unit is grounds for stopping and trying a different partition. 2. Include no more components in the partition than the chosen technology will support on the sub-unit. 3. Partition the circuit such that the sub-units perform recognizable, easily testable functions.

One of the more important variables in partitioning is the size of the field-replaceable unit (FRU). Among the factors entering into this choice are the needs of the system architecture, the system features

666

12 Interconnection Systems

and performance requirements, manufacturing capabilities, marketing needs, service policies, etc. Usually, one of the most important factors in determining the FRU to be used is the prior FRU usage practices. The existence of prior expertise, tools, equipment and procedures will bias subsequent designs in the same direction, assuming there were no serious deficiencies.

12.4.2 Partitioning Approaches Another very important system characteristic to be recognized and considered is the kind of wiring which is being used and the kind of partitioning approach which is most appropriate (Wilson, 1980). There are two distinct approaches to partitioning an electronic system. The component-oriented approach first breaks down the electronic system into component assemblies, without particular regard for regular placement of interconnection patterns. When the time comes to interconnect systems partitioned in this way, the interconnections are generally quite random, while the components are orderly and well laid out. The interconnections-oriented approach first breaks the system down into interconnection networks. The specific interconnections then get designed as relatively orderly and efficient structures, while the components end up being relatively randomly distributed, as dictated by the location of the interconnection network.

12.4.2.1 Component-Oriented Partitioning Most systems today are still designed following the component-oriented approach. However, this is done largely for historical reasons. The approach which results in the most cost-effective final system is the one which should ideally be fol-

lowed. Because of the limiting effect of interconnections in so many modern electronic systems, the interconnection-oriented partitioning approach, or a composite of the component- and interconnectionoriented approach, should be carefully considered. Component-oriented partitioning involves carefully partitioning, or allocating, the components required to implement the system into blocks with approximately equal component numbers (or in the case of widely varying component types, into approximately equal component mounting area requirements). The foremost concern is that each block form a reasonably functional unit and fit within the physical constraints of the physical entity (number of I/Os, area required for components) for each interconnection level. The interconnections are then added at the end.

12.4.2.2 Interconnection-Oriented Partitioning In interconnection-oriented partitioning, one designs and implements interconnections in orderly bundles rather than as customized, randomized, one-by-one connections. This order is achieved by understanding and recognizing that three very different signal distribution patterns are found, in varying degrees, within electronic systems. These are designated broadcast, network and status/control patterns. Interconnection oriented design calls for recognizing each and treating it appropriately. There are three modes of interconnection-oriented partitioning ; functional, modular, and hierarchical. Figures 12-23 and 12-24 illustrate these modes conceptually. Functional partitioning strives for the absolute minimization of interconnections

12.4 Partitioning

667

Environment

Figure 12-23. Functional and modular partitioning occurring within a complex structure with repeating elements.

Backplm

VQ! Figure 12-24. An overview of the appearance of hierarchically partitioned interconnections.

intersected by a partition boundary. This prxess tends to separate out functional units - circuitry segments which in the limit have only several inputs and outputs, as well as some power and ground interco tinections. Functionally partitioned circu try within a large electronic system teiids to yield dissimilar sized chunks of equipment. This can limit the available physical packaging options. Modular partitioning can be appropriate for electronic systems in which a fuiictional regularity is present. For exan iple, electronic switching systems have an extensive switching fabric with widespi ead application of repeating banks of idi ntical switchpoints. Modularly partitioning such a circuit and laying out common interconnection patterns allows one

to take advantage of the regularity of the interconnections. If each of those regular interconnections were to have been randomly routed, regardless of the other similar interconnections, the resulting interconnection problem would be vastly more difficult . In hierarchical partitioning, the system is superimposed onto a hierarchical form factor and functions are allocated to different physical entities. This is based largely on the capacity of the interconnection hardware at each level, but can also be simultaneously influenced by modular and functional partitioning considerations. Most large electronic systems are hierarchically partitioned. This process tends to lead to relatively uniform partition sizes at each interconnection level.

668

12 Interconnection Systems

An idealized partitioning procedure combines flexibility and standardization by judiciously balancing the elements of functional, modular and hierarchical partitioning. It simplifies the structure into separable elements, capitalizing on repeated patterns and past design successes, while providing for conflicting needs.

12.4.3 Interconnection Distribution Patterns The traditional partitioning approach assumes that every interconnection has similarity of function with any other; namely, to make two or more physically separated points in an electronic system electrically common. As a result, logic interconnections and power interconnections are often lumped together in the same design problem. This approach is usually quite reasonable when systems with a limited number of interconnections are being designed. But in modern-day systems, which can have millions of interconnections, it is appropriate to consider interconnections more carefully in order to optimize the overall system design. An alternative design approach (Wilson, 1980), which is capable of handling interconnections in bundles rather than individually, is briefly described here. In this approach, interconnections are distinguished from one another on the basis that they are carrying different types of “signals”, e.g., logic, power, timing, control, etc. Significant differences can exist in the distribution patterns of the different types of interconnections. The ability to successfully deal with these interconnections in bundles or batches hinges upon identifying the common interconnections within each distribution pattern. As discussed in the previous section, when the interconnections within any

electronic system are analyzed in terms of pattern and form, they can normally be categorized into three different classes or patterns. These interconnection classes are the broadcast, network, and status/control patterns. Once the interconnections fitting each of these patterns are successfully identified in a design, the interconnection design emphasis shifts from detailing each interconnection, one by one, to providing bundled interconnections fitting these distribution patterns. See Fig. 12-25 for a schematic representation of interconnections fitting each of these patterns.

12.4.3.1 Broadcast Interconnections These are interconnections which originate from one source and are broadcast to many loads. They are transmitting locally generated “signals” to a radial distribution. The number of actual interconnections is generally fairly small, but they tend to require a high level of reliability and

(POWER, TIMING, ETC.)

SYSTEM ENVIRONMENT

Figure - 12-25. A schematic overview of the three kinds of signal distribution functions.

12.5 MultichiD Modules

669

physical robustness because they are absoI .itely critical to the successful functioning c f the electronic system. These broadcast iiiterconnections may deal with either analog or digital signals.

Their reliability needs are intermediate between those of network and broadcast interconnections. Changes occur fairly often, especially early in the life of a system, and are made on a one-by-one basis.

12.4.3.2 Network Interconnections

12.4.4 Ideal System Partitioning Approach

These tend to be fairly orderly distribution-pattern interconnections with many replications. They are typically signals v hich are inputs to or outputs from other fi inctions or electronic systems, sometimes a1 distant locations. The byte-wide buses SI) ubiquitous in modern electronic systems a re network interconnections. The longdistance telephone network is filled with network interconnections. The number of kads is often very high and the lengths long. Therefore, maintenance of signal integrity is an important design considera I ion. Since the very nature of network interconnection features redundancy, reliability is not of quite such paramount importance a. in the broadcast and status/control classes of interconnections. The signals are either analog or digital, and changes or rt,arrangements are relatively rare. When changes are made, they are most naturally dtme in bulk form, rather than on an indiwdual, wire-by-wire, basis.

The characteristics and needs of each of the three different types of interconnections are sufficiently different from one another that it is reasonable to attempt to accommodate them differently in the design. The partitioning approach suggested here involves first decomposing the interconnection design into three parallel design problems. These would deal separately with the broadcast, network and status/ control lead distributions, and optimize each individually. This approach will enable the designer to focus on the “big picture” of the patterns of the interconnections, rather than on building blocks of point-to-point wiring. In this way, the cost-dominating interconnections and interfaces can be minimized, rather than optimizing the components and physical building blocks.

1:!.4.3.3 Status/Control Interconnections These are locally generated signals u hich determine or control the status of tl e local system (logic and control circiiits). The physical topology is often treelitie and is much less regular than broadciist or network distributions. The number o ‘these leads in a system is relatively high, b it they tend to be short. These signals are gthnerally digital and require careful engini.ering to ensure adequate design margins aiid to avoid false triggering.

12.5 Multichip Modules Interconnecting individually packaged chips on large printed wiring boards (PWBs) to provide a performance-intensive function has proved to be increasingly difficult as system operating frequencies have increased. The most performancecritical portions of circuits can usually be designed to be localized to limited sections of the interconnection substrate. The interconnection capability (length of wiring which can be provided per unit area) on silicon chips has always greatly exceeded

670

12 Interconnection Systems

that of PWBs. As the scale of integration of silicon has spurted ahead over time, the pace of innovation on PWBs has not kept pace, resulting in an even greater capability gap. This has created a fertile opportunity for interconnection substrate technologies with a density intermediate between that of silicon chips and PWBs. This is the domain of the multichip module (MCM). A MCM is a dense, high-performance interconnection structure which provides the electrical, mechanical and thermal support for multiple bare chips and possibly other components (Turlik, 1992). They are generally used to concentrate the most dense, high-speed and performance-intensive aspects of a system on one or a few high-performance substrates (Balde, 1990). Until the mid-I980s, the electronic industry’s multichip substrate needs were normally met by ceramic-based hybrid integrated circuits (HICs). HICs were the first widely used MCM technology, whose biggest strength lay in its extensive passive component capability. This mainly alumina-based substrate technology has reached a well developed status (Tummala, 1989) with a broad range of applications in the automotive, telecommunications, and computer industries. In these applications the technology has increasingly bumped up against its limits in the arena of overall density and speed. Three basic categories of MCMs have been generally accepted as characterizing the range of all MCM applications: MCM-C, MCM-D, and MCM-L (IPC. 1990). They are characterized by their fabrication method and dielectric material type (Turlik, 1994). There is also some usage of composite names, e.g., MCMDL, when a combination of two processes is used in one type:

MCM-C. These modules are constructed of ceramic or glass-ceramic materials. The conductors are made of fireable metals such as tungsten (W) and molybdenum (Mo), or by using a screenable frit metal such as gold (Au), silver (Ag), palladium (Pd), and copper (Cu). MCM-D. These modules are formed by depositing thin-film multilayer conductors such as copper (Cu), aluminum (Al), or gold (Au) on unreinforced organic or inorganic dielectrics over a support structure of silicon, diamond, ceramic, or metal. MCM-L. These modules are built using laminated printed circuit board technology. These laminates may be reinforced. The conductors are normally additively deposited or subtractively defined copper.

The two strongest drivers for the implementation of modern MCM components in the commercial market-place in the late 1990s are: 1) the need for minimization of overall system-level cost, and 2) the demand for smaller and lighter electronic equipment. In the past, MCM cost has not been an issue of primary importance compared to the need to provide performance critical subsystems. As lower-cost MCM production methods have been developed, a market for using MCMs as a way to reduce system level cost has emerged (Thompson, 1995). Though the cost of an MCM may be greater than the parts cost of the equivalent single-chip packages and discrete components it replaces, it is often possible to build a more cost-effective system using MCMs. Proceedings (1994a-c, 1995a-c) and Balde et al. (1995) provide access to many of the ongoing state-of-theart MCM development and application activities.

67 1

12.6 Printed Wiring Board (PWB) Technology

12.6 Printed Wiring Board (PWB) ' rechnology

n I Single - sided rigid board

12.6.1 Introduction This section addresses printed wiring hoard (PWB) technology from the per< pective of a prospective user. It presents an overview of the major technology op1 ions and the most commonly applied pro( esses. Early electrical systems used discrete \vires and bus-bars to interconnect termii;als with one another. In 1925, the Ducas ~'atent(Ducas, 1925) first introduced the c oncept of patterning a planar, conductive toil and etching away everything but the desired conductive paths. These were the liumble beginnings of the PWB industry. PWBs perform an analogous interconiiection function as MCMs, but generally on a larger scale. Most electronic equipiiient requires that a minimum of volume i nd weight be consumed in providing the 1 interconnections, and therefore utilizes PWBs rather than discrete wires. Their application ranges from disposable, finite-life consumer electronics to the highest relii bility space electronics. In these applicat ions, as well as practically all other elect ronic systems, printed wiring functions i s the primary interconnection medium (Combs, 1987). Laminating a copper foil sheet to one or both sides of a glass-reinforced epoxy, rlolyimide or other polymeric substrate 1- xms a single-sided or double-sided lamir ate. Applying various patterning, drilling L nd metalization processes creates an int :rconnection circuit, An interconnection circuit with copper metalization on one aide of the plastic substrate, called a singlesided circuit, is the simplest form of PWB. IVhen both sides are metalized and patt :rned, it is called a double-sided circuit.

Double - sided ngid board

Figure 12-26. Typical cross-section of a single-sided PWB and a double-sided PWB.

See Fig. 12-26 for typical cross-sectional views. If a multiplicity of double-sided circuits is laminated and interconnected together, the resulting assembly is called a multilayer board (MLB). Figure 12-27 illustrates a high-density MLB intended for mounting surface mount devices on both surfaces. 12.6.2 Material Systems The dielectric material selected for a PWB application will be largely determined by its usage and reliability requirements as well as its market availability and cost, The dielectric substrate can be a thermoplastic or thermosetting resin used alone, or with a reinforcing material in the form of a web, matt, or randomly oriented fibers. Among the dielectric materials commonly used are phenolic, epoxy, triazine,

Figure 12-27. Isometric sketch of a MLB with surface-mounted devices on top and bottom.

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12 Interconnection Systems

rules) is dictated by the limitations of the manufacturing process. The low glass transition temperature of many of the commonly used plastic substrate materials places environmental restrictions on the application and usage of the PWBs in actual field situations. In addition, this precludes using some of the traditional processes used for metalizing and for fabricating passive devices on MCMs and HICs (Turlik, 1992). The most widely used PWB dielectric material, FR-4, consists of mats of woven fiberglass cloth which is impregnated with epoxy which has been bromated for greater fire retardancy. Its glass transition temperature is 140°C. However, in order to avoid discoloration and gradual deterioration of properties, it should not be operated for extended periods at temperatures greater than 120 "C. Because the ma-

polyimide, polyester, tetrafluoroethylene, polyamides, and polysulfones. The most frequently used dielectric material systems, listed in the order of decreasing annual sales volume, are epoxy (generally reinforced with fiberglass), phenolic (paper reinforced) and polyimide (often glass or kevlar fiber-reinforced). Epoxy glass is dominant in the mid-range market segment and is widely used in all segments. Phenolic paper, the next in volume, is most widely applied in the lowest cost/performance market segment such as disposable consumer products. Polyimide is a distant third in overall volume and is used predominantly for high electrical performance applications or in high temperature environments. See Table 12-2 for a comparison of their properties. The maximum wiring density of the circuit (as achieved with the finest design

Table 12-2. Properties of various PWB resins. Resin

G-1OFR RSM-1212 Quatrex 5010 RSM-1151 G-200 BT2100F BT2060BG Kerimid RSM-1206 RDX 64826 XU-71787 UDEL ULTEM Victrex

Generic type

FR-4 epoxy FR-4 epoxy Tetra func. epoxy Tetra func. epoxy BT epoxy BT Modified-BT Polyimide Polyimide Cyanate ester I Cyanate ester IV PTFE Polysulfone Pol yetherimide Polyether sulfone Poly olefin Pol ybutadiene Polyphenylene oxide Polycarbonate

Glass transition temperature, T,

('F)

125 125 180 180 185 250 220 215

255 255 355 355 365 480 430 525

260

500 500

'60 ..

192 212

375 115 445

'30 -

85 195

185 385

Relative permittivity

3.6 3.6 3.6 3.6 3.2 3.1 2.9 3.2 3.1 2.8 2.0 3.0 3.1 3.5 2.3 2.8 2.55 3.0

Loss tangent

0.032 0.032 0.032 0.032 0.012 0.003 0.001 0.02 -

0.005 0.004 0.0002 0.004 0.0065 0.0035 0.002 0.005 0.0007 0.001

12.6 Printed Wiring Board (PWB) Technology

jority of PWBs in the world are made with FR-4, its material cost reflects that of a mature product (Harper, 1969). As a result, when better properties are needed, the material cost premium paid for other dielectrics can be substantial.

12.6.3 PWB Categories PWBs can be manufactured as either rigid or flexible structures. In addition, there is a hybrid structure called discrete wired circuits.

12.6.3.1 Rigid PWBs Most of the PWBs designed and manufactured today are mechanically rigid. T’iey generally serve an electrical interconncction function as well as serving as a mechanical assembly platform. In addition to being planar single-sided, double-sided 01 multilayer boards, PWBs could also be molded into a 3-D shape which performs a structural function. Such PWBs tend to be single-sided and generally serve relatively modest interconnection functions. They are made up of an injection molded, extriided or thermoformed thermoplastic r e i n upon which electrically conductive interconnects are formed. These can be formed by means of screened or printed conductive inks, or by employing additive or subtractive technology on a copper film pl,tted on the molded substrate.

12.6.3.2 Discrete Wired Circuits The discrete wired circuit is another variation of the rigid PWB. In this case the inner core structure is typically fabricated as an MLB. It generally provides power and ground planes. The signal interconnedions are achieved by discrete individual insulated wires machine-placed into an adhesive spread on the surface of the core

673

PWB. The wire is terminated by drilling through it and the underlying copper pads and subsequently electroplating copper into the holes. Discrete wired circuits can achieve very high interconnection densities with a single layer of wiring since the insulated wire can form cross-overs and effectively occupy a high percentage of available wiring channels.

12.6.3.3 Flexible PWBs Flexible circuits are made on nonrigid substrates so they can be bent, within the limits imposed by the equipment design, to impart particular design advantages. Allowing the circuit to bend repeatedly requires that the conductor, adhesive and cover layer material also be flexible, in addition to the base substrate. Flexible circuits can typically produce weight and volume reductions on the order of 50% compared to equivalent round-wire interconnection assemblies (Shepler and Casson, 1989). In appropriate applications, assembly and installation costs are generally reduced and wiring errors can be all but eliminated. The lower mass of flex circuit assemblies, compared to round-wire, also allows the use of smaller, less expensive cable restraints. However, since flexible circuits are quite thin, they are often more difficult to repair than rigid boards. Flexible circuit assemblies are typically replaced, rather than repaired. A particular design application may entail flexing of the circuit on a continual basis (such as the type of circuit often used to connect to PC printer heads), or it may involve flexing and bending once, in the equipment assembly process (such as is frequently done in compact consumer equipment such as cameras and camcorders). They are generally applied to miniaturized box packaging systems in design situations

674

12 Interconnection Systems

where their properties can be exploited to gain a saving in system cost. size. weight and space. A protective coating is generally employed over the circuitry. This is applied to the conductor side of the circuit to shield it from possible Contaminants. moisture or mechanical damage. as well as to reduce the stress on the conductors during flexing. The protective coating can be one of three types 1 Insulating. adhesive coated films. This

film typically has pre-drilled or punched holes to provide for access to pads and features. The thickness of the film is selected to be the same as the base flexible substrate. When the coated film is laminated to the substrate under heat and pressure. the resulting assembly has the conductors located in the center, near the neutral axis. This minimizes the stress in the conductors during flexure and maximizes their fatigue life. 2. Photosensitive film solder masks. Two variations of these solder masks exist dry-film and liquid. The dry-film solder mask is applied by vacuum lamination to the flexible circuit under heat and pressure. Liquid solder masks are applied to the flexible circuit by means of a roller, spraying or curtain coating. Both types of films are subsequently put through standard photo processing steps to define the pad access holes and other features. This method can yield very high resolution on the features, but can also be relatively expensive. 3. Screen-printed cover coats. Polymer resin is screen-printed onto the flexible circuit, covering all areas except for the exposed pads. These resins are usually UV curable and need no solvent thinning.

The bonded-flex (also called rigid-flex) board is a special kind of composite flex circuit in which a flexible circuit is bonded to rigid dielectric support planes. The rigid planes provide an assembly platform for components to be mounted and terminated using cost-effective, conventional technologies. The exposed portions of the flex circuit are confined to restricted areas of the wiring plane. These flex circuit sections serve to interconnect the rigid boards and allow the final assembly to be folded into compact and complex shapes, with all the boards already pre-interconnected. This approach is very effectively applied in producing light and compact notebook personal computers, cameras and camcorders.

12.6.4 PWB Production Processes 12.6.4.1 Basic Processes

Producing interconnection traces on a dielectric substrate entails patterning, plating and etching in subtractive or partially additive processes. It involves patterning and plating in fully additive processes. Figure 12-28 depicts the two most common fabrication sequences in use today, the “print and etch” and the “print, plate and etch” processes (Wargotz, 1992). Though the fully additive “print and plate” process is conceptually very simple and appealing, in practice it is not as well developed and broadly applicable as the other two processes. Print and Etch

The “print and etch” process is useful only for PWBs without plated-through holes. This includes single-sided PWBs, double-sided PWBs without plated-through holes, and inner layers of multilayer boards without buried vias. In this process sequence, the starting point is a dielectric

12.6 Printed Wiring Board (PWB) Technology A - Print and etch

675

B - print,plate and etch

Copper-clad laminate

Reverse-printed organic resist 1)

’)

Pri

Electroplated etch resist

ist 2)

Organic resist removed 3)

r 1 Finished circuit

Electroplated Metal

Laminated Plastic

Etched

! d E L B u u

CopperFoil

Printed Resist

wbstrate with a copper foil coating whose thickness has the desired thickness of the final copper traces. This might typically be 1/2, 1 or 2 oz. copper (17.5, 35 or 70 pm i hick). Interconnection traces are formed, as depicted in Fig. 12-28 a, by printing and developing a positive photoresist pattern of the desired circuit on the original copper foil. Typically, the photoresist is a photodefinable polymer. The desired circuit is then obtained by etching away the unwanted copper which was not protected by the resist coating. The simplicity and minimal number of processing steps is a major advantage of the print and etch process. Another advantage is the ability to use thin photoresist. The major disadvantage of this process is the need to etch away the full thickness of the unwanted copper in the non-circuit portions of the PWB. Since most etchants and etch processes are isotropic, Le., a conductor line gets undercut to the same ex-

Figure 12-28. Subtractively produced PWBs.

tent as its thickness is etched, the finest feature which can be produced is limited. A general rule of thumb for isotropic etchants is that the finest feature which can be reproducibly generated in the limit must be greater than twice the copper thickness being etched. Print, Plate and Etch The “print, plate and etch” process is used for PWBs with plated-through holes (PTHs). This includes double-sided PWBs, MLB inner layers with buried vias, and laminated MLBs. The process also works on PWBs without holes, as long as the starting point is a board with thin blanket metalization. In this process sequence, the starting point is a dielectric substrate which has a thin initial copper coating everywhere. The primary function of this copper is to short everything on the surface of the substrate

676

12 Interconnection Systems

together to allow an electroplating process to be used to plate the interconnection traces. A negative photoresist image of the desired interconnection trace pattern is first printed on the copper. Then the interconnection pattern is electroplated to the final desired copper thickness. The exposed, plated copper areas are then electroplated with an etch resist coating, usually tin or solder. The negative printed image of the traces is then removed and the underlying copper chemically etched away to produce the desired interconnection circuit. A major advantage of the print, plate and etch process is that thin copper can be used for the initial metalization, which minimizes line narrowing from etching. In addition, the finished conductor cross-sectional shape is largely determined by the geometry of the patterned photoresist and is thus immune to the etch undercutting problem of the print and etch process. A major disadvantage of the process is the difficulty of defining fine features in the relatively thick (37- 50 pm) photoresist. The lack of thickness uniformity from electroplating over the surface of a panel is another problem.

Plated- Through Holes When two-sided circuits are made, it is necessary to electrically interconnect the two sides in selected places with platedthrough holes (PTHs). This is done by means of holes (generally made by drilling) which are subsequently plated with copper. The drilled hole and adjacent copper surfaces being interconnected are first additively coated with electroless copper. Electroless copper deposition is extremely slow and is therefore an impractical process to use for achieving the final required copper thickness. It is only used to make

the holes electrically common with the sheets of copper on both sides of the substrate, prior to electroplating in the print, plate and etch process which is applied to produce the patterned circuitry, including the holes.

12.6.4.2 Fabrication Sequences for Different PWB Types Single-Sided Circuits Single-sided circuits are the simplest variety of PWB because PTHs are not required when all the circuitry is on only one side. Both the plate and etch and the print, plate and etch process sequences shown in Fig. 12-28 can be applied. Any holes required in the circuit can be made either before or after the interconnection traces are formed, because no plating is applied to them.

Double-Sided Circuits A typical fabrication sequence for double-sided rigid (DSR) printed wiring circuits is depicted in Fig. 12-29. The “print, plate and etch” process is applied. The result is a double-sided board with PTHs and either bare copper or tin-plated interconnection circuits. These can be used as component layers for a multilayer board (requires bare copper option). Or they can be made into finished DSR boards after going through the appropriate additional steps indicated in Fig. 12-29.

Multilayer P WBs Figure 12-30 depicts the multilayer board (MLB) fabrication sequence. The inner core layers, made from thin (generally 75 to 200 pm thick) dielectric laminate circuits, are individually fabricated following the bare copper DSR process just discussed. The appropriately patterned inner

12.7 Future Directions

I Drill holes

677

:I Hole preparation

iEiectroi’i,s copper]

Solder mask and nomenclature

Hot air solder

and develop

Electroplated

copper and solder

u [I Strip resist

Pack and ship

mre layers are then stacked up with intervzning sheets of B-stage (partially cured) dielectric sheets. These layers are all very c*trefully aligned with respect to one another and placed in a lamination press 1 hich bonds the assembly into one contiguous board under heat and pressure. The resultant assembly is then treated as a DSR board to form the final MLB, with hole drilling, plating, printing and etching.

Figure 12-29. Typical manufacturing sequence for DSR boards.

the analogous processes are used as for rigid boards. However, for large volume flex circuit production, a continuous rollto-roll production process can be employed to provide the very lowest cost. Flex circuits are frequently designed to be produced with non-rectangular form factors. They can be designed to be folded into complex shapes to support three-dimensional interconnection structures in densely packaged electronic systems.

F!exible Circuits Flexible, or flex, circuits are typically made as single-sided, double-sided, or sometimes multilayer circuits. These can br made exclusively of flex material, or of a combination of flex and rigid material (ti) produce bonded-flex PWBs). Generally

12.7 Future Directions The electronics industry is under continual, relentless pressure to turn out products which are better, faster and cheaper

678

12 Interconnection Systems

Etch Internal Layers

Stack For Lamination

Inner Layers Interspersed with &Stage

Unetched Copper Layer

Laminate

Drill Holes

_1_1 Electroless 8 Electroplate Copper

Figure 12-30. Typical manufacturing sequence for multilayer boards.

than those which came before. Players in the electronics industry have to match their product development cycles with the electronics industry’s development curve in order to compete effectively. The computer, telecommunications and consumer electronic product segments of this industry aggressively pace this curve with development time frames which are in the range of six to 18 months (Asthana, 1995). These short time frames are particularly difficult to accommodate in the market-place because the traditional product qualification cycle time can last longer than the length of the entire development cycle.

12.7.1 Merging of Markets There are three primary consumer-driven electronics markets : 0 entertainment delivery to consumer 0 computing services 0 communications capabilities

These services have increasingly common characteristics. Over time the electronic equipment which will be providing these services will essentially be identical. It will be electronic equipment designed for the reception, transmission, manipulation and display of digital data streams. Figure 12-31 provides a pictorial representation. There will be differences in the form and the function of the information, but electronically speaking, the differences will be minor and easily accommodated within the equipment design.

12.7.2 New Form of Consumer Services The concept of providing services to the consumer has undergone a drastic change in the 1990s. What has emerged out of the reformulation of the way of meeting the electronic information needs of the worldwide consumer is quite different from what existed in earlier eras. The new consumer

12.7 Future Directions

679

Voice

Information

Data

Figure 12-31. The many separate electronic industry segments of the 1990s are moving toward one merged global information industry.

Text Generation

Processing

Storage

Transmission

information

szrvices can be characterized by the follow1ng: all digital content high information bandwidth needs audio, video or data content (the digits do not care what kind of data are transmitted) capacity provided on demand that varies over time pricing proportional to usage The character of the new consumer ser\ices is quite different from those of the past. Delivery can either be on-line via a digital link to a service provider or off-line kia stored media such as tapes, floppy disks, compact disks or video disks. Online delivery means are increasingly the dominant choice of the modern consumer. This is driving the rewiring of the world, either physical wire or fiberoptic cable, or Kith digital radio links. There are three primary modes of transport for these digit'il data: e

Telephone network In principle the telephone network is the right kind of network for providing asynchronous information to widely disparate destinations on demand. Its greatest advantage is that it is largely in-place in much of the world. Its prima-

ry drawback is that there is insufficient electrical bandwidth available in the loop network, close to customers. e Cable TI/ network The present cable TV network has a lot of electrical bandwidth, but is non-interactive (one-way) and in a non-switched network. 0 Direct broadcast satellites This method has a great advantage in rural areas in that it does not require the stringing of cables and wiring which the other methods require. However, it may be less cost effective in more densely settled urban areas.

12.7.3 Evolution of Technology Most progress in technology is by means of many evolutionary steps. Technology developments are usually the taking of the most logical next steps in moving forward to the next generation of product design. In the latter 199Os, this has meant, on the component level, the increasing application of cost- and space-efficient packaging techniques such as ball grid arrays (BGA), tape automated bonding (TAB), direct chip attach (DCA), chip scale packaging (CSP), flip chip (FC), and chip-on-board (COB). This movement comes from the need for increased component level 110

680

12 Interconnection Systems

counts as well as higher operating speeds and denser packaging. These components are being mounted on smaller, denser PWBs and MCMs to provide cost-effective electronic modules. Efficiently providing all these services requires fundamental changes in the electronic infrastructure of the entire world. The impact on the interconnection systems providing this infrastructure for future electronic services is quite immense. Electronic interconnection system developments must keep up with the furious pace of development of the worldwide electronics industry.

12.8 References Ambekar, S. M., Hamilton, W. E., Cole, T. E. (1987), A T & T Tech. J. 66 141, 87. Asthana, P. (1995). IEEE Spectrum 32 ( 6 ) , 49. Balde. J. (1991), “New Packaging Strategy to Reduce System Costs”, in Multichip Modules: System Advantages, Major Constructions, and Materials Technologies: Johnson, R. W., Teng, R. K. F., Balde, J. W. (Eds.). Piscataway, NJ: IEEE Press, p.7. Balde, J., Garou, P.. Nelson, J., Van Loan, P. (Eds.) (1995) Compendium ofpapers 1992-1995, h i . Conf: and Exhibition on Multichip Modules. Reston, VA: ISHM, The Microelectronics Society. Combs, Jr., F. (Ed.) (1987), Printed Circuit Handbook, 3rd ed. New York: McGraw-Hill. Ducas, J. (1925). CJ. S. Patent 1563 731. Goddard, C. T. (1979), IEEE Trans. Compon., H y brids, Manuf, Technol. CHMT-2. 367. Harper. C . (1969), Handbook of Electronic Packaging. New York: McGraw-Hill. Hoover. C. W., Harrod, W. L., Cohen, M. I. (1987), A T & T Tech. J. 66 ( 4 1 , 4. IPC (1990). IPC-MC-790. Lincolnwood, IL: Institute for Interconnecting and Packaging Electronic Circuits. Knausenberger, W. H., (1992), “Interconnection Trends in Telecommunications”, in Proc. 1992 In?. Electronics Packaging SOC. Conf., Austin, T X . Wheaton, IL: IEPS, pp. 27-30. Knausenberger, W. H., Schaper, L. W. (1984). IEEE Trans. Compon., Hj,brids, Manuf. Technol. CHMT-7, 261. Pinnel, M. R., Knausenberger, W. H. (1987), A T & 7 Tech. J. 66 14,. 45. Proceedings (1994a) Proc. 1994 Int. Electron. Packaging Cor$, Atlanta, G A . Wheaton. IL: IEPS.

Proceedings (1994 b), Proc. 44th Electron. Compon. Technol. Conf., Washington, D C . Piscataway, NJ: IEEE. Proceedings (1994c), Proc. 1994 Int. Con$ on Multichip Modules, Denver, C O . Reston, VA: ISHMThe Microelectronics Society. Proceedings (1995a) Proc. 1995 Int. Electron. Packaging Society Conf., Sun Diego, C A . Wheaton, IL: IEPS. Proceedings (1 995 b), Proc. 45th Electron. Compon. Technol. Conf., Las Vegas, N K Piscataway, NJ: IEEE. Proceedings (1995~1,Proc. 1995 Int. Conf. on Multichip Modules. Denver, CO. Reston, VA: ISHMThe Microelectronics Society. Rust, R. D. (1989), Introduction to the General Problems in Production ofFine Lines, Paper 799. Lincolnwood, IL: Institute of Printed Circuits Technology. Shepler, T. H.. Casson, K. L. (1989), in Electronic Materials Handbook, Vol. 1. Materials Park, OH: ASM International, p. 579. Sutherland. I. E., Mead,C. A. (1977), Sci. Am. (Sept.) 210. Thompson, P. (1995), IEEE Trans. Compon., Packaging Manuf. Technol. A , 18, ( 1 ) , 10. Tummala. R. (1989), “Ceramic Packaging”, in Microelectronics Packaging Handbook: Tummala, R., Rymaszewski, E. (Eds.). New York: Van Nostrand, Chap. 7. Turlik, I. (1992), “Background to MCM Technology”, in Thin Film Multichip Modules: Massnar, G., Turlik. I., Balde, J., Garrou, P. (Eds.). ISHM Technical Monograph. Reston, VA: ISHM, Chap. 2. Turlik, I. (1994). “Interconnect Substrate Technologies”, in Physical Architecture of V L S I Systems: Hannemann, R., Kraus, A,, Pecht, M. (Eds.). New York: Wiley, Chap. 3. Wargotz. W. B. (1992), “Communication Printed Wiring Interconnection Technology”, in The Froehlichl Kent Encyclopedia of’ Telecommunications. New York: Marcel Dekker, p. 305. Wessely, H.. Fritz, O., Horn, M., Klimke, P., Koschnick, W., Schmidt, K.-H. (1991), IEEE Trans. Comp.. Hybrids. Manuf. Technol. CHMT-14, 272. Wilson, D. K. (1980), Des. Stud. I , 245.

General Reading Doane. D. A., Franzon, P. D. (Eds.) (1993), Multichip Module Technologies and Alternatives: The Basics. New York: Van Nostrand Reinhold. Fink, D. G., Christiansen, D. (1989), Electronic Engineers’ Handbook, 3rd ed. New York: McGraw-Hill. Ginsberg, G. L. (1990), Printed Circuits Design. New York: McGraw-Hill. Ginsberg, G. L. (1992), Electronic Equipment Puckaging Technology. New York: Van Nostrand Reinhold.

12.8 References

;insberg, G. L., Schnorr, D. (1995), Multichip Modules and Related Technologies: MCM, T A B and C O B Design. New York: McGraw-Hill. llwang, J. S. (1995), Ball Grid Array and Fine Pitch Peripheral Interconnections. Pennington, NJ: Electrochemical Society. I .au, J. H. (1994), Chip on Board Technologies f o r Multichip Modules. New York: Van Nostrand Reinhold. !.au, J. H. (1994), Handbook of Fine Pitch Surface Mount Technology. New York: Van Nostrand Reinhold.

(

681

Lau, J. H. (1995), Bell Grid Array Technology. New York: McGraw-Hill. Lau, J. H. (1995), Flip Chip Technologies. New York: McGraw-Hill. Manko, H. H. (1992), Solders and Soldering: Materials, Design, Production and Analysis f o r Reliable Bonding, 3rd ed. New York: McGraw-Hill. Marcoux, P. (1992), Fine Pitch Surface Mount Technology. New York: Van Nostrand Reinhold.

INDEX

Index Terms

Links

A A defects

abrasive polishing

abrupt junction approximation accelerated crucible rotation technique (ACRT)

545 93

acceptors – annealing

562

– doping

274

– gallium arsenides

165

– indium phosphides

173

– metallization

acetic acids

acid catalyzed deblocking

225 221 f

acid catalyzed photocrosslinking

206

acid etchant

297

acid hardening resists (AHRs)

208

acidic phenol groups

218

acidic solution etching

506

583 f

– silicon

acid catalyzed cleavage

500 f

activation energy – deblocking

222

– doping

273

activation processes, doping

507

active devices

499

active regions, silicon devices

413

adhesion promoters

196

advanced application specific integrated circuits (ASIC)

194

advanced carbothermic reduction (ARC)

This page has been reformatted by Knovel to provide easier navigation.

Index Terms advanced isolation techniques, silicon devices

Links 420 ff

AlGaAs growth

166

AlGaAs/GaAs red light emitting diode (LED)

394

alkaline developers, photocrosslinking

205

alkaline soluble polymers, photolithography

218

alkaline solution etching alkyl bis(p-azidobenzal)cyclohexanones (ABC)

39 204

alloying – metallization

585

– Schottky barriers

556

alumina

640 f

– dielectric constants

570

alumina ceramic

633

aluminothermic reduction

aluminum – chlorine etching

329

– endpoint monitoring

306

– interconnections

458

– metallization

548

– Schottky barriers

553

aluminum compounds aluminum deposition, contacts aluminum etching

670

494

581 ff

– ohmic contacts

– wire bonding

494

615 ff 84 452 301 f

aluminum gallium arsenides

493 ff

aluminum impurities, silicon

aluminum–oxygen complexes

520

amine-promoted image reversal

235

amorphous silicon, low pressure chemical vapor deposition

477

anhydrous HF (AHF), dry cleaning

473

annealing

413 ff

– doping

270

502 f

– ion implantation

278

282 f

521

This page has been reformatted by Knovel to provide easier navigation.

560 ff

Index Terms

Links

annealing (Cont.): – ohmic contacts

548

anode etching

301

– doping

537

antimonides

73 f

antimony doping

antimony preamorphization

441

antimony solvents, liquid phase epitaxy

141

antireflective coatings (ARC) – photoresists

237

– solar cells

386

application specific integrated circuits (ASICS)

448

Arrhenius equation

138

arsenic diffusion, silicon arsenic doping

273 f 24

arsenic vapor pressures

564

arsenides

73 f

AsH3, molecular beam epitaxy

162

505

ashing – dielectrics

573

– doping

540

atomic absorption spectroscopy (AAS)

195

atomic contaminants

atomic diffusion mechanism

269

atomic force microscopy (AFM)

201

Auger electron spectroscopy

147

avalanche breakdown, IMPATT diodes

380

avalanche cold cathode device

372

AZ AQUATAR, photoresists

239

azido groups, photocrosslinking

204

B back–end processing, integrated circuit packaging back surface damage, silicon backgating

612 55 497

522 f

This page has been reformatted by Knovel to provide easier navigation.

273

Index Terms

Links

back-plane connections

581

backscattering effects, photolithography

188

backside processing

590 ff

baking

497

ball grid arrays

611

629

– doping

500

529

– silicon devices

345

352

barrel etchers

300

barrel reactor, dielectrics

573

barrier injection transit time (BARITT) diode

346

382

barrier metals

581

584 f

632

band-gaps

Benard cell

benzil

206

benzocyclobutane (BCB)

205

benzophenone

206

beryllia ceramic

633

beryllium – doping

500 f

506

– gallium arsenides

165

276

bias voltage

310

biasing conditions, silicon devices

348

bilayer gate structure, Schottky barriers

558

bilayer systems, contrast enhancement

236

binary compounds, liquid phase epitaxy

141

bipolar complementary metal-oxide semiconductor (BICMOS)

365

bipolar inversion channel field-effect transistor (BICFET)

357

bipolar junction transistor (BJT)

402

bipolar transistors

529

348 ff

bird’s beak transition

419

bismuth solvents, liquid phase epitaxy

141

blue-green semiconductor diode laser

405

boiling points – silane

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

boiling points (Cont.): – silicon

Boltzman–Matano analysis

274

Boltzmann constant

553

bond cleavage photopolymerization

206

bonding interface, device isolation

429

bonding methods, integrated circuit packaging

612 ff

bonds – epitaxial growth

121

– silicon chemical vapor deposition

154

159

boron – annealing behavior

287

– ion implantation isolation

519

– metallization

449

– SIMS profile

446

boron doping

505

– photolithography

183

– shallow junctions

440

– silicon

boron impurities, silicon

boron nitride boats, crystal pulling

76 ff

borosilicate glass (BSG)

442

bottom antireflective coatings (BARC)

237

boule qualification process

510

bound interstitial impurities, Czochralski silicon boundary conditions, predeposition

273 f

47 270

boundary layers – chemical vapor deposition – silicon

134 27

breakage, backside processing

591

breakdown voltage – p-n junctions

419

– rectifier diodes

– silicon devices

349

This page has been reformatted by Knovel to provide easier navigation.

Index Terms bridge structures, backside processing

Links 591

Bridgman technique – compound semiconductors

80 f

– mercury cadmium tellurides

broadcast interconnections

668

broken bonds, epitaxial growth

121

bromine chemistry

320

bromine containing compounds

539

Bronsted acid

208

brush damage

330

bubble formation – device isolation

429

– etch doping

536

bulk metal impurities bulk processing, silicon Burgers vector

12 6 277

buried layers, doping

502 f

buried oxide (BOX) isolation

421

burring, liftoff processes

589

Burton–Prim–Slichter (BPS) model butyloxycarbonyl (t-BOC) groups

508

222 f

C C4 process technology

614

618

500

506

cadmium – doping – ultra-pure

– zone refining

cadmium acceptors – gallium arsenide

165

– indium phosphides

173

cadmium selenides

cadmium sulfides

cadmium tellurides – compound semiconductors

73 ff

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

cadmium tellurides (Cont.): – crystal growth

– melting points

cadmium zinc tellurides

capacitor model, silicon devices

347

capping layers, doping

270

carbon

carbon black powder

carbon concentration, gas source epitaxy

513

carbon doping

500

– gallium arsenides

165

carbon–hydrogen bonds

204

carbon layers, photoresists

241

carbothermic reduction, silica

505

carrier concentration – epitaxial growth

114

– silicon devices

348

carrier mobilities, doping

499

carrier recombination, silicon surfaces cascade semiconductor laser cast recrystallize anneal (CRA)

41 405 92

cathode operations, etching

301

cationic initiated photopolymerization

206

caustic etchants

cavity up/down, integrated circuit packaging

624

ceramic-based hybrid integrated circuits

670

ceramic-integrated circuit packaging

619 ff

ceramic multichip modules (CMC)

637

ceramics, interconnections

670

change and repair, integrated circuit packaging

636

640 f

channeling – doping

507

– ion implantation

281

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

channels – field-effect transistors

397

– resistors

576

– silicon devices

362

charcoal

charge carriers, silicon devices

348

charge coupled devices (CCD) – photodetectors – silicon

383 360 ff

charge transport, nonvolatile memory

369

charge trapping, gate dielectrics

430

charged defects, doping

274

charging, doping

523

chemical amplification of resist lines (CARL)

249

chemical beam epitaxy (CBE)

513

chemical cleaning – DRAM

331

– silicon contamination chemical etching – silicon

40 298 39

chemical formulations, etchants

535

chemical mechanical polishing (CMP) – etching

326

– interconnections

467

– photoresists

203

– shallow trench isolation

423

– silicon devices chemical properties, epitaxial growth chemical reactivity, compound semiconductors chemical structures, Norrish photoinitiators

367

114 78 207

chemical vapor deposition (CVD) – cluster tool technology

471

– dielectrics

571

– epitaxial growth

114

117

103 f

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

chemical vapor deposition (CVD) (Cont.): – gate oxides

438 f

– metallization – silicon

453

582

chemically amplified resists (CAR) – deblocking

226

– photopolymerization

204

chemically modified gate oxides

208

435 f

chemistry – photoresists

203 ff

– silicon chemical vapor deposition

156 f

chip carriers

611

627

chip on board (COB) technology

657

662

chip size

632

chlorine chemistry, etching

320

329

chlorine containing compounds, doping

539

chlorosilanes, silicon

11 f

157

– doping

500

509

– endpoint monitoring

306

– thin film resistors

580

chromium

chromium diffusion – gallium arsenides – silicon

276 9

circuit parameters, GaAs FET

400

cladding

463

clean room facilities, device processing

493

412 f

cleaning – backside processing

591 f

– device processing

497

– DRAM

331

– etching

297

– gate dielectrics

430 ff

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

cleavage – backside processing

591 f

– deblocking

225

– device processing

493

– photopolymerization

206

cleavage twinning closed tube diffusion closed tube techniques cluster tool technology, metallization coal

26 511 73 469 ff 8

coating, photoresists

196

coating films, printed wiring board

674

cobalt

413

cobalt silicides

455

Cochran analysis

cofired ceramics

633

coimplantation

506

coinitiators, photopolymerization

206

co*ke

cold-wall CVD reactors

132

collars, cluster tool technology

479

collector barrier, hot-electron transistor

379

collector base junction

351

complementary metal-oxide semiconductors (CMOS)

363

– device isolation

418

– metallization

448

– rapid thermal processing

477

complemetary heterostructure FET (C-HIGFET)

495

component oriented partitioning

666

compound semiconductor device processing

489

compound semiconductor processing concentration dependence, doping

137

495

67 270 ff

conducting regions, epitaxial growth

114

conduction band, group III–V semiconductors

395

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

conductivities – backside processing

591

– epitaxial growth

114

connections, metallization

581

connector mask, DRAM

333

constitutional supercooling – compound semiconductors

– crystal growth

– silicon

27 f

contact etching

323

336

contact holes – interconnections

458

– metallization

448

contact mask, DRAM etching

333

contact pad via openings

557

contact plug technology

459

contact printing contact resistance

337

185 ff 551

contacts – metallization

452

– Schottky barriers

552

contaminations – backside processing

591

– compound semiconductors

74 f

– dielectrics

569

– doping

511

– etching

296

– metal–silicon contacts

359

– silicon devices contrast enhancement layer (CEL)

412

236

control – diagnostic tools – etching – interconnections

312

317 f

296 f

305 ff

669

This page has been reformatted by Knovel to provide easier navigation.

Index Terms convection, silicon pulling

Links 30 f

cooling rates – annealing

560

– silicon

copper – endpoint monitoring

306

– etching

330

– interconnections

458

– metallization

670

273

412 f

583 f

copper diffusion, silicon

40 f

counter pressure, doping

270

counter rotation, silicon pulling

462

494

cover coats, printed wiring board

674

cracker cell, molecular beam epitaxy

151

cracking – dielectrics

571

– silicon

creep

cresol isomers

218

critical dimensions, etching

296

331

crosslinking – acid hardening resists

210

– diazo resists

235

– photoresists

204 ff

crucible rotations, silicon pulling

cryogenic fragmentation

cryomagnets

cryopanel, molecular beam epitaxy crystal diameters, silicon pulling

148 f 34

crystal growth – compound semiconductors – silicon crystal slip, annealing crystal structures

71 ff

79 ff

84 f

16 f

566 96

This page has been reformatted by Knovel to provide easier navigation.

Index Terms curing

Links 201

current–voltage characteristics – double barrier diode

377

– field-effect transistors

508

– microvacuum triode

372

– n-i-n diode

346

– ohmic contacts

545

– p-n-p-n diodes

355

cusp field effect

cutting, compound semiconductors

106

cyclopentanone

233

Czochralski crystal growth

24 ff

413

D D defects, silicon

damage – backside processing

591

– compound semiconductors

107

– dielectrics

430

– doping

507

– etching

296

299

– ion implantation

278

282 ff

521

– mask pattern

187 53 ff

324

– silicon

571

dangling bonds – dielectrics

569

– epitaxial growth

123

dash neck diameter

de Broglie wavelength deblocking, acid-catalized

375 221 f

decomposition, epitaxial growth

117

decoupling, multichip packaging

639

deep-etched slices, silicon

deep level states, annealing

569

deep trench isolation

320

This page has been reformatted by Knovel to provide easier navigation.

413

Index Terms deep ultraviolet (DUV) lithography

Links 187 ff

– Schottky barriers

558

deep ultraviolet curing

201

deep ultraviolet projection systems, photolithography

190

defect clusters

283

defect-diffiisant interactions

274

198

225

232

367

defects – compound semiconductors

– crystal growth

– doping

268

507

– epitaxial growth

114

118

– ion implantation isolation

519

– Schottky barriers

554

– silicon

412 f degradation, photoresists

232

delay time, chemically amplified resists

227

density of states (DOS) – group III–V semiconductors

395

– quantum effect devices

373

– Schottky barriers

554

denudation, silicon devices

414

dep-etch sequence

328

depletion region – device processing

496

– ohmic contacts

545

– Schottky barriers

552

– silicon devices

350

deposition processes, DRAM storage dielectrics

367

475 ff

depth of focus (DOF) – acid hardening resists

211

– interconnections

467

– photolithography

186 ff

depth profiles, ion implantation isolation

199 ff

518

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

desorption, chemical vapor deposition

138

development methods, photoresists

199

device characteristics, epitaxial growth

114

device failures, silicon

device isolation, silicon

412

device processing, compound semiconductor

489

device structures

391

– silicon

341

diameter control, crystal growth

418 ff

diamond lattice – crystal growth

– epitaxial growth

124

– silicon devices

413

diamond scribe

597

diazonaphtoquinones (DNQ) diazophotoresists diborane

214 f

229

234

234 18

dicing

612

die attachement

614

638

590 ff

597

die separation dielectric deposition

557

dielectric etching

301

dielectrics – device processing

567

– interconnections

670 f

dies

612

diffusion – 3 d metals in silicon – doping

413 268 ff

442 f

– epitaxial growth

114

125

– gallium arsenides

276

– liquid phase epitaxy

144

– silicon

diffusion barrier, metallization

511 ff

275

452

This page has been reformatted by Knovel to provide easier navigation.

525 f

Index Terms

Links

diffusion-enhanced silylation resists (DESIRE)

245

diffusion-induced dislocation networks

277

diffusion-limited etchants, doping

535

diffusion-limited precipitation, oxygen in silicon Dill parameters

49 216

dimensions, critical see: critical dimensions diodes – barrier injection transit time

346

382

– impact ionization avalanche transit time

346

380

– quantum effect devices

375

– silicon

346 f

dipping, liquid phase epitaxy

141

direct image reversal, photolithography

235

direct tunneling, nonvolatile memory

369

direct writing, photolithography

193 f

discharching. doping

523

discrete wire circuit, printed wiring board

673

disilane decomposition

136

dislocation-free silicon

25 f

dislocation loops dislocation networks

36 277

dislocations – compound semiconductors

– crystal growth

105

– silicon devices

displacement energy, ion implantation

412 f

282 f

displacement repair, annealing

561

displacements, doping

507

dissipation – integrated circuit packaging

610

– metallization

581

– resistors

579

dissolution – Czochralski silicon

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

dissolution (Cont.): – photoresists

19.

– silicon pulling

distillation, silicon

distilled water rinsing, gate dielectrics

432

distribution patterns, interconnections

668

DNQ novolac photorresists

241

204

214

500

506

donors – annealing

562

– doping

274

– gallium arsenides

165

– indium phosphides

173

– silicon

– compound semiconductors

74 f

– crystal growth

dopants

– epitaxial growth

116 f

– group III–V semiconductors

396

– metallization

451

– photolithography

183

– shallow junctions

440

– silicon

22 ff

doping – charge-coupled devices – device processing

362 494 f

– selective

265

– shallow trench isolation

423

– silicon

498 f

161

doping profiles – IMPATT diodes

380

– silicon devices

355

dots, quantum effect devices

373

double barrier quantum well (DBQW), quantum effect devices

375

double-barrier resonant-tunneling diode (DBRTD)

376

This page has been reformatted by Knovel to provide easier navigation.

Index Terms double diffusion front

Links 501 ff

double drift devices

381

double sided circuits

676

double sided printed wiring board

671

dovetail

532

drain engineering, MOSFETs

363

drain ohmic contacts

397

drift mobilities

499

drift vector

314

drive-in annealing

270

dry chemistry, isolation methods

516

512

529

dry cleaning – cluster tool technology

473

– gate dielectrics

433

dry etching

296 f

– device processing

298

495

– doping

531

537 f

– photoresists

202

dry film photoresists

205

dual in line package (DIP)

610

dyed photoresists

237

626

632

295 f

299

331 ff

– interconnections

456

653

– metallization

470

– photolithography

183

– photoresists

215

– silicon devices

412

– storage dielectrics

475

dynamic random access memory (DRAM) – etching

189

E edge dislocations

118

edge lifting, backside processing

594

edge rounding effusion cell

38 148 This page has been reformatted by Knovel to provide easier navigation.

Index Terms electric arc furnace process, silicon

Links 8

electrical properties – epitaxial growth

114

– integrated circuit packaging

633

– wire bonding

616

electrically active impurities

electrically erasable programmable read-only memory (EEPROM) electromagnetic stirring

368 33

electromigration – metallization

581

– Schottky barriers

558

– thin film resistors

580

electron affinity

553

electron beam lithography (EBL) – Schottky barriers electron beam writing electron bombardement, ion implantation isolation

193 f 558 585 f 521

electron cyclotron resonance (ECR) – etching

300

– plasma CVD

575

– p-n junctions formation

448

electron projection lithography

195

electron source, field-effect transistors

397

electron trapping, gate dielectrics

430

electron wind, thin film resistors

580

emitter-base junctions

351

– doping

534

emitters, solar cells

386

end-of-range (EOR) damage

507

endpoint diagnostic, etching

305 ff

enhanced diffusion, oxygen in silicon

enhanced gettering, silicon

epitaxial growth

304

537

495

111

This page has been reformatted by Knovel to provide easier navigation.

543

Index Terms

Links

epitaxial growth (Cont.): – compound semiconductors

107

– device processing

352

– silicon

494

501

epitaxial methods, doping

513

epitaxial structures, device processing

493

epitaxial systems

152

epitaxy – definition

116

– silicon

epiwafers

417

epoxy dielectrics

671

epoxy resins

207

erasable programmable read-only memory (EPROM)

368

erosion effect, silicon pulling

etch-back procedures

464

etching

291

– backside processing

591 f

– cluster tool technology

479

– compound semiconductors

107

– device processing

494 ff

– doping

531 ff

– gate dielectrics

430 f

– isolation methods

515

– metrology

312

– novolaks

229

– photolithography

182

– photoresists

201 f

– printed wiring board

674

– resistors

576

– Schottky barriers

556

– shallow trench isolation

423

– silicon ethyl lactate

247

233

This page has been reformatted by Knovel to provide easier navigation.

Index Terms ethylene diamine pyrocatechol (EDP)

Links 361

370

evaporation – compound semiconductors

– Czochralski silicon

– liftoffprocesses

588

– Schottky barriers

554

– silicon pulling

– metallization

453

excimer lasers – gas immersion doping – photolithography

447 187 f

excitation methods – dielectrics

572

– etching

299

exposure, photolithography exposure time, liquid phase epitaxy

182 ff 143

extended bulk epitaxy

extrinsic gettering

extrinsic semiconductors, doping

268

extrinsic stacking fault

118

F fabrication steps – integrated circuit packaging – interconnections – printed wiring board Fabry–Perot etalon

612 ff 670 676 ff 375

faceting – compound semiconductors – crystal growth

72 101 f

– epitaxial growth

121

– etching

298

– silicon

failure – diffusion doping

525

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

failure (Cont.): – gate oxides

416

– rectifier diodes

– silicon

– thin film resistors

580

failure mode analysis (FMA)

494

faults, ion implantation

429

285 f

Fermi level – dilelectrics

568

– doping

274

– Schottky barriers

552

– silicon devices Fermi surface

523

346 f 499

Fick diffusion – doping

269

– epitaxial growth

125

– oxygen in silicon

field-effect devices, silicon

358 ff

field-effect transistors (FET)

397 ff

field effects, resistors

579

field implant

334

526

field replaceable unit (FRU) – integrated circuit packaging – interconnections film forming polymers

633 656 f

663 f

226

film thickness – etching

305

– photoresists

184

196

fine pitch quad flatpack (FQFP)

611

632

flatpack(FP)

611

626

flexible circuits

677

flexible printed wiring board

673

flip chip bonding

614

floated-zone compound semiconductors

632

618 ff

This page has been reformatted by Knovel to provide easier navigation.

Index Terms floated-zone silicon

Links 16 f

floating-gate avalanche injection metal-oxide semiconductor (FAMOS) flow profiles, chemical vapor deposition fluidized bed reactor

368 133 11

fluorinated chemistry, etching

320

fluorination, gate oxides

437

fluorine, doping

505

fluorocarbon addition, etching

329

539

focus-lattitude enhancement exposure (FLEX), photolithography

192

focused ion beam (FIB) repair, thin film resistors

580

focused ion beam chemical vapor deposition (FIBCVD)

195

fomaldehyde

218

forward bias, silicon devices

348

four-layer devices

355

four-level interconnects

582

Fowler–Nordheim tunneling

369

Fr-4, interconnections

672

fracture – dielectrics

571

– silicon

fragmentation – photoresists

206

– silicon

Frank–van der Merve growth free radical initiated photopolymerization

126 f 205

freezing – compound semiconductors – silicon

73 f

Fresnel diffraction

184

fringing

581

front–end processing

612

full isolation by porous oxidized silicon (FIPOS)

367

425

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

functional partitioning, interconnections

666

functional units, cluster tools

471

furnace annealing

560

G gallium

141

gallium antimonides gallium arsenic phase diagram

78 141

gallium arsenides – annealing

563

– chemical vapor deposition

117

– compound semiconductors

71 f

– crystal pulling – device processing – device structures

88 495 394 ff

– dielectric constant

570

– doping

268

– epitaxial growth

124

– isolation methods

517

– liquid phase epitaxy

141

– melting point

76 f

493 ff

498 ff

525

– metal-oxide field-effect transistor

398

– metallization

583

– molecular beam epitaxy

161

– planar-doped barrier

347

– Schottky barriers

555

– thermal conductivity

591

gallium phosphides – annealing

563

– compound semiconductors

71 f

– melting point

gas immersion laser doping

442

gas panel, chemical vapor deposition

130

gas phase, chemical vapor deposition

136

gas phase diffusion

443

447

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

gas phase dry cleaning

473

gas phase silylation systems

245

gas source epitaxy (GSE)

513

gate definition, etching

321

gate dielectric stack

439

gate dielectrics

412

gate dimensions

493 ff

gate electrodes

449

gate etching

534

gate induced drain leakage (GIDL)

440

gate masks, DRAM etching gate oxide integrity (GOI) gate stacks, oxides/oynitrides

429 f

333 f 36

414 ff

474

479

433

gates – device processing

552 ff

– interconnections

652

– MOSFETs

362

generation-recombination sites, shallow junctions

440

germane clean

474

germanium

657

477

– chemical vapor deposition

117

– compound semiconductors

73 f

– crystal growth

96 f

– doping

505

– gallium arsenides

165

– melt growth

– metallization

581

– molecular beam epitaxy

146

– p-n junctions formation

442

– silicon damages

germanium-hydrogen bonds

159

germanium silicides, silicon devices

353

germanium silicide/silicon heterojunction internal photoemission detector

384

This page has been reformatted by Knovel to provide easier navigation.

Index Terms gettering

Links 53 ff

Gibbs energy, epitaxial growth

120

glass-ceramic materials

670

glass-transition temperature, printed wiring board resins

672

412 ff

gold – diffusion doping

525

– interconnections

458

– metallization

581 ff

– Schottky barriers

553 ff

– wire bonding

615 ff

gold-aluminum intermetallic compounds

584

gold diffusion, silicon

273

gold-indium/tin/germanium, ohmic metallization

548

gold/platinum/titanium system

585

gold-based alloys

494

goniometer

670

graded germanium silicide bipolar transistor grades, silicon

254 7f

gradient freeze technique, group III–V semiconductors

396

grain boundaries – compound semiconductors – crystal growth graphite

87 105 78

graphite components graphite heaters gravels

142 29 7

grid arrays, integrated circuit packaging

611

628 f

632

grinding – backside processing – silicon

591 ff 38 f

grooves – crystal growth

102

– die separation

597

group II transition elements

513

This page has been reformatted by Knovel to provide easier navigation.

Index Terms group II/V/VI elements, annealing

Links 562

group II–VI compounds

group III–V compounds

141

145

– device structures

394

– doping

270

– molecular beam epitaxy

146

– ohmic contacts

545

group V elements, doping

511

growth, silicon devices

414

growth behaviors, epitaxial

126

growth chamber, molecular beam epitaxy

148

growth chemistry, silicon chemical vapor deposition

146

498 ff

156 f

growth rates, dielectrics

572

Gunn type oscillations, resistors

578

H hardening, photoresists

201

hardness, silicon

345

heat dissipation, resistors

579

heat treatments, silicon devices

414

heating rates, annealing

560

Helmholtz energy

120

heptanone

233

heteroepitaxial growth

116

heteroepitaxy, silicon

365

heterointerfaces/structures

396

heterojunction bipolar transistor (HBT)

353

– diffusion doping

525

heterojunctions, silicon devices

159

352

heterostructure field-effect transistors (HFET)

397

400

heterostructure growth, liquid phase epitaxy

146

hexamethoxy methyl melamine (HMMM)

209

hexamethylcyclotrisilazane (HMCTS)

196

hexamethyldisilizane (HMDS)

196

HF etching, gate dielectrics

432

126

402

493 ff

528

234

This page has been reformatted by Knovel to provide easier navigation.

Index Terms HgCdTe, annealing

Links 563

hi-lo structure – IMPATT diodes – silicon

380 56

high-electron mobility transistor (HEMT)

397

high-frequency power amplifiers (HPA)

503

high-pressure liquid encapsulated Czochralski technique

400 f

493 ff

high-pressure oxidation (HIPOX)

375

high-temperature oxides, chemical vapor deposition

438

Hinshelwood-Langmuir reaction

140

hole burning, photoresists

238

hole concentrations

506

hole mobilities

499

hole trapping gate dielectrics

430

holes – interconnections

458

– metallization

448

– MOSFETs

364

hom*oepitaxial growth

116

hom*ogeneous field-effect transistors

360

hom*ojunction transitor

354

horizontal Bridgman (HB), group III–V semiconductors

396

horizontal growth host atoms, diffusion doping

71 ff

126

526

host lattice – doping

268

– ion implantation isolation

518

277

507

hot-electron transistors (HET) – resonant-tunneling

377

– silicon devices

357

hot spots, thin film resistors

580

hot-wall CVD reactors

132

hot-wall technology, compound semiconductors

hot zones, silicon pulling

This page has been reformatted by Knovel to provide easier navigation.

Index Terms hybrid circuit packages

Links 630 f

hybrid integrated circuits (HIC)

670

hydride based chemistry, SiH4/GeH4 growth

153

hydrogen, doping

505

hydrogen abstraction

206

hydrogen annealing

416

hydrogen bonding

468

hydrogen diffusion

273

hydrogen halides

213

hydrogen prebake

473

hydrogenation, dielectrics

571

hydroxy groups

196

I ideal system partitioning approach, interconnections

669

illumination-based imaging techniques

182

imaging, photolithography

182 ff

immersion etching

297

– doping

536

immersion ion implantation

443

impact ionization avalanche transit time (IMPATT) diode

346

234

380

impurities – annealing

562

– chemical vapor deposition

131

– compound semiconductors

70 f

– crystal growth – doping

74 f

99 500

– epitaxial growth – indium phosphides – silicon

114 ff 173 11

impurity layers, silicon devices

364

impurity profile, double diffusion front

512

152

impurity redistribution – diffusion doping

525

– silicon

8 ff This page has been reformatted by Knovel to provide easier navigation.

161

Index Terms

Links

in-line packages, integrated circuits

611

in situ dry cleaning

473

incorporation, epitaxial growth

632

124 f

indium – liquid phase epitaxy

141

– ohmic contacts

548

indium antimonides – compound semiconductors

71 f

– crystal pulling

– melting point

75 ff

indium arsenides – crystal pulling

88 f

– melting point

indium germanium phosphides

493 ff

indium phosphides – annealing

563

– chemical vapor deposition

117

– compound semiconductors

71 f

– crystal pulling

76 f

– device structures

394 ff

493 ff

– doping

498 ff

527

– ion implantation isolation

519

– melting points

– metallization

585

– metal-organic vapor phase epitaxy

170

– thermal conductivity

591

indium-tin, ohmic metallization

548

induced-base transistor (IBT)

357

induction heating, silicon

inductively coupled plasma-optical emission spectroscopy (ICP-OES)

195

inductively coupled plasma-optical mass spectroscopy (ICP-MS)

195

inductors, dielectrics

568

infrared detection capability, quantum effect devices

373

This page has been reformatted by Knovel to provide easier navigation.

Index Terms initiation nucleation, crystal growth initiation reactions, photopolymerization

Links 96 206 f

inner diameter circular saw

input-output (I/O) terminals

615

insertion force, integrated circuit packaging

636

insulated gate bipolar thyristor (IGBT)

356

insulating films, printed wiring board

674

integrated circuits (IC) – device processing

496

– fabrication

182

– interconnections

652 ff

integrated circuits (IC) packaging

607

integrated CMOS processing, rapid thermal

477

interdevice interactions, device processing

497

interlevel dielectric (ILD) layers

336

interconnection sytems

649

interconnections – doping

543

– metallization

456 f

– multichip packaging

638

interdiffusion

153

interface engineering

474

interface shape, crystal growth

494

557

585

interfaces – annealing

569

– epitaxial growth

119

– metal–silicon

359

interference pattern, photolithography

184 f

interlayer connections, metallization

582

interlayer dielectric (ILD) films, etching

325

interlayer isolation, device processing

567 ff

intermetal dielectric (IMD) layer, etching

328

intermetallic compounds, metallization

584

internal surfaces, epitaxial growth

119

This page has been reformatted by Knovel to provide easier navigation.

582

Index Terms inter-polysilicon oxide mask, DRAM etch processing

Links 335

interstitial clusters, silicon

interstitial impurities, Czochralski silicon

interstitial lattice sites

413

interstitials

269

507

413 f

intrinsic gettering intrinsic stacking faults

118

iodonium

212

ion beam lithography (IBL)

195

ion channeling – doping

281

– thin film transistors

368

ion depth, doping

505

508

ion implantation – doping

278 ff

– epitaxial growth

114

– group III–V semiconductors

396

– isolation

517 f

– MESFET

493 ff

– photolithography

183

– resistors

576

– Schottky barriers

556

– shallow junctions

440 ff

ion milling, metallization

586

ion projection lithography (IPL)

195

ion surface reactions, etching

300

ionic contaminants, silicon

494 ff

500

– diffusion

273

413

island growth, epitaxial

127

ISLAND process

425

isolation methods

494

– etching

504 ff

412

iron

– impurities

501

515

320 f

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

isolation methods (Cont.): – ion implantation – silicon devices

556 418 f

isomask, DRAM etching

332

isopropyl alcohol

432

isorotation, silicon pulling

isotopes, silicon

isotropy conditions, etching

295

J Joint Electron Devices Engineering Council (JEDEC) standards junction field-effect transistors (JFET)

624 348

360

397

525

540

junction leakage – metal-oxide semicondutors

439

– silicon devices

412

junction-to-air thermal resistance

621

junctions – device processing – doping

495 498 ff

– epitaxial growth

114

– Schottky barriers

552

– silicon devices

325

348 ff

K Kapton

633

ketocoumarines

206

kick-out mechanism, doping

276

kinematic susceptibility, silicon pulling

kinks

121

Knoop hardness

345

Knudsen cells – group III–V semiconductors

396

– molecular beam epitaxy

150

Knudsen number

133

This page has been reformatted by Knovel to provide easier navigation.

495

Index Terms KOH etching

Links 361

L laminar flow

133

laminated printed circuit board technology

670

Langmuir adsorption Langmuir probes

138 f 316

lapping – backside processing – silicon

593 39

large-scale integration (LSI) – integrated circuit packaging

611

– microlithography

205

laser ablation

597

laser diodes

404

laser interferometry, endpoint monitoring

307 f

laser planarization

469

laser trimming

580

lateral straggle, ion implantation

279

lattice constants – device structures

394

– doping

268

lattice damage

571

lattice matched heteroepitaxial growth

129

lattice pulling/latching, liquid phase epitaxy

146

277

500

lattice structures – compound semiconductors

– silicon

layer-by-layer growth, epitaxial

126 f

layers – device processing

497

– epitaxial growth

114

– silicon

lead solvents, liquid phase epitaxy

141

leading edge chips

654

This page has been reformatted by Knovel to provide easier navigation.

Index Terms leadless chip carrier

Links 611

623

632

leakage – backside processing

594

– dielectrics

572

– ion implantation isolation

520

– silicon-induced

365

leakage currents – gas phase diffusion

447

– gate oxides

434

– silicon devices

412

ledges, epitaxial growth

121

Levenson-type phase shift mask technology

191

Lewis acids

207

lifetime, silicon devices

412

liftoff processes

581 ff

– ohmic contacts

548

– photoresists

203

– Schottky barriers

556

LIGA (Lithographie, Galvanoformung, Abformung) process

188

587 ff

lightly doped drain (LDD) – device processing

502

– DRAM

336

– MOSFETs

363

– etching

321

– p-n junctions formation

446

lightly doped layers

540

line compounds, liquid phase epitaxy

141

linewidth – chemically amplified resists

226

– photolithography

192

Linshard–Scharft-Schiott (LSS) theory

280

liquid encapsulated Czochralski (LEC) pulling – compound semiconductors

– group III–V semiconductors

396

86 f

This page has been reformatted by Knovel to provide easier navigation.

Index Terms liquid encapsulation technique, compound semiconductors liquid phase epitaxy (LPE) – compound semiconductors – doping

Links 73 119 78 513

– epitaxial growth liquid phase silylation systems

140 ff 249 f

lithography see: photolithography lo-hi-lo structure

380

local oxidation of silicon (LOCOS)

363

low-impurity channel transistor (LICT)

476

low-insertion force (LOI), integrated circuit packaging

636

low-noise amplifiers (LNA)

503

low-pressure, reactive ion etching

301

413

418 f

low-pressure chemiacl vapor deposition (LPCVD) – gate oxides

438

– silicon

low-pressure hot wall CVD reactors low-pressure liquid encapsulated Czochralski technique

132 ff 86

low-temperature buffer, doping

525

low thermal budget, diffusion doping

527

LTO, chemical vapor deposition

438

luminescence efficiency, molecular beam epitaxy

162

M machine-related metrology, etching

312

magnesium acceptors – gallium arsenides

165

– indium phosphides

173

magnesium doping

529

– silicon

magnetic Czochralski silicon

magnetic pulling

magnetically enhanced reactive ion etching (MERIE)

304

magnetics metrology, etching

314

magneton enhanced ion etching (MIE)

247

414

This page has been reformatted by Knovel to provide easier navigation.

Index Terms magnetron tools, etching

Links 300

304

manganese – doping

500

– gallium arsenides

165

manufacture processes

291

mask aligner

186

mask level

497

masks – backside processing

593

– DRAM

332 ff

– etching

541

– photolithography

182 ff

mass flow controllers (MFC)

313

mass spectroscopy

309

mass transport CVD reactors master image, photolithography

132 ff 182

material properties – compound semiconductors – device structures

78 394 f

– printed wiring board resins

672

– silicides

455

mechanical damage, silicon

mechanical parameters, wire bonding

616

medium scale integration (MSI)

611

melamine, acid hardening resists

210

493

500

56 f

75 f

78 f

melt growth – compound semiconductors – germanium

77 ff 71

– liquid phase epitaxy melt surface evaporation, Czochralski silicon

141 46

melting points – compound semiconductors

– doping

500

– liquid phase epitaxy

141

This page has been reformatted by Knovel to provide easier navigation.

413

Index Terms

Links

melting points (Cont.): – noble metals

458

– silicon

22 ff

memory cards, integrated circuit packaging

611

meniscus contact, crystal growth

mercury, zone refining

632

mercury cadmium tellurides (MCT) – chemical vapor deposition

117

– crystal growth

mercury selenides, melting point

mercury tellurides

73 f

mercury/rare gas discharge lamp, photolithography

184

187

mesa etching – isolation methods

515

– resistors

576

metal etching

329

metal-insulator-metal (MIS) structures, Schottky barriers

554

metal-insulator-oxide semiconductor (MIOS) memory

369

metal ion-free (MIF) developers

200

metal mask, DRAM

333

337

metal-organic chemical vapor deposition (MOCVD)

382

494

– doping

513

531

metal-organic molecular beam epitaxy (MOMBE)

151

metal-organic vapor phase epitaxy (MOVPE)

137

metal-oxide semiconductor field-effect transistor (MOSFET)

114

– doping

268

– photolithography

183

metal-oxide semiconductor structures

360

metal–semiconductor field-effect transistor (MESFET)

360

metal–silicon contacts metal work function, Schottky barriers

348

362 ff

394 f

398 f

358 f 553

metallization – device processing

494

– dielectric layers

568

581 ff

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

metallization (Cont.): – integrated circuit packaging

619 f

– silicon devices

412

metallurgical grade silicon

7 ff

methacrylate based photopolymerization

205

methoxybutyl acetate

233

methylene groups, photolithography

218

metric tape automated bonding

611

632

296 ff

305 ff

metrology, etching Michler ketone

206

microcracking

571

microdefects

448 ff

microinterconnects

612 ff

microvacuum field emitter, silicon devices

371

microwave diodes

380

microwave etchers

300

638

304

migration – diffusion doping

525

– silicon devices

414

millions of instructions per second (MIPS), interconnections

653

misfit dislocation

118

mitigation

497

mobility – doping

498

– gate oxides

434

– group III–V semiconductors

395

modular partitioning, interconnections

667

modulation-doped field-effect transistor (MODFET)

370 ff

modulation transfer function (MTF), photolithography

186

molecular beam epitaxy (MBE)

117

– doping

513

– gallium arsenide

347

– group III–V semiconductors

396

– IMPATT diodes

382

397

146 ff

494

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

molecular beam epitaxy (MBE) (Cont.): – laser diodes

405

– silicon devices

352

molecular contaminants, silicon

molecular flow, chemical vapor deposition

133

molybdenum

670

monitoring, etching

305 ff

monolithic microwave integrated circuits (MMIC)

398

Mott–Gurney law

347

mounting, backside processing

591 f

multichip modules (MCM) – integrated circuit packaging

611

– interconnections

669 ff

multichip packaging

610 ff

multilayer masking

593

multilayer metallization

494

multilayer printed wiring board (MLB)

674

– interconnections

659

multilayer resists, silicon-containing

240

multilevel films etching

479

multilevel interconnections

463

multiple epitaxial layers

142

multiple implant isolation profile

520

multiple metallization layers

568

multiple photoresists, doping

541

multiple quantum-well detector

377

multiple wire saw

mushroom gates

558

632

637

637 ff

582

N n-channel devices, silicon

362

n-i-n diodes

346

n-p heterojunction

402

n-p junction – silicon devices

350

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

– epitaxial growth

114

n-type behavior, doping

500

n-type channel

397 f

n-wells – DRAM

331

– silicon devices

414

193-nanometer photolithography natrium diffusion near ultraviolet projection systems

424

229 f 12

273

189

nearest neighbors – doping

269

– epitaxial growth

119

neck fracture

needle eye technique

negative differential resistance (NDR)

379

negative tone resists

182

negative tone silicon bilayer photoresists

242

network interconnections

669

neutron damage, ion implantation isolation

521

neutron transmutation doping (NTD)

204 f

nickel – backside processing

596

– doping

500

– Schottky barriers

553

nickel chromide

580

nickel diffusion, silicon

273

nickel–germanium–gold compositions, ohmic contacts

494

551

nickel sputtering

459

nitrene

204

nitridation, gate oxides

436

nitride clad LOCOS (NCL)

421

nitride etching

296

nitride spacers, device isolation nitrides

412 f

300

419 ff 477

This page has been reformatted by Knovel to provide easier navigation.

Index Terms nitrobenzyl sulfonate esters

Links 214

nitrogen – doping

505

– float-zoned silicon

– ion milling

586

nitroso compounds, photocrosslinking

204

noble metals

458

noise, multichip packaging

638

nonvolatile memory

368

Norrish cleavage notching, reflective

206 f 238

novolaks – acid hardening resists – photoresists

211 205 ff

214

219

241 nucleation – compound semiconductors

– crystal growth

– epitaxial growth

127

– oxygen in silicon

– silicon devices

414

185

189

– doping

525

543 ff

– metallization

583

– resistors

577

ohmic metal deposition

556

Ohnishi number

230

one-sided abrupt p-n junctions

380

onium salts, standard

213

open-tube diffusion

511

numerical aperture

O ohmic contacts

optical emission spectroscopy (OES) optical mask aligner

306 ff

316

186

This page has been reformatted by Knovel to provide easier navigation.

229

Index Terms

Links

optical proximity correction (OPC)

191

ortho/para link configuration ratio

220

outline pattern transfer imaging (OPTIMA)

191

overpressure atmosphere, annealing

563

oxalic acids

218

oxidation-induced stacking faults (OISF)

414

oxide breakdown

412

oxide thickness, gate dielectrics

429 f

oxides – etching

301

– gates

324

– low pressure chemical vapor deposition

477

– spacers/collars

479

oxirane

207

474

oxygen – Czochralski silicon

46 ff

– doping

505

– ion implantation isolation

519

– silicon

oxygen inhibition, photopolymerization oxygen vacancy A centers

509

273

206 53

oxynitrides – dielectrics

569

– doping

512

– gate stack

474

P p-channel devices, silicon p-i-n junction

362 498 f

p-n junctions – doping

498 f

– IMPATT diodes

380

– liquid phase epitaxy

142

– Schottky barriers

552

525

540

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

– silicon devices

348 ff

p-n-p bipolar transistors

350

p-n-p-n diodes

355

p-type dopants

268

p-wells – DRAM

334

– silicon devices

414

package attachement

424

631 ff

packaging – integrated circuits – interconnections

607 654 ff

packaging materials, dielectric constants

633

pad mask, DRAM etching

333

337

palladium – interconnections

670

– metallization

584

– Schottky barriers

555

partitioning, interconnections

665

passivated emitters, solar cells

386

passivation – annealing

561

– Schottky barriers

557

passive devices, doping

499

pattern inspection, photoresists

200

pattern repair, photolithography

195

patterning – etching

295

– interconnections

668

– metallization

582

– ohmic contacts

548

– printed wiring board

674

– resistors

579

– Schottky barriers

557

pelletization, silicon

329

585

This page has been reformatted by Knovel to provide easier navigation.

Index Terms penetration depth, doping periodic crystal growth

Links 288 21

permeable base transistor (PBT)

360

permittivity, printed wiring board resins

672

Pfann equation

phase diagrams – gold–gallium

550

– ohmic contacts

545

phase shift mask technology (PSMT)

191

phenolic dielectrics

671

phenolic resins

214 f

phosphine – indium phosphides – silicon

170 14

phospho-silicate glas (PSG) phosphorus diffusion

270 9

phosphorus doping

505

– photolithography

183

– silicon

phosphorus vapor pressures

564

photo enhanced chemical vapor deposition

574

photoacid generators (PAG)

208

– deblocking

221

– diazo resists

234

photoactive compounds (PAC)

204 f

photocrosslinking

204

photodetectors

382

photofragmentation

206

photoinitiators, crosslinking

273 f

413

212

214 f

205 ff

photolithographic patterning – metallization

582

– ohmic contacts

548

photolithography

177

– Schottky barriers

556

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

photoluminescence

173

photonic diodes

380

photoresist ashing

430

photoresist patterning

494

photoresist processing

195 ff

497

photoresists – chemistry

203 ff

– doping

541

– etching

327

– ion implantation isolation

521

– photolithography

182

photoresists masking, backside processing

593

photosensitive film solder masks

674

physical deposition, epitaxial growth

117

physical etching

298

532

physical properties – epitaxial growth

114

– group III–V semiconductors

395

– printed wiring board resins

672

– silicon-based growth

137

physical vapor deposition (PVD)

471

piezoelectric effect – dielectrics

570

– resistors

578

pin grid array

611

pin-to-hole soldering

631

pinhole leakage

594

pinning

553

Piper–Polich technique

628

632

pitting

270

planar doped barrier (PDB)

347

planarization – etching

326 f

– interconnections

463

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

planarization (Cont.): – metallization

448

– photoresists

201 f

– shallow trench isolation

423

plasma arc technique

plasma-assisted chemical etching

plasma-assisted surface decomposition

537

plasma chemical vapor deposition (PCVD)

241

plasma-enhanced chemical vapor deposition (PECVD) – dielectrics

572

– quantum effect devices

375

plasma etching

295

– doping

537

– metrology

312

315

plasma immersion ion implantation (PIII)

443

448

plasma sources, photolithography

187

plasma sputtering

531

plastic ball grid arrays

611

298 f

301

632

plastic deformation – device isolation – silicon

419 38

plastic integrated circuit packaging

620

plastic leaded chip carriers

611

plastic temperature, silicon

plated through-holes (PTH)

675

632

plating – backside processing

596

– liftoff processes

589

– printed wiring board

674

platinum – metallization – Schottky barriers

584 553 ff

plug-in card

656

plug-in hybrid circuit package

630

663

This page has been reformatted by Knovel to provide easier navigation.

537

Index Terms

Links

plug technology, interconnections

459

plugs, backside processing

596

point defects – doping

268

– silicon devices

Poisson equation

346

Poisson modulus

Poisson ratio

413

277

polarity – crystal growth

– photolithography

182

– photoresists

204

polishing – backside processing

591

– photoresists

203

– silicon

39 f

polyamides dielectrics, interconnections

672

poly-buffer LOCOS

419 f

polycarbonate, photoresists

233

polycide structure, dopant diffusion

451

polyester dielectrics, interconnections

672

polyhydrostyrene (PHS), photocrosslinking

205

polyhydroxystyrene, photolithography

221

polyimides – dielectric constant

570

575

– DRAM mask

334

337

– interconnections

672

– photocrosslinking

205

– photoresists

241

poly(cis-isoprene), photocrosslinking

204

polymer binders, photocrosslinking

204

polymer degradation, photoresists

204

poly(methyl isopropenyl ketone) (PMIPK)

232

poly(methyl methacrylate) (PMMA)

232

This page has been reformatted by Knovel to provide easier navigation.

Index Terms poly(methylglutarimide) (PMGI) polysilicon

Links 232 6f

– DRAM

475

– endpoint monitoring

307

– etching

300

– low-pressure chemical vapor deposition

477

– nonvolatile memory

369

– solar cells

386

polysilicon-encapsulated local oxidation (PELOX)

421

polysilicon-polycide, DRAM etching

337

polysulfone dielectrics

672

positive-tone photoresists

182

– silicon bilayer

243

322 ff

214

post-exposure bake (PEB) – acid hardening resists

208

– photolithography

199 f

post-optical lithography

193 f

potential-effect devices

345 ff

power distribution, multichip packaging

639

power-pin relationship

621

Prandtl number prebake, dry cleaning

30 473

precipitation – interstitial oxygen

– liquid phase epitaxy

141

– silicon

7 ff

predeposition, doping

270

preoxidation cleaning

430 f

pressure, etching pressure balancing technique, compound semiconductors pressure dependence, doping pressure reduction, silicon pulling

412 f

301 85 270 29

Preston equation

467

printed wiring board (PWB)

663

669 ff

This page has been reformatted by Knovel to provide easier navigation.

Index Terms printing, photolithography

Links 185

process control see: control process flow – backside

592

– FET fabrication

496

– ISLAND method

426

– poly buffer LOCOS

422

– polysilicon encapsulated local oxidation

422

process-induced damage

430 f

process lattitudes, photolithography

198

process-related measurements, etching

315

process steps – integrated circuit packaging

612 ff

– liquid phase epitaxy

143

– photolithography

183

– tape automated bonding

617

profile modification technique (PROMOTE)

234

projected transverse straggle, ion implantation

279

projection printing

185

propagation delay, integrated circuit packaging

633

propagation reactions, photopolymerization proportional integral derivative (PID) control proximity printing

189 f

206 f 318 184 ff

pseudomorphic high-electon mobility transistors (pHEMT)

493

pullers, silicon

16 f

– compound semiconductors

70 ff

– photoresists

195 f

purity

– silicon

pyrolysis

14 f

pyrolytic boron nitride (PBN) – compound semiconductors – molecular beam epitaxy

78 151

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

Q quad flatpack

611

quality control, photoresists quantum effect devices

627

632

195 f 345

373 ff

quantum wells – MOSFETs

364

– silicon devices

373

quartz

quench anneal technique, mercury cadmium tellurides quinone dervatives, photopolymerization

92 206

R rack-and-frame style packaging

662

radiation damage

521

radiation effect, silicon

radiation-induced solubility, photoresists

204

radical recombination, photocrosslinking

205

radicals, photopolymerization radio frequency metrology

206 f 310 ff

random crystallization

random walk-well model, oxygen in silicon

316

rapid thermal annealing (RTA) – device processing

560 ff

– doping

502

– metallization

449

– ohmic contacts

549

– shallow junctions

440

rapid thermal chemical vapor deposition (RTCVD)

443

rapid thermal multiprocessing (RTMP)

475

rapid thermal nitridation (RTN)

436

rapid thermal oxidation (RTO)

474

506

527

rapid thermal processing (RTP) – cluster tool technology – gate oxides

471 f 433 ff

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

rapid thermal processing (RTP) (Cont.) – silicon chemical vapor deposition Rayleigh convection Rayleigh model

153 91 185

RCA clean – gate dielectrics – silicon contamination

431 40

reactants, chemical vapor deposition

117

reaction rate controlled etchants

535

reactive evaporation, metallization

453

reactive ion beam etching (RIBE)

537

reactive ion etching (RIE)

296 ff

130

301

– chemically amplified resists

230

– cluster tool technology

471

– doping

537

– gate dielectrics

430

– photoresists

202

247

130 f

152

reactor configurations – chemical vapor deposition – dielectrics

573

– silicon impurities recessed sealed sidewall field oxidation (RESSFOX)

13 421

recombination – ion implantation isolation

520

– shallow junctions

440

– silicon devices

349

rectifier diodes failure

rectifying contacts

552

rectifying structures

347

reflection high-energy electron diffraction (RHEED)

147

reflection suppression, photoresists

237

163

refraction index – endpoint monitoring

307

– photoresists

239

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

refractory metals – metallization

585

– molecular beam epitaxy

151

refractory oxides reduction

relief image, photolithography

182

remote plasma generation

304

Rent’s rule

620 f

repair, integrated circuit packaging repeatability, etching

640 ff 297

reproducibility – annealing

569

– device processing

493

residual gas analysis (RGA) resist spin-on

309 f 464

resistance – contact etching

325

– integrated circuit packaging

616

– metallization

452

– ohmic contacts

551

– resistors

577

– group III–V semiconductors

395

621

resistivities – noble metals

458

– silicides

450

– silicon pulling

resistors

576 ff

resists

182 ff

– coating

30 ff

196

– deposition

195 ff

– etching

331

– profiles

200

234

resolution – photolithography

184 f

– photoresists

204 f

This page has been reformatted by Knovel to provide easier navigation.

Index Terms resonant-tunneling diode (RTD)

Links 375 f

resonant-tunneling hot-electron transistor

377

response surface method (RSM), etching

305

reverse bias, silicon devices

348

reverse leakage, rectifier diodes

Richardson constant

553

rigid printed wiring board

673

ring-opening, photopolymerization

207

ring parameters, novolaks

229

rocking curve measurements, silicon Ryton

41 633

S S pits

SALICIDE formation – cluster tool technology

472

– metallization

456

– p-n junctions

443

sands

sandwich structures, metallization

585

sawing – die separation

597

– integrated circuit packaging

612

– silicon

SC1 clean

SC2 clean

scanning electron microscopy (SEM)

201

– AZR PN 114

188

– etching

326

scanning tunneling microscope (STM)

123

scanning tunneling microscope aligned field (SAFE) concept

194

431 f

scattering with angular limitation projection electron beam lithography (SCALPEL)

195

Schottky barriers – device processing

552 ff

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

Schottky barriers (Cont.) – doping

498

– epitaxial growth

115

– field-effect transistors

397

– silicon devices

358

screen-printed cover coats

674

scribe and cleave

597

sealed interface local oxidation (SILO)

419

– isolation etching

320

sealed sidewall trenching (SST)

425

sealing

544

619 ff

second phase hardening, silicon

secondary ion mass spectrometry (SIMS)

197

– silicides/silicon interfaces

445

– silicon devices

352

segregation – compound semiconductors

– crystal growth

102

– diffusion doping

527

– impurities

– oxygen in silicon

75 f

selective deposition/growth processes, cluster tool technology

479

selective doping

265

selective epitaxial growth (SEG)

420

selectivity, interconnections

462

selenides

73 f

76 f

selenium

500

505

selenium donors

424

173 +

self-aligned implantation for n layer technology (SAINT)

555

self-aligned refractory gate integrated circuit process (SARGIC)

555

self-interstitials, silicon semiconductor grade polycrystal silicon

53 11 ff

semiconductor laser diodes

402

semi-insulating characteristics

500

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

semi-insulating indium phosphides

173

sensitivity, photolithography

197

204

separation-by-implantation of oxygen (SIMOX)

367

426

– cluster tool technology

476

479

– doping

540

– silicon devices

412

shallow junctions

shallow trench isolation (STI)

420 f

side groups, photocrosslinking

205

439 ff

sidegating – device processing – doping

497 522 f

sidewall mask isolation (SWAMI)

320

Siemens process

11 f

signal distribution functions, interconnections

668

signal termination, multichip packaging

639

silane formation, chemical vapor deposition

136

silane route

11 f

419

silica – compound semiconductors

– dielectric constant

570

silicide–silicon contacts

359

silicides

412

– etching

322

– metallization

455

– p-n junctions formation

442

– resistivites

450

581

silicon – bipolar junction transistor

402

– chemical vapor deposition

117

– crystal growth

96 f

– epitaxial growth

124

– etching

330

– interconnections

670

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

silicon (Cont.): – low-pressure chemical vapor deposition – melting point

477 78

– molecular beam epitaxy

146

– p-n junctions formation

442

– thermal conductivity

591

– wire bonding

616

silicon-added bilayer resists (SABRE)

248

silicon-based integrated circuits

295

silicon carbide

117

silicon–carbon bonds

154

silicon chemical vapor deposition

152

silicon device processing

407

silicon device structures

341

– epitaxial growth

114

silicon dioxide – epitaxial growth

114

– photolithography

183

silicon donors – diffusion doping

525

– gallium arsenides

165

– indium phosphides

173

silicon doping

500 f

– group III–V semiconductors

276

505

396

silicon-hydrogen bonds – chemical vapor deposition

159

– gate oxides

436

silicon nitrides – dielectric constant

570

– doping

512

– endpoint monitoring

307

silicon-on-insulator (SOI)

366

– device isolation – quantum effect devices

418 f

425 ff

377

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

silicon oxides

307

silicon–oxygen bonds

154

silicon photodetectors

382

silicon processing silicon–silicon bonds

512

1 154

silicon surfaces – doping

270

– etching

324 f

silicon wafers

182

silsesquioxane

242

silver – interconnections

458

– Schottky barriers

553

silver-indium, ohmic contacts

548

silylation systems

245

silyl ethers

196

single-crystal silicon

240

single-photon processes

204

single-sided circuits, printed wiring board

676

single-wafer cluster tool technology

471 479 ff

singlets, photocrosslinking

204

sinks, etching

297

site selection, impurities

563

sitegating

514

sites/sinks gettering slice preparation

249

16 ff

single-layer photoresists

single-wafer integrated processing

670

53 106 ff

slicing

sliding

141

slip dislocations

small-angle neutron scattering (SANS)

small-outline integrated circuits

611

solar cells

385

628

632

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

solder bump

614

solder flow, backside processing

594

618 ff

631

solder masks – photopolymerization

205

– printed wiring board

674

solid phase diffused drain (SPDD)

446

solid phase epitaxy

286

solid state diffusion

114

solubility, photoresists solute distribution, crystal growth

204 f 99

solvents – liquid phase epitaxy

141

– photoresists

233

spacers, cluster tool technology

479

spiking – ohmic contacts

548

– Schottky barriers

555

spin coating

196

241

spin-on-glass (SOG) – etching

327

– interconnections

465

spin-on-oxides, p-n junctions formation

442

spray processing

298

sputter etching

298

327

531

sputtering – dielectrics

571

– doping

537

541

– metallization

453

586

– photoresists

241

– Schottky barriers

554

SRH generation-recombination sites

440

stack etching

323

stacked-gate oxides stacked inductors

438 f 568

This page has been reformatted by Knovel to provide easier navigation.

Index Terms stacked nitride/oxide films

Links 474

stacking faults – epitaxial growth – silicon

118 54

412 f

standing wave effects – photolithography

197

– photoresists

237

stannium – doping

500

– ohmic contacts

548

statistical process control (SPC) – device processing

494

– etching

319

status interconnections

669

step-bunching phenomenon

127

step-flow growth, epitaxial

126 f

steppers, photolithography

187

stirring – crystal growth

– doping

523

– silicon

Stockbarger technique

storage dielectrics

475

storage stability – chemically amplified resists – photoresists

226 195 f

straggle, ion implantation strains, silicon

279

507

Stranski–Krastanov growth

127 f

stress deformation

stresses, annealing

566

striations

stripping – photolithography

182 f

This page has been reformatted by Knovel to provide easier navigation.

Index Terms – photoresists

Links 201 f

structural defects

118

structural properties, epitaxial growth

114

structures – compound semiconductors

– crystal growth

submicrometer metal-oxide semiconductor field-effect transistor

362 f

substitutional atoms

507

substitutional diffusion

269

substitutional impurities

substitutional lattice sites

413

substrate choice, multichip packaging

637

substrate wafer, epitaxial growth

114

subsurface damages

sucrose pelletization

Sues reaction

216

sulfides

sulfonic acids

213

sulfonium

212

sulfur

500

sulfur donors

173

superconducting cryomagnets

505

supercooling – compound semiconductors

– crystal growth

– silicon

supersaturation – chemical vapor deposition

136

– liquid phase epitaxy

143

– silicon

suppliers, photoresists

233

surface adsorption, chemical vapor deposition

138

surface contamination, silicon

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

surface damage – compound semiconductors – silicon

107 41

surface decomposition, plasma-based

537

surface integrity, doping

512

surface leakage, ion implantation isolation

520

surface migration, epitaxial growth

117

surface reactions, chemical vapor deposition

132

surface temperatures, annealing

562

surface texturing, solar cells

387

136

surfaces – epitaxial growth

119

– silicon chemical vapor deposition

152

susceptor reactors, dielectrics

573

124

swelling – photocrosslinking

205

– photoresists

246

synchroton sources, photolithography

188

syringe pulling

T T-gate structures – e-beam exposed

586

– Schottky barriers

558

tank formation, rapid thermal processing

477

tantalum – metallization

581

– molecular beam epitaxy

151

tantalum nitride

580

tantalum silicides

323

tape automated bonding (TAB)

611

target etching time

298

Teal–Little pulling

tearing

616 f

632

589

technical constaints, melt growth

77 ff

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

Teflon

633

tellurides

73 f

tellurium – compound semiconductors

– doping

500

– indium phosphides

173

– ultra-pure

– zone refining

temperature gradient zone melting (TGZM)

temperatures – annealing

562

– crystal growth – doping

96 270 ff

– gate oxides

434

– liquid phase epitaxy

143

– silicon

TEOS, chemical vapor deposition

438

terephthal aldehyde tetramethyl acetal

210

termination reactions, photopolymerization

534

413

205 f

terraces kinks ledges (TKL) model

121

tetrafluoroethylene dielectrics

672

tetramethoxy methyl glycoluril (TMMGU)

209

tetramethylammonium hydroxide (TMAH)

200

thermal budgets – annealing

562

– doping

501

thermal conduction modules (TCM)

637

thermal conductivity

591

thermal convection – Czochralski silicon – silicon pulling thermal donors, Czochralski silicon thermal effects, resistors thermal management, integrated circuit packaging

46 30 f 47

52 f

579 621 ff

639

This page has been reformatted by Knovel to provide easier navigation.

Index Terms thermal metrology, etching thermal neutron capture

Links 315 19

thermal nitridation

453

thermal oscillations, silicon

21 f

thermal pyrolysis

14 f

thermal resistance

616

thermal shock, silicon thermal transport, CVD reactors

26 132 ff

thermodynamic properties, silicon-based growth

137

thermodynamics, epitaxial growth

119

thermoresins, interconnections

671

thick films, integrated circuit packaging

633

thickness variation, silicon

641 f

thin-film multilayers, interconnections

670

thin-film resistors

579

thin-film transistors (TFT)

367

thin films, epitaxial growth

114

thin gate oxides

429

thin nitride etching

296

thixantones

206

three-components systems, photoresists

226

three-level interconnects, metallization

582

three-stage oxygen precipitation

621

118

130

300

through-hole hybrid package

630

through-hole soldering

631

thyristors

348

time-dependent dielectric breakdown, silicon devices

416

time–temperature profile, rapid thermal multiprocessing

476

time–temperature sequences, doping

501

355 f

tin – gallium arsenides

165

– indium phosphides

173

tipping

141

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

titanium – backside processing

596

– metallization

453

– Schottky barriers

553 ff

– thin film resistors

580

titanium-based gates

558

titanium diffusion, silicon

413

titanium oxides

570

titanium-platinum-gold system

555

titanium silicides

455

titanium-tungsten/gold layers

585

titanium-tungsten nitrides

452

tolerances, gate etching

321

top antireflective coatings (TARC)

239

481

484

top metal contact – MOSFETs

362

– solar cells

386

top surface imaging

245

total indicator reading (TIR)

total thickness variation (TTV), silicon

transient charging

523

transition elements, doping

513

transition flow, chemical vapor deposition

133

transition metals, silicon contamination transmission coefficient, quantum effect devices

412

376

transport kinetics – chemical vapor deposition – epitaxial growth trap mobile silicon self-interstitials

132 124 f 53

trapping – crystal growth

101

– doping

523

– gate dielectrics

430

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

travelling heater method (THM) – compound semiconductors

– mercury cadmium tellurides

trench capacitor

334

trench etching

301

576

420 f

515

trench isolation, silicon devices trenches, liftoff processes

588

triazine dielectrics

671

triethyl indium precursors

170

trifluoromethane sulfonate

213

triisobutyl aluminum (TIBA)

460

trimethyl indium precursors

170

trimethylsilyldiethylamine (TMSDEA)

196

trimming, thin film resistors

580

triodes

372

triplets, photocrosslinking

204

tungsten – etching

329

– interconnections – metallization

460 f

670

581 ff

– Schottky barriers

553

tungsten-silicon, multilayer structures

558

tunneling – etching

300

– nonvolatile memory

369

– ohmic contacts

545

– quantum effect devices

375 f

twinning – compound semiconductors – crystal growth – silicon

87 102 26

two-component resists, deblocking

222

This page has been reformatted by Knovel to provide easier navigation.

Index Terms

Links

U ultra-high vacuum (UHV) – epitaxial growth

117

– molecular beam epitaxy

146

ultra-high vacuum chemical vapor deposition (UHV/CVD) ultra-large scale integration (ULSI) manufacturing

352 ff 45

ultra-large scale integration (ULSI) patterns

187

ultra shallow junction formation

476

ultrapure polysilicon

6 ff

ultraviolet lithography ultraviolet radiation, chemical vapor deposition

125

412

189 ff 136

undercutting – etching

298

– liftoff processes

588 f

– photoresist

532

underlying films, damage

305

unified defect model

554

Union Carbide process

14 f

urea

210

V V-groove etch figure

532

vacancies – doping

507

– epitaxial growth

118

– ion implantation

284

– silicon

vacuum metrology, etching

413

313

valence band – group III–V semiconductors

395

– hot-electron transistor

379

– silicon devices

352

Valox

633

vapor phase epitaxy

513

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Index Terms

Links

vapor pressure – annealing

563

– compound semiconductors

78 f

– molecular beam epitaxy

146

vertical Bridgman technique

vertical gradient freeze technique

vertical growth, compound semiconductors

71 ff

very high speed integrated circuits (VHSI)

194

359

365

very large scale integration (VLSI) – doping

278

– etching

329

– interconnections – silicon

652 ff 345 f

via etch/patterning

557

via holes, metallization

448

vias, backplane connections

581

viscosity, silicon pulling viscous flow, chemical vapor deposition

30 133

vitreous silicides

voids

volatility – chemical vapor deposition

137

– compound semiconductors

– group II/V/VI elements

562

Volmer–Weber growth

127

W wafer dicing

612

wafer fabrication

493 f

wafer preparation – DRAM etching – silicon

331 36 ff

wafering, compound semiconductors

106 ff

wafers – epitaxial growth

114

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Index Terms – photolithography – silicon

Links 182 6

wedge option, SEMI US

532

wells – DRAM etching

331

– MOSFETs

364

– rapid thermal processing

477

– silicon devices

414

wet chemistry, isolation methods

516

wet cleaning – cluster tool technology

473

– gate dielectrics

432

wet etching

295

– doping

495

532 ff

– shallow trench isolation

423

wet sinks, etching

297

wetting, epitaxial growth

127

Wigner-Seitz approximation wire bonding

50 612 ff

wires, quantum effect devices

373

wiring capability, interconnections

658

Wolff rearrangement, photoresists

216

writing techniques, photolithography

182

wurtzite

641

193 f

X X-ray double crystal diffractometer X-ray stepper, photolithography

41 187

Y Young modulus

277

Z Zeigler growth

zeolites

14 This page has been reformatted by Knovel to provide easier navigation.

413 ff

Index Terms zero insertion force (ZIF) zinc doping

Links 636 500 f

– group III–V semiconductors

505

525

396

zinc acceptors – gallium arsenides

165

– indium phosphides

173

zinc diffusion

276

zinc impurities

173

zinc selenides – compound semiconductors

71 ff

– crystal growth

– melting point

zinc sulfides

zinc tellurides

zincblende structure – compound semiconductors

– crystal growth

– etching

532

– isolation methods

515

zone melting

zone melting recrystallization (ZMR) zone refining

367 71

74 f

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Handbook of Semiconductor Technology, Volume 2 - PDF Free Download (2024)

References